FastISel.h revision 76ad43c6e1619ed4c087b8ccb2cd573eb9d7093e
1//===-- FastISel.h - Definition of the FastISel class ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the FastISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_FASTISEL_H 15#define LLVM_CODEGEN_FASTISEL_H 16 17#include "llvm/ADT/DenseMap.h" 18#include "llvm/CodeGen/ValueTypes.h" 19#include "llvm/CodeGen/MachineBasicBlock.h" 20 21namespace llvm { 22 23class AllocaInst; 24class Constant; 25class ConstantFP; 26class FunctionLoweringInfo; 27class Instruction; 28class LoadInst; 29class MachineBasicBlock; 30class MachineConstantPool; 31class MachineFunction; 32class MachineInstr; 33class MachineFrameInfo; 34class MachineRegisterInfo; 35class TargetData; 36class TargetInstrInfo; 37class TargetLibraryInfo; 38class TargetLowering; 39class TargetMachine; 40class TargetRegisterClass; 41class TargetRegisterInfo; 42class User; 43class Value; 44 45/// FastISel - This is a fast-path instruction selection class that 46/// generates poor code and doesn't support illegal types or non-trivial 47/// lowering, but runs quickly. 48class FastISel { 49protected: 50 DenseMap<const Value *, unsigned> LocalValueMap; 51 FunctionLoweringInfo &FuncInfo; 52 MachineRegisterInfo &MRI; 53 MachineFrameInfo &MFI; 54 MachineConstantPool &MCP; 55 DebugLoc DL; 56 const TargetMachine &TM; 57 const TargetData &TD; 58 const TargetInstrInfo &TII; 59 const TargetLowering &TLI; 60 const TargetRegisterInfo &TRI; 61 const TargetLibraryInfo *LibInfo; 62 63 /// The position of the last instruction for materializing constants 64 /// for use in the current block. It resets to EmitStartPt when it 65 /// makes sense (for example, it's usually profitable to avoid function 66 /// calls between the definition and the use) 67 MachineInstr *LastLocalValue; 68 69 /// The top most instruction in the current block that is allowed for 70 /// emitting local variables. LastLocalValue resets to EmitStartPt when 71 /// it makes sense (for example, on function calls) 72 MachineInstr *EmitStartPt; 73 74public: 75 /// getLastLocalValue - Return the position of the last instruction 76 /// emitted for materializing constants for use in the current block. 77 MachineInstr *getLastLocalValue() { return LastLocalValue; } 78 79 /// setLastLocalValue - Update the position of the last instruction 80 /// emitted for materializing constants for use in the current block. 81 void setLastLocalValue(MachineInstr *I) { 82 EmitStartPt = I; 83 LastLocalValue = I; 84 } 85 86 /// startNewBlock - Set the current block to which generated machine 87 /// instructions will be appended, and clear the local CSE map. 88 /// 89 void startNewBlock(); 90 91 /// getCurDebugLoc() - Return current debug location information. 92 DebugLoc getCurDebugLoc() const { return DL; } 93 94 /// SelectInstruction - Do "fast" instruction selection for the given 95 /// LLVM IR instruction, and append generated machine instructions to 96 /// the current block. Return true if selection was successful. 97 /// 98 bool SelectInstruction(const Instruction *I); 99 100 /// SelectOperator - Do "fast" instruction selection for the given 101 /// LLVM IR operator (Instruction or ConstantExpr), and append 102 /// generated machine instructions to the current block. Return true 103 /// if selection was successful. 104 /// 105 bool SelectOperator(const User *I, unsigned Opcode); 106 107 /// getRegForValue - Create a virtual register and arrange for it to 108 /// be assigned the value for the given LLVM value. 109 unsigned getRegForValue(const Value *V); 110 111 /// lookUpRegForValue - Look up the value to see if its value is already 112 /// cached in a register. It may be defined by instructions across blocks or 113 /// defined locally. 114 unsigned lookUpRegForValue(const Value *V); 115 116 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also 117 /// takes care of truncating or sign-extending the given getelementptr 118 /// index value. 119 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V); 120 121 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that 122 /// vreg is being provided by the specified load instruction. If possible, 123 /// try to fold the load as an operand to the instruction, returning true if 124 /// possible. 125 virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/, 126 const LoadInst * /*LI*/) { 127 return false; 128 } 129 130 /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions 131 /// into the current block. 132 void recomputeInsertPt(); 133 134 struct SavePoint { 135 MachineBasicBlock::iterator InsertPt; 136 DebugLoc DL; 137 }; 138 139 /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions 140 /// into the local value area and return the old insert position. 141 SavePoint enterLocalValueArea(); 142 143 /// leaveLocalValueArea - Reset InsertPt to the given old insert position. 144 void leaveLocalValueArea(SavePoint Old); 145 146 virtual ~FastISel(); 147 148protected: 149 explicit FastISel(FunctionLoweringInfo &funcInfo, 150 const TargetLibraryInfo *libInfo); 151 152 /// TargetSelectInstruction - This method is called by target-independent 153 /// code when the normal FastISel process fails to select an instruction. 154 /// This gives targets a chance to emit code for anything that doesn't 155 /// fit into FastISel's framework. It returns true if it was successful. 156 /// 157 virtual bool 158 TargetSelectInstruction(const Instruction *I) = 0; 159 160 /// FastEmit_r - This method is called by target-independent code 161 /// to request that an instruction with the given type and opcode 162 /// be emitted. 163 virtual unsigned FastEmit_(MVT VT, 164 MVT RetVT, 165 unsigned Opcode); 166 167 /// FastEmit_r - This method is called by target-independent code 168 /// to request that an instruction with the given type, opcode, and 169 /// register operand be emitted. 170 /// 171 virtual unsigned FastEmit_r(MVT VT, 172 MVT RetVT, 173 unsigned Opcode, 174 unsigned Op0, bool Op0IsKill); 175 176 /// FastEmit_rr - This method is called by target-independent code 177 /// to request that an instruction with the given type, opcode, and 178 /// register operands be emitted. 179 /// 180 virtual unsigned FastEmit_rr(MVT VT, 181 MVT RetVT, 182 unsigned Opcode, 183 unsigned Op0, bool Op0IsKill, 184 unsigned Op1, bool Op1IsKill); 185 186 /// FastEmit_ri - This method is called by target-independent code 187 /// to request that an instruction with the given type, opcode, and 188 /// register and immediate operands be emitted. 189 /// 190 virtual unsigned FastEmit_ri(MVT VT, 191 MVT RetVT, 192 unsigned Opcode, 193 unsigned Op0, bool Op0IsKill, 194 uint64_t Imm); 195 196 /// FastEmit_rf - This method is called by target-independent code 197 /// to request that an instruction with the given type, opcode, and 198 /// register and floating-point immediate operands be emitted. 199 /// 200 virtual unsigned FastEmit_rf(MVT VT, 201 MVT RetVT, 202 unsigned Opcode, 203 unsigned Op0, bool Op0IsKill, 204 const ConstantFP *FPImm); 205 206 /// FastEmit_rri - This method is called by target-independent code 207 /// to request that an instruction with the given type, opcode, and 208 /// register and immediate operands be emitted. 209 /// 210 virtual unsigned FastEmit_rri(MVT VT, 211 MVT RetVT, 212 unsigned Opcode, 213 unsigned Op0, bool Op0IsKill, 214 unsigned Op1, bool Op1IsKill, 215 uint64_t Imm); 216 217 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 218 /// to emit an instruction with an immediate operand using FastEmit_ri. 219 /// If that fails, it materializes the immediate into a register and try 220 /// FastEmit_rr instead. 221 unsigned FastEmit_ri_(MVT VT, 222 unsigned Opcode, 223 unsigned Op0, bool Op0IsKill, 224 uint64_t Imm, MVT ImmType); 225 226 /// FastEmit_i - This method is called by target-independent code 227 /// to request that an instruction with the given type, opcode, and 228 /// immediate operand be emitted. 229 virtual unsigned FastEmit_i(MVT VT, 230 MVT RetVT, 231 unsigned Opcode, 232 uint64_t Imm); 233 234 /// FastEmit_f - This method is called by target-independent code 235 /// to request that an instruction with the given type, opcode, and 236 /// floating-point immediate operand be emitted. 237 virtual unsigned FastEmit_f(MVT VT, 238 MVT RetVT, 239 unsigned Opcode, 240 const ConstantFP *FPImm); 241 242 /// FastEmitInst_ - Emit a MachineInstr with no operands and a 243 /// result register in the given register class. 244 /// 245 unsigned FastEmitInst_(unsigned MachineInstOpcode, 246 const TargetRegisterClass *RC); 247 248 /// FastEmitInst_r - Emit a MachineInstr with one register operand 249 /// and a result register in the given register class. 250 /// 251 unsigned FastEmitInst_r(unsigned MachineInstOpcode, 252 const TargetRegisterClass *RC, 253 unsigned Op0, bool Op0IsKill); 254 255 /// FastEmitInst_rr - Emit a MachineInstr with two register operands 256 /// and a result register in the given register class. 257 /// 258 unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 259 const TargetRegisterClass *RC, 260 unsigned Op0, bool Op0IsKill, 261 unsigned Op1, bool Op1IsKill); 262 263 /// FastEmitInst_rrr - Emit a MachineInstr with three register operands 264 /// and a result register in the given register class. 265 /// 266 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, 267 const TargetRegisterClass *RC, 268 unsigned Op0, bool Op0IsKill, 269 unsigned Op1, bool Op1IsKill, 270 unsigned Op2, bool Op2IsKill); 271 272 /// FastEmitInst_ri - Emit a MachineInstr with a register operand, 273 /// an immediate, and a result register in the given register class. 274 /// 275 unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 276 const TargetRegisterClass *RC, 277 unsigned Op0, bool Op0IsKill, 278 uint64_t Imm); 279 280 /// FastEmitInst_rii - Emit a MachineInstr with one register operand 281 /// and two immediate operands. 282 /// 283 unsigned FastEmitInst_rii(unsigned MachineInstOpcode, 284 const TargetRegisterClass *RC, 285 unsigned Op0, bool Op0IsKill, 286 uint64_t Imm1, uint64_t Imm2); 287 288 /// FastEmitInst_rf - Emit a MachineInstr with two register operands 289 /// and a result register in the given register class. 290 /// 291 unsigned FastEmitInst_rf(unsigned MachineInstOpcode, 292 const TargetRegisterClass *RC, 293 unsigned Op0, bool Op0IsKill, 294 const ConstantFP *FPImm); 295 296 /// FastEmitInst_rri - Emit a MachineInstr with two register operands, 297 /// an immediate, and a result register in the given register class. 298 /// 299 unsigned FastEmitInst_rri(unsigned MachineInstOpcode, 300 const TargetRegisterClass *RC, 301 unsigned Op0, bool Op0IsKill, 302 unsigned Op1, bool Op1IsKill, 303 uint64_t Imm); 304 305 /// FastEmitInst_rrii - Emit a MachineInstr with two register operands, 306 /// two immediates operands, and a result register in the given register 307 /// class. 308 unsigned FastEmitInst_rrii(unsigned MachineInstOpcode, 309 const TargetRegisterClass *RC, 310 unsigned Op0, bool Op0IsKill, 311 unsigned Op1, bool Op1IsKill, 312 uint64_t Imm1, uint64_t Imm2); 313 314 /// FastEmitInst_i - Emit a MachineInstr with a single immediate 315 /// operand, and a result register in the given register class. 316 unsigned FastEmitInst_i(unsigned MachineInstrOpcode, 317 const TargetRegisterClass *RC, 318 uint64_t Imm); 319 320 /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands. 321 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode, 322 const TargetRegisterClass *RC, 323 uint64_t Imm1, uint64_t Imm2); 324 325 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg 326 /// from a specified index of a superregister to a specified type. 327 unsigned FastEmitInst_extractsubreg(MVT RetVT, 328 unsigned Op0, bool Op0IsKill, 329 uint32_t Idx); 330 331 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 332 /// with all but the least significant bit set to zero. 333 unsigned FastEmitZExtFromI1(MVT VT, 334 unsigned Op0, bool Op0IsKill); 335 336 /// FastEmitBranch - Emit an unconditional branch to the given block, 337 /// unless it is the immediate (fall-through) successor, and update 338 /// the CFG. 339 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL); 340 341 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1); 342 343 unsigned createResultReg(const TargetRegisterClass *RC); 344 345 /// TargetMaterializeConstant - Emit a constant in a register using 346 /// target-specific logic, such as constant pool loads. 347 virtual unsigned TargetMaterializeConstant(const Constant* C) { 348 return 0; 349 } 350 351 /// TargetMaterializeAlloca - Emit an alloca address in a register using 352 /// target-specific logic. 353 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) { 354 return 0; 355 } 356 357 virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) { 358 return 0; 359 } 360 361private: 362 bool SelectBinaryOp(const User *I, unsigned ISDOpcode); 363 364 bool SelectFNeg(const User *I); 365 366 bool SelectGetElementPtr(const User *I); 367 368 bool SelectCall(const User *I); 369 370 bool SelectBitCast(const User *I); 371 372 bool SelectCast(const User *I, unsigned Opcode); 373 374 bool SelectExtractValue(const User *I); 375 376 bool SelectInsertValue(const User *I); 377 378 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 379 /// Emit code to ensure constants are copied into registers when needed. 380 /// Remember the virtual registers that need to be added to the Machine PHI 381 /// nodes as input. We cannot just directly add them, because expansion 382 /// might result in multiple MBB's for one BB. As such, the start of the 383 /// BB might correspond to a different MBB than the end. 384 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); 385 386 /// materializeRegForValue - Helper for getRegForVale. This function is 387 /// called when the value isn't already available in a register and must 388 /// be materialized with new instructions. 389 unsigned materializeRegForValue(const Value *V, MVT VT); 390 391 /// flushLocalValueMap - clears LocalValueMap and moves the area for the 392 /// new local variables to the beginning of the block. It helps to avoid 393 /// spilling cached variables across heavy instructions like calls. 394 void flushLocalValueMap(); 395 396 /// hasTrivialKill - Test whether the given value has exactly one use. 397 bool hasTrivialKill(const Value *V) const; 398 399 /// removeDeadCode - Remove all dead instructions between the I and E. 400 void removeDeadCode(MachineBasicBlock::iterator I, 401 MachineBasicBlock::iterator E); 402}; 403 404} 405 406#endif 407