FastISel.h revision c7f72de3b4ef21828ea4780f0693bf0acd04e1c5 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/BasicBlock.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/CodeGen/SelectionDAGNodes.h"
20
21namespace llvm {
22
23class MachineBasicBlock;
24class MachineFunction;
25class MachineRegisterInfo;
26class TargetData;
27class TargetInstrInfo;
28class TargetLowering;
29class TargetRegisterClass;
30
31/// FastISel - This is a fast-path instruction selection class that
32/// generates poor code and doesn't support illegal types or non-trivial
33/// lowering, but runs quickly.
34class FastISel {
35  MachineBasicBlock *MBB;
36  MachineFunction &MF;
37  MachineRegisterInfo &MRI;
38  const TargetData &TD;
39  const TargetInstrInfo &TII;
40  TargetLowering &TLI;
41
42public:
43  /// SelectInstructions - Do "fast" instruction selection over the
44  /// LLVM IR instructions in the range [Begin, N) where N is either
45  /// End or the first unsupported instruction. Return N.
46  /// ValueMap is filled in with a mapping of LLVM IR Values to
47  /// register numbers.
48  BasicBlock::iterator
49  SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
50                     DenseMap<const Value*, unsigned> &ValueMap,
51                     MachineBasicBlock *mbb);
52
53  virtual ~FastISel();
54
55protected:
56  explicit FastISel(MachineFunction &mf);
57
58  /// FastEmit_r - This method is called by target-independent code
59  /// to request that an instruction with the given type and opcode
60  /// be emitted.
61  virtual unsigned FastEmit_(MVT::SimpleValueType VT,
62                             ISD::NodeType Opcode);
63
64  /// FastEmit_r - This method is called by target-independent code
65  /// to request that an instruction with the given type, opcode, and
66  /// register operand be emitted.
67  ///
68  virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
69                              ISD::NodeType Opcode, unsigned Op0);
70
71  /// FastEmit_rr - This method is called by target-independent code
72  /// to request that an instruction with the given type, opcode, and
73  /// register operands be emitted.
74  ///
75  virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
76                               ISD::NodeType Opcode,
77                               unsigned Op0, unsigned Op1);
78
79  /// FastEmit_i - This method is called by target-independent code
80  /// to request that an instruction with the given type which materialize
81  /// the specified immediate value.
82  virtual unsigned FastEmit_i(MVT::SimpleValueType VT, uint64_t Imm);
83
84  /// FastEmit_ri - This method is called by target-independent code
85  /// to request that an instruction with the given type, opcode, and
86  /// register and immediate operands be emitted.
87  ///
88  virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
89                               ISD::NodeType Opcode,
90                               unsigned Op0, uint64_t Imm,
91                               MVT::SimpleValueType ImmType);
92
93  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
94  /// to emit an instruction with an immediate operand using FastEmit_ri.
95  /// If that fails, it materializes the immediate into a register and try
96  /// FastEmit_rr instead.
97  unsigned FastEmit_ri_(MVT::SimpleValueType VT,
98                        ISD::NodeType Opcode,
99                        unsigned Op0, uint64_t Imm,
100                        MVT::SimpleValueType ImmType);
101
102  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
103  /// result register in the given register class.
104  ///
105  unsigned FastEmitInst_(unsigned MachineInstOpcode,
106                         const TargetRegisterClass *RC);
107
108  /// FastEmitInst_ - Emit a MachineInstr with one register operand
109  /// and a result register in the given register class.
110  ///
111  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
112                          const TargetRegisterClass *RC,
113                          unsigned Op0);
114
115  /// FastEmitInst_ - Emit a MachineInstr with two register operands
116  /// and a result register in the given register class.
117  ///
118  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
119                           const TargetRegisterClass *RC,
120                           unsigned Op0, unsigned Op1);
121
122private:
123  unsigned createResultReg(const TargetRegisterClass *RC);
124
125  bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
126                      DenseMap<const Value*, unsigned> &ValueMap);
127
128  bool SelectGetElementPtr(Instruction *I,
129                           DenseMap<const Value*, unsigned> &ValueMap);
130};
131
132}
133
134#endif
135