FastISel.h revision d71867a8f4b1ab6ab8cc8f5b1a732184ec5bad1b 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/CodeGen/ValueTypes.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20
21namespace llvm {
22
23class AllocaInst;
24class ConstantFP;
25class FunctionLoweringInfo;
26class Instruction;
27class MachineBasicBlock;
28class MachineConstantPool;
29class MachineFunction;
30class MachineInstr;
31class MachineFrameInfo;
32class MachineRegisterInfo;
33class TargetData;
34class TargetInstrInfo;
35class TargetLowering;
36class TargetMachine;
37class TargetRegisterClass;
38class TargetRegisterInfo;
39class LoadInst;
40
41/// FastISel - This is a fast-path instruction selection class that
42/// generates poor code and doesn't support illegal types or non-trivial
43/// lowering, but runs quickly.
44class FastISel {
45protected:
46  DenseMap<const Value *, unsigned> LocalValueMap;
47  FunctionLoweringInfo &FuncInfo;
48  MachineRegisterInfo &MRI;
49  MachineFrameInfo &MFI;
50  MachineConstantPool &MCP;
51  DebugLoc DL;
52  const TargetMachine &TM;
53  const TargetData &TD;
54  const TargetInstrInfo &TII;
55  const TargetLowering &TLI;
56  const TargetRegisterInfo &TRI;
57  MachineInstr *LastLocalValue;
58
59public:
60  /// getLastLocalValue - Return the position of the last instruction
61  /// emitted for materializing constants for use in the current block.
62  MachineInstr *getLastLocalValue() { return LastLocalValue; }
63
64  /// setLastLocalValue - Update the position of the last instruction
65  /// emitted for materializing constants for use in the current block.
66  void setLastLocalValue(MachineInstr *I) { LastLocalValue = I; }
67
68  /// startNewBlock - Set the current block to which generated machine
69  /// instructions will be appended, and clear the local CSE map.
70  ///
71  void startNewBlock();
72
73  /// getCurDebugLoc() - Return current debug location information.
74  DebugLoc getCurDebugLoc() const { return DL; }
75
76  /// SelectInstruction - Do "fast" instruction selection for the given
77  /// LLVM IR instruction, and append generated machine instructions to
78  /// the current block. Return true if selection was successful.
79  ///
80  bool SelectInstruction(const Instruction *I);
81
82  /// SelectOperator - Do "fast" instruction selection for the given
83  /// LLVM IR operator (Instruction or ConstantExpr), and append
84  /// generated machine instructions to the current block. Return true
85  /// if selection was successful.
86  ///
87  bool SelectOperator(const User *I, unsigned Opcode);
88
89  /// getRegForValue - Create a virtual register and arrange for it to
90  /// be assigned the value for the given LLVM value.
91  unsigned getRegForValue(const Value *V);
92
93  /// lookUpRegForValue - Look up the value to see if its value is already
94  /// cached in a register. It may be defined by instructions across blocks or
95  /// defined locally.
96  unsigned lookUpRegForValue(const Value *V);
97
98  /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
99  /// takes care of truncating or sign-extending the given getelementptr
100  /// index value.
101  std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
102
103  /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
104  /// vreg is being provided by the specified load instruction.  If possible,
105  /// try to fold the load as an operand to the instruction, returning true if
106  /// possible.
107  virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/,
108                             const LoadInst * /*LI*/) {
109    return false;
110  }
111
112  /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions
113  /// into the current block.
114  void recomputeInsertPt();
115
116  struct SavePoint {
117    MachineBasicBlock::iterator InsertPt;
118    DebugLoc DL;
119  };
120
121  /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions
122  /// into the local value area and return the old insert position.
123  SavePoint enterLocalValueArea();
124
125  /// leaveLocalValueArea - Reset InsertPt to the given old insert position.
126  void leaveLocalValueArea(SavePoint Old);
127
128  virtual ~FastISel();
129
130protected:
131  explicit FastISel(FunctionLoweringInfo &funcInfo);
132
133  /// TargetSelectInstruction - This method is called by target-independent
134  /// code when the normal FastISel process fails to select an instruction.
135  /// This gives targets a chance to emit code for anything that doesn't
136  /// fit into FastISel's framework. It returns true if it was successful.
137  ///
138  virtual bool
139  TargetSelectInstruction(const Instruction *I) = 0;
140
141  /// FastEmit_r - This method is called by target-independent code
142  /// to request that an instruction with the given type and opcode
143  /// be emitted.
144  virtual unsigned FastEmit_(MVT VT,
145                             MVT RetVT,
146                             unsigned Opcode);
147
148  /// FastEmit_r - This method is called by target-independent code
149  /// to request that an instruction with the given type, opcode, and
150  /// register operand be emitted.
151  ///
152  virtual unsigned FastEmit_r(MVT VT,
153                              MVT RetVT,
154                              unsigned Opcode,
155                              unsigned Op0, bool Op0IsKill);
156
157  /// FastEmit_rr - This method is called by target-independent code
158  /// to request that an instruction with the given type, opcode, and
159  /// register operands be emitted.
160  ///
161  virtual unsigned FastEmit_rr(MVT VT,
162                               MVT RetVT,
163                               unsigned Opcode,
164                               unsigned Op0, bool Op0IsKill,
165                               unsigned Op1, bool Op1IsKill);
166
167  /// FastEmit_ri - This method is called by target-independent code
168  /// to request that an instruction with the given type, opcode, and
169  /// register and immediate operands be emitted.
170  ///
171  virtual unsigned FastEmit_ri(MVT VT,
172                               MVT RetVT,
173                               unsigned Opcode,
174                               unsigned Op0, bool Op0IsKill,
175                               uint64_t Imm);
176
177  /// FastEmit_rf - This method is called by target-independent code
178  /// to request that an instruction with the given type, opcode, and
179  /// register and floating-point immediate operands be emitted.
180  ///
181  virtual unsigned FastEmit_rf(MVT VT,
182                               MVT RetVT,
183                               unsigned Opcode,
184                               unsigned Op0, bool Op0IsKill,
185                               const ConstantFP *FPImm);
186
187  /// FastEmit_rri - This method is called by target-independent code
188  /// to request that an instruction with the given type, opcode, and
189  /// register and immediate operands be emitted.
190  ///
191  virtual unsigned FastEmit_rri(MVT VT,
192                                MVT RetVT,
193                                unsigned Opcode,
194                                unsigned Op0, bool Op0IsKill,
195                                unsigned Op1, bool Op1IsKill,
196                                uint64_t Imm);
197
198  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
199  /// to emit an instruction with an immediate operand using FastEmit_ri.
200  /// If that fails, it materializes the immediate into a register and try
201  /// FastEmit_rr instead.
202  unsigned FastEmit_ri_(MVT VT,
203                        unsigned Opcode,
204                        unsigned Op0, bool Op0IsKill,
205                        uint64_t Imm, MVT ImmType);
206
207  /// FastEmit_i - This method is called by target-independent code
208  /// to request that an instruction with the given type, opcode, and
209  /// immediate operand be emitted.
210  virtual unsigned FastEmit_i(MVT VT,
211                              MVT RetVT,
212                              unsigned Opcode,
213                              uint64_t Imm);
214
215  /// FastEmit_f - This method is called by target-independent code
216  /// to request that an instruction with the given type, opcode, and
217  /// floating-point immediate operand be emitted.
218  virtual unsigned FastEmit_f(MVT VT,
219                              MVT RetVT,
220                              unsigned Opcode,
221                              const ConstantFP *FPImm);
222
223  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
224  /// result register in the given register class.
225  ///
226  unsigned FastEmitInst_(unsigned MachineInstOpcode,
227                         const TargetRegisterClass *RC);
228
229  /// FastEmitInst_r - Emit a MachineInstr with one register operand
230  /// and a result register in the given register class.
231  ///
232  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
233                          const TargetRegisterClass *RC,
234                          unsigned Op0, bool Op0IsKill);
235
236  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
237  /// and a result register in the given register class.
238  ///
239  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
240                           const TargetRegisterClass *RC,
241                           unsigned Op0, bool Op0IsKill,
242                           unsigned Op1, bool Op1IsKill);
243
244  /// FastEmitInst_rrr - Emit a MachineInstr with three register operands
245  /// and a result register in the given register class.
246  ///
247  unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
248                           const TargetRegisterClass *RC,
249                           unsigned Op0, bool Op0IsKill,
250                           unsigned Op1, bool Op1IsKill,
251                           unsigned Op2, bool Op2IsKill);
252
253  /// FastEmitInst_ri - Emit a MachineInstr with a register operand,
254  /// an immediate, and a result register in the given register class.
255  ///
256  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
257                           const TargetRegisterClass *RC,
258                           unsigned Op0, bool Op0IsKill,
259                           uint64_t Imm);
260
261  /// FastEmitInst_rii - Emit a MachineInstr with one register operand
262  /// and two immediate operands.
263  ///
264  unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
265                           const TargetRegisterClass *RC,
266                           unsigned Op0, bool Op0IsKill,
267                           uint64_t Imm1, uint64_t Imm2);
268
269  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
270  /// and a result register in the given register class.
271  ///
272  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
273                           const TargetRegisterClass *RC,
274                           unsigned Op0, bool Op0IsKill,
275                           const ConstantFP *FPImm);
276
277  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
278  /// an immediate, and a result register in the given register class.
279  ///
280  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
281                            const TargetRegisterClass *RC,
282                            unsigned Op0, bool Op0IsKill,
283                            unsigned Op1, bool Op1IsKill,
284                            uint64_t Imm);
285
286  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
287  /// operand, and a result register in the given register class.
288  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
289                          const TargetRegisterClass *RC,
290                          uint64_t Imm);
291
292  /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.
293  unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
294                          const TargetRegisterClass *RC,
295                          uint64_t Imm1, uint64_t Imm2);
296
297  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
298  /// from a specified index of a superregister to a specified type.
299  unsigned FastEmitInst_extractsubreg(MVT RetVT,
300                                      unsigned Op0, bool Op0IsKill,
301                                      uint32_t Idx);
302
303  /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
304  /// with all but the least significant bit set to zero.
305  unsigned FastEmitZExtFromI1(MVT VT,
306                              unsigned Op0, bool Op0IsKill);
307
308  /// FastEmitBranch - Emit an unconditional branch to the given block,
309  /// unless it is the immediate (fall-through) successor, and update
310  /// the CFG.
311  void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
312
313  unsigned UpdateValueMap(const Value* I, unsigned Reg);
314
315  unsigned createResultReg(const TargetRegisterClass *RC);
316
317  /// TargetMaterializeConstant - Emit a constant in a register using
318  /// target-specific logic, such as constant pool loads.
319  virtual unsigned TargetMaterializeConstant(const Constant* C) {
320    return 0;
321  }
322
323  /// TargetMaterializeAlloca - Emit an alloca address in a register using
324  /// target-specific logic.
325  virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
326    return 0;
327  }
328
329  virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) {
330    return 0;
331  }
332
333private:
334  bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
335
336  bool SelectFNeg(const User *I);
337
338  bool SelectGetElementPtr(const User *I);
339
340  bool SelectCall(const User *I);
341
342  bool SelectBitCast(const User *I);
343
344  bool SelectCast(const User *I, unsigned Opcode);
345
346  /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
347  /// Emit code to ensure constants are copied into registers when needed.
348  /// Remember the virtual registers that need to be added to the Machine PHI
349  /// nodes as input.  We cannot just directly add them, because expansion
350  /// might result in multiple MBB's for one BB.  As such, the start of the
351  /// BB might correspond to a different MBB than the end.
352  bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
353
354  /// materializeRegForValue - Helper for getRegForVale. This function is
355  /// called when the value isn't already available in a register and must
356  /// be materialized with new instructions.
357  unsigned materializeRegForValue(const Value *V, MVT VT);
358
359  /// hasTrivialKill - Test whether the given value has exactly one use.
360  bool hasTrivialKill(const Value *V) const;
361};
362
363}
364
365#endif
366