1//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares codegen opcodes and related utilities. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_ISDOPCODES_H 15#define LLVM_CODEGEN_ISDOPCODES_H 16 17namespace llvm { 18 19/// ISD namespace - This namespace contains an enum which represents all of the 20/// SelectionDAG node types and value types. 21/// 22namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. 76 /// Materializes the offset from the local object pointer of another 77 /// function to a particular local object passed to llvm.localescape. The 78 /// operand is the MCSymbol label used to represent this offset, since 79 /// typically the offset is not known until after code generation of the 80 /// parent. 81 LOCAL_RECOVER, 82 83 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 84 /// the DAG, which implements the named register global variables extension. 85 READ_REGISTER, 86 WRITE_REGISTER, 87 88 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 89 /// first (possible) on-stack argument. This is needed for correct stack 90 /// adjustment during unwind. 91 FRAME_TO_ARGS_OFFSET, 92 93 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 94 /// 'eh_return' gcc dwarf builtin, which is used to return from 95 /// exception. The general meaning is: adjust stack by OFFSET and pass 96 /// execution to HANDLER. Many platform-related details also :) 97 EH_RETURN, 98 99 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 100 /// This corresponds to the eh.sjlj.setjmp intrinsic. 101 /// It takes an input chain and a pointer to the jump buffer as inputs 102 /// and returns an outchain. 103 EH_SJLJ_SETJMP, 104 105 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 106 /// This corresponds to the eh.sjlj.longjmp intrinsic. 107 /// It takes an input chain and a pointer to the jump buffer as inputs 108 /// and returns an outchain. 109 EH_SJLJ_LONGJMP, 110 111 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) 112 /// The target initializes the dispatch table here. 113 EH_SJLJ_SETUP_DISPATCH, 114 115 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 116 /// simplification, or lowering of the constant. They are used for constants 117 /// which are known to fit in the immediate fields of their users, or for 118 /// carrying magic numbers which are not values which need to be 119 /// materialized in registers. 120 TargetConstant, 121 TargetConstantFP, 122 123 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 124 /// anything else with this node, and this is valid in the target-specific 125 /// dag, turning into a GlobalAddress operand. 126 TargetGlobalAddress, 127 TargetGlobalTLSAddress, 128 TargetFrameIndex, 129 TargetJumpTable, 130 TargetConstantPool, 131 TargetExternalSymbol, 132 TargetBlockAddress, 133 134 MCSymbol, 135 136 /// TargetIndex - Like a constant pool entry, but with completely 137 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 138 /// 64-bit index. Targets can use this however they like. 139 TargetIndex, 140 141 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 142 /// This node represents a target intrinsic function with no side effects. 143 /// The first operand is the ID number of the intrinsic from the 144 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 145 /// node returns the result of the intrinsic. 146 INTRINSIC_WO_CHAIN, 147 148 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 149 /// This node represents a target intrinsic function with side effects that 150 /// returns a result. The first operand is a chain pointer. The second is 151 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 152 /// operands to the intrinsic follow. The node has two results, the result 153 /// of the intrinsic and an output chain. 154 INTRINSIC_W_CHAIN, 155 156 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 157 /// This node represents a target intrinsic function with side effects that 158 /// does not return a result. The first operand is a chain pointer. The 159 /// second is the ID number of the intrinsic from the llvm::Intrinsic 160 /// namespace. The operands to the intrinsic follow. 161 INTRINSIC_VOID, 162 163 /// CopyToReg - This node has three operands: a chain, a register number to 164 /// set to this value, and a value. 165 CopyToReg, 166 167 /// CopyFromReg - This node indicates that the input value is a virtual or 168 /// physical register that is defined outside of the scope of this 169 /// SelectionDAG. The register is available from the RegisterSDNode object. 170 CopyFromReg, 171 172 /// UNDEF - An undefined node. 173 UNDEF, 174 175 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 176 /// a Constant, which is required to be operand #1) half of the integer or 177 /// float value specified as operand #0. This is only for use before 178 /// legalization, for values that will be broken into multiple registers. 179 EXTRACT_ELEMENT, 180 181 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 182 /// Given two values of the same integer value type, this produces a value 183 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 184 /// legalization. 185 BUILD_PAIR, 186 187 /// MERGE_VALUES - This node takes multiple discrete operands and returns 188 /// them all as its individual results. This nodes has exactly the same 189 /// number of inputs and outputs. This node is useful for some pieces of the 190 /// code generator that want to think about a single node with multiple 191 /// results, not multiple nodes. 192 MERGE_VALUES, 193 194 /// Simple integer binary arithmetic operators. 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 196 197 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 198 /// a signed/unsigned value of type i[2*N], and return the full value as 199 /// two results, each of type iN. 200 SMUL_LOHI, UMUL_LOHI, 201 202 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 203 /// remainder result. 204 SDIVREM, UDIVREM, 205 206 /// CARRY_FALSE - This node is used when folding other nodes, 207 /// like ADDC/SUBC, which indicate the carry result is always false. 208 CARRY_FALSE, 209 210 /// Carry-setting nodes for multiple precision addition and subtraction. 211 /// These nodes take two operands of the same value type, and produce two 212 /// results. The first result is the normal add or sub result, the second 213 /// result is the carry flag result. 214 ADDC, SUBC, 215 216 /// Carry-using nodes for multiple precision addition and subtraction. These 217 /// nodes take three operands: The first two are the normal lhs and rhs to 218 /// the add or sub, and the third is the input carry flag. These nodes 219 /// produce two results; the normal result of the add or sub, and the output 220 /// carry flag. These nodes both read and write a carry flag to allow them 221 /// to them to be chained together for add and sub of arbitrarily large 222 /// values. 223 ADDE, SUBE, 224 225 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 226 /// These nodes take two operands: the normal LHS and RHS to the add. They 227 /// produce two results: the normal result of the add, and a boolean that 228 /// indicates if an overflow occurred (*not* a flag, because it may be store 229 /// to memory, etc.). If the type of the boolean is not i1 then the high 230 /// bits conform to getBooleanContents. 231 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 232 SADDO, UADDO, 233 234 /// Same for subtraction. 235 SSUBO, USUBO, 236 237 /// Same for multiplication. 238 SMULO, UMULO, 239 240 /// Simple binary floating point operators. 241 FADD, FSUB, FMUL, FDIV, FREM, 242 243 /// FMA - Perform a * b + c with no intermediate rounding step. 244 FMA, 245 246 /// FMAD - Perform a * b + c, while getting the same result as the 247 /// separately rounded operations. 248 FMAD, 249 250 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 251 /// DAG node does not require that X and Y have the same type, just that 252 /// they are both floating point. X and the result must have the same type. 253 /// FCOPYSIGN(f32, f64) is allowed. 254 FCOPYSIGN, 255 256 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 257 /// value as an integer 0/1 value. 258 FGETSIGN, 259 260 /// Returns platform specific canonical encoding of a floating point number. 261 FCANONICALIZE, 262 263 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 264 /// specified, possibly variable, elements. The number of elements is 265 /// required to be a power of two. The types of the operands must all be 266 /// the same and must match the vector element type, except that integer 267 /// types are allowed to be larger than the element type, in which case 268 /// the operands are implicitly truncated. 269 BUILD_VECTOR, 270 271 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 272 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 273 /// element type then VAL is truncated before replacement. 274 INSERT_VECTOR_ELT, 275 276 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 277 /// identified by the (potentially variable) element number IDX. If the 278 /// return type is an integer type larger than the element type of the 279 /// vector, the result is extended to the width of the return type. 280 EXTRACT_VECTOR_ELT, 281 282 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 283 /// vector type with the same length and element type, this produces a 284 /// concatenated vector result value, with length equal to the sum of the 285 /// lengths of the input vectors. 286 CONCAT_VECTORS, 287 288 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 289 /// with VECTOR2 inserted into VECTOR1 at the (potentially 290 /// variable) element number IDX, which must be a multiple of the 291 /// VECTOR2 vector length. The elements of VECTOR1 starting at 292 /// IDX are overwritten with VECTOR2. Elements IDX through 293 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 294 INSERT_SUBVECTOR, 295 296 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 297 /// vector value) starting with the element number IDX, which must be a 298 /// constant multiple of the result vector length. 299 EXTRACT_SUBVECTOR, 300 301 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 302 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 303 /// values that indicate which value (or undef) each result element will 304 /// get. These constant ints are accessible through the 305 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 306 /// 'vperm' instruction, except that the indices must be constants and are 307 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 308 VECTOR_SHUFFLE, 309 310 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 311 /// scalar value into element 0 of the resultant vector type. The top 312 /// elements 1 to N-1 of the N-element vector are undefined. The type 313 /// of the operand must match the vector element type, except when they 314 /// are integer types. In this case the operand is allowed to be wider 315 /// than the vector element type, and is implicitly truncated to it. 316 SCALAR_TO_VECTOR, 317 318 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 319 /// producing an unsigned/signed value of type i[2*N], then return the top 320 /// part. 321 MULHU, MULHS, 322 323 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned 324 /// integers. 325 SMIN, SMAX, UMIN, UMAX, 326 327 /// Bitwise operators - logical and, logical or, logical xor. 328 AND, OR, XOR, 329 330 /// Shift and rotation operations. After legalization, the type of the 331 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 332 /// the shift amount can be any type, but care must be taken to ensure it is 333 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 334 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 335 /// to represent the shift amount. 336 /// When the 1st operand is a vector, the shift amount must be in the same 337 /// type. (TLI.getShiftAmountTy() will return the same type when the input 338 /// type is a vector.) 339 SHL, SRA, SRL, ROTL, ROTR, 340 341 /// Byte Swap and Counting operators. 342 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, 343 344 /// Bit counting operators with an undefined result for zero inputs. 345 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 346 347 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 348 /// i1 then the high bits must conform to getBooleanContents. 349 SELECT, 350 351 /// Select with a vector condition (op #0) and two vector operands (ops #1 352 /// and #2), returning a vector result. All vectors have the same length. 353 /// Much like the scalar select and setcc, each bit in the condition selects 354 /// whether the corresponding result element is taken from op #1 or op #2. 355 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 356 /// change the condition type in order to match the VSELECT node using a 357 /// pattern. The condition follows the BooleanContent format of the target. 358 VSELECT, 359 360 /// Select with condition operator - This selects between a true value and 361 /// a false value (ops #2 and #3) based on the boolean result of comparing 362 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 363 /// condition code in op #4, a CondCodeSDNode. 364 SELECT_CC, 365 366 /// SetCC operator - This evaluates to a true value iff the condition is 367 /// true. If the result value type is not i1 then the high bits conform 368 /// to getBooleanContents. The operands to this are the left and right 369 /// operands to compare (ops #0, and #1) and the condition code to compare 370 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 371 /// then the result type must also be a vector type. 372 SETCC, 373 374 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but 375 /// op #2 is a *carry value*. This operator checks the result of 376 /// "LHS - RHS - Carry", and can be used to compare two wide integers: 377 /// (setcce lhshi rhshi (subc lhslo rhslo) cc). Only valid for integers. 378 SETCCE, 379 380 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 381 /// integer shift operations. The operation ordering is: 382 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 383 SHL_PARTS, SRA_PARTS, SRL_PARTS, 384 385 /// Conversion operators. These are all single input single output 386 /// operations. For all of these, the result type must be strictly 387 /// wider or narrower (depending on the operation) than the source 388 /// type. 389 390 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 391 /// into new bits. 392 SIGN_EXTEND, 393 394 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 395 ZERO_EXTEND, 396 397 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 398 ANY_EXTEND, 399 400 /// TRUNCATE - Completely drop the high bits. 401 TRUNCATE, 402 403 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 404 /// depends on the first letter) to floating point. 405 SINT_TO_FP, 406 UINT_TO_FP, 407 408 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 409 /// sign extend a small value in a large integer register (e.g. sign 410 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 411 /// with the 7th bit). The size of the smaller type is indicated by the 1th 412 /// operand, a ValueType node. 413 SIGN_EXTEND_INREG, 414 415 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 416 /// in-register any-extension of the low lanes of an integer vector. The 417 /// result type must have fewer elements than the operand type, and those 418 /// elements must be larger integer types such that the total size of the 419 /// operand type and the result type match. Each of the low operand 420 /// elements is any-extended into the corresponding, wider result 421 /// elements with the high bits becoming undef. 422 ANY_EXTEND_VECTOR_INREG, 423 424 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 425 /// in-register sign-extension of the low lanes of an integer vector. The 426 /// result type must have fewer elements than the operand type, and those 427 /// elements must be larger integer types such that the total size of the 428 /// operand type and the result type match. Each of the low operand 429 /// elements is sign-extended into the corresponding, wider result 430 /// elements. 431 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to 432 // scalars, but it also doesn't handle vectors well. Either it should be 433 // restricted to scalars or this node (and its handling) should be merged 434 // into it. 435 SIGN_EXTEND_VECTOR_INREG, 436 437 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 438 /// in-register zero-extension of the low lanes of an integer vector. The 439 /// result type must have fewer elements than the operand type, and those 440 /// elements must be larger integer types such that the total size of the 441 /// operand type and the result type match. Each of the low operand 442 /// elements is zero-extended into the corresponding, wider result 443 /// elements. 444 ZERO_EXTEND_VECTOR_INREG, 445 446 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 447 /// integer. 448 FP_TO_SINT, 449 FP_TO_UINT, 450 451 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 452 /// down to the precision of the destination VT. TRUNC is a flag, which is 453 /// always an integer that is zero or one. If TRUNC is 0, this is a 454 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 455 /// value of Y. 456 /// 457 /// The TRUNC = 1 case is used in cases where we know that the value will 458 /// not be modified by the node, because Y is not using any of the extra 459 /// precision of source type. This allows certain transformations like 460 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 461 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 462 FP_ROUND, 463 464 /// FLT_ROUNDS_ - Returns current rounding mode: 465 /// -1 Undefined 466 /// 0 Round to 0 467 /// 1 Round to nearest 468 /// 2 Round to +inf 469 /// 3 Round to -inf 470 FLT_ROUNDS_, 471 472 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 473 /// rounds it to a floating point value. It then promotes it and returns it 474 /// in a register of the same size. This operation effectively just 475 /// discards excess precision. The type to round down to is specified by 476 /// the VT operand, a VTSDNode. 477 FP_ROUND_INREG, 478 479 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 480 FP_EXTEND, 481 482 /// BITCAST - This operator converts between integer, vector and FP 483 /// values, as if the value was stored to memory with one type and loaded 484 /// from the same address with the other type (or equivalently for vector 485 /// format conversions, etc). The source and result are required to have 486 /// the same bit size (e.g. f32 <-> i32). This can also be used for 487 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 488 /// getNode(). 489 /// 490 /// This operator is subtly different from the bitcast instruction from 491 /// LLVM-IR since this node may change the bits in the register. For 492 /// example, this occurs on big-endian NEON and big-endian MSA where the 493 /// layout of the bits in the register depends on the vector type and this 494 /// operator acts as a shuffle operation for some vector type combinations. 495 BITCAST, 496 497 /// ADDRSPACECAST - This operator converts between pointers of different 498 /// address spaces. 499 ADDRSPACECAST, 500 501 /// CONVERT_RNDSAT - This operator is used to support various conversions 502 /// between various types (float, signed, unsigned and vectors of those 503 /// types) with rounding and saturation. NOTE: Avoid using this operator as 504 /// most target don't support it and the operator might be removed in the 505 /// future. It takes the following arguments: 506 /// 0) value 507 /// 1) dest type (type to convert to) 508 /// 2) src type (type to convert from) 509 /// 3) rounding imm 510 /// 4) saturation imm 511 /// 5) ISD::CvtCode indicating the type of conversion to do 512 CONVERT_RNDSAT, 513 514 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 515 /// and truncation for half-precision (16 bit) floating numbers. These nodes 516 /// form a semi-softened interface for dealing with f16 (as an i16), which 517 /// is often a storage-only type but has native conversions. 518 FP16_TO_FP, FP_TO_FP16, 519 520 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 521 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 522 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary 523 /// floating point operations. These are inspired by libm. 524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 525 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 527 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two 528 /// values. 529 /// In the case where a single input is NaN, the non-NaN input is returned. 530 /// 531 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. 532 FMINNUM, FMAXNUM, 533 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that 534 /// when a single input is NaN, NaN is returned. 535 FMINNAN, FMAXNAN, 536 537 /// FSINCOS - Compute both fsin and fcos as a single operation. 538 FSINCOS, 539 540 /// LOAD and STORE have token chains as their first operand, then the same 541 /// operands as an LLVM load/store instruction, then an offset node that 542 /// is added / subtracted from the base pointer to form the address (for 543 /// indexed memory ops). 544 LOAD, STORE, 545 546 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 547 /// to a specified boundary. This node always has two return values: a new 548 /// stack pointer value and a chain. The first operand is the token chain, 549 /// the second is the number of bytes to allocate, and the third is the 550 /// alignment boundary. The size is guaranteed to be a multiple of the 551 /// stack alignment, and the alignment is guaranteed to be bigger than the 552 /// stack alignment (if required) or 0 to get standard stack alignment. 553 DYNAMIC_STACKALLOC, 554 555 /// Control flow instructions. These all have token chains. 556 557 /// BR - Unconditional branch. The first operand is the chain 558 /// operand, the second is the MBB to branch to. 559 BR, 560 561 /// BRIND - Indirect branch. The first operand is the chain, the second 562 /// is the value to branch to, which must be of the same type as the 563 /// target's pointer type. 564 BRIND, 565 566 /// BR_JT - Jumptable branch. The first operand is the chain, the second 567 /// is the jumptable index, the last one is the jumptable entry index. 568 BR_JT, 569 570 /// BRCOND - Conditional branch. The first operand is the chain, the 571 /// second is the condition, the third is the block to branch to if the 572 /// condition is true. If the type of the condition is not i1, then the 573 /// high bits must conform to getBooleanContents. 574 BRCOND, 575 576 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 577 /// that the condition is represented as condition code, and two nodes to 578 /// compare, rather than as a combined SetCC node. The operands in order 579 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 580 BR_CC, 581 582 /// INLINEASM - Represents an inline asm block. This node always has two 583 /// return values: a chain and a flag result. The inputs are as follows: 584 /// Operand #0 : Input chain. 585 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 586 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 587 /// Operand #3 : HasSideEffect, IsAlignStack bits. 588 /// After this, it is followed by a list of operands with this format: 589 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 590 /// of operands that follow, etc. See InlineAsm.h. 591 /// ... however many operands ... 592 /// Operand #last: Optional, an incoming flag. 593 /// 594 /// The variable width operands are required to represent target addressing 595 /// modes as a single "operand", even though they may have multiple 596 /// SDOperands. 597 INLINEASM, 598 599 /// EH_LABEL - Represents a label in mid basic block used to track 600 /// locations needed for debug and exception handling tables. These nodes 601 /// take a chain as input and return a chain. 602 EH_LABEL, 603 604 /// CATCHPAD - Represents a catchpad instruction. 605 CATCHPAD, 606 607 /// CATCHRET - Represents a return from a catch block funclet. Used for 608 /// MSVC compatible exception handling. Takes a chain operand and a 609 /// destination basic block operand. 610 CATCHRET, 611 612 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for 613 /// MSVC compatible exception handling. Takes only a chain operand. 614 CLEANUPRET, 615 616 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 617 /// value, the same type as the pointer type for the system, and an output 618 /// chain. 619 STACKSAVE, 620 621 /// STACKRESTORE has two operands, an input chain and a pointer to restore 622 /// to it returns an output chain. 623 STACKRESTORE, 624 625 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 626 /// of a call sequence, and carry arbitrary information that target might 627 /// want to know. The first operand is a chain, the rest are specified by 628 /// the target and not touched by the DAG optimizers. 629 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 630 CALLSEQ_START, // Beginning of a call sequence 631 CALLSEQ_END, // End of a call sequence 632 633 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 634 /// and the alignment. It returns a pair of values: the vaarg value and a 635 /// new chain. 636 VAARG, 637 638 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 639 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 640 /// source. 641 VACOPY, 642 643 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 644 /// pointer, and a SRCVALUE. 645 VAEND, VASTART, 646 647 /// SRCVALUE - This is a node type that holds a Value* that is used to 648 /// make reference to a value in the LLVM IR. 649 SRCVALUE, 650 651 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 652 /// reference metadata in the IR. 653 MDNODE_SDNODE, 654 655 /// PCMARKER - This corresponds to the pcmarker intrinsic. 656 PCMARKER, 657 658 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 659 /// It produces a chain and one i64 value. The only operand is a chain. 660 /// If i64 is not legal, the result will be expanded into smaller values. 661 /// Still, it returns an i64, so targets should set legality for i64. 662 /// The result is the content of the architecture-specific cycle 663 /// counter-like register (or other high accuracy low latency clock source). 664 READCYCLECOUNTER, 665 666 /// HANDLENODE node - Used as a handle for various purposes. 667 HANDLENODE, 668 669 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 670 /// takes as input a token chain, the pointer to the trampoline, the pointer 671 /// to the nested function, the pointer to pass for the 'nest' parameter, a 672 /// SRCVALUE for the trampoline and another for the nested function 673 /// (allowing targets to access the original Function*). 674 /// It produces a token chain as output. 675 INIT_TRAMPOLINE, 676 677 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 678 /// It takes a pointer to the trampoline and produces a (possibly) new 679 /// pointer to the same trampoline with platform-specific adjustments 680 /// applied. The pointer it returns points to an executable block of code. 681 ADJUST_TRAMPOLINE, 682 683 /// TRAP - Trapping instruction 684 TRAP, 685 686 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 687 DEBUGTRAP, 688 689 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 690 /// is the chain. The other operands are the address to prefetch, 691 /// read / write specifier, locality specifier and instruction / data cache 692 /// specifier. 693 PREFETCH, 694 695 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 696 /// This corresponds to the fence instruction. It takes an input chain, and 697 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 698 ATOMIC_FENCE, 699 700 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 701 /// This corresponds to "load atomic" instruction. 702 ATOMIC_LOAD, 703 704 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 705 /// This corresponds to "store atomic" instruction. 706 ATOMIC_STORE, 707 708 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 709 /// For double-word atomic operations: 710 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 711 /// swapLo, swapHi) 712 /// This corresponds to the cmpxchg instruction. 713 ATOMIC_CMP_SWAP, 714 715 /// Val, Success, OUTCHAIN 716 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 717 /// N.b. this is still a strong cmpxchg operation, so 718 /// Success == "Val == cmp". 719 ATOMIC_CMP_SWAP_WITH_SUCCESS, 720 721 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 722 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 723 /// For double-word atomic operations: 724 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 725 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 726 /// These correspond to the atomicrmw instruction. 727 ATOMIC_SWAP, 728 ATOMIC_LOAD_ADD, 729 ATOMIC_LOAD_SUB, 730 ATOMIC_LOAD_AND, 731 ATOMIC_LOAD_OR, 732 ATOMIC_LOAD_XOR, 733 ATOMIC_LOAD_NAND, 734 ATOMIC_LOAD_MIN, 735 ATOMIC_LOAD_MAX, 736 ATOMIC_LOAD_UMIN, 737 ATOMIC_LOAD_UMAX, 738 739 // Masked load and store - consecutive vector load and store operations 740 // with additional mask operand that prevents memory accesses to the 741 // masked-off lanes. 742 MLOAD, MSTORE, 743 744 // Masked gather and scatter - load and store operations for a vector of 745 // random addresses with additional mask operand that prevents memory 746 // accesses to the masked-off lanes. 747 MGATHER, MSCATTER, 748 749 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 750 /// is the chain and the second operand is the alloca pointer. 751 LIFETIME_START, LIFETIME_END, 752 753 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the 754 /// beginning and end of GC transition sequence, and carry arbitrary 755 /// information that target might need for lowering. The first operand is 756 /// a chain, the rest are specified by the target and not touched by the DAG 757 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be 758 /// nested. 759 GC_TRANSITION_START, 760 GC_TRANSITION_END, 761 762 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of 763 /// the most recent dynamic alloca. For most targets that would be 0, but 764 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time 765 /// known nonzero constant. The only operand here is the chain. 766 GET_DYNAMIC_AREA_OFFSET, 767 768 /// BUILTIN_OP_END - This must be the last enum value in this list. 769 /// The target-specific pre-isel opcode values start here. 770 BUILTIN_OP_END 771 }; 772 773 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 774 /// which do not reference a specific memory location should be less than 775 /// this value. Those that do must not be less than this value, and can 776 /// be used with SelectionDAG::getMemIntrinsicNode. 777 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300; 778 779 //===--------------------------------------------------------------------===// 780 /// MemIndexedMode enum - This enum defines the load / store indexed 781 /// addressing modes. 782 /// 783 /// UNINDEXED "Normal" load / store. The effective address is already 784 /// computed and is available in the base pointer. The offset 785 /// operand is always undefined. In addition to producing a 786 /// chain, an unindexed load produces one value (result of the 787 /// load); an unindexed store does not produce a value. 788 /// 789 /// PRE_INC Similar to the unindexed mode where the effective address is 790 /// PRE_DEC the value of the base pointer add / subtract the offset. 791 /// It considers the computation as being folded into the load / 792 /// store operation (i.e. the load / store does the address 793 /// computation as well as performing the memory transaction). 794 /// The base operand is always undefined. In addition to 795 /// producing a chain, pre-indexed load produces two values 796 /// (result of the load and the result of the address 797 /// computation); a pre-indexed store produces one value (result 798 /// of the address computation). 799 /// 800 /// POST_INC The effective address is the value of the base pointer. The 801 /// POST_DEC value of the offset operand is then added to / subtracted 802 /// from the base after memory transaction. In addition to 803 /// producing a chain, post-indexed load produces two values 804 /// (the result of the load and the result of the base +/- offset 805 /// computation); a post-indexed store produces one value (the 806 /// the result of the base +/- offset computation). 807 enum MemIndexedMode { 808 UNINDEXED = 0, 809 PRE_INC, 810 PRE_DEC, 811 POST_INC, 812 POST_DEC, 813 LAST_INDEXED_MODE 814 }; 815 816 //===--------------------------------------------------------------------===// 817 /// LoadExtType enum - This enum defines the three variants of LOADEXT 818 /// (load with extension). 819 /// 820 /// SEXTLOAD loads the integer operand and sign extends it to a larger 821 /// integer result type. 822 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 823 /// integer result type. 824 /// EXTLOAD is used for two things: floating point extending loads and 825 /// integer extending loads [the top bits are undefined]. 826 enum LoadExtType { 827 NON_EXTLOAD = 0, 828 EXTLOAD, 829 SEXTLOAD, 830 ZEXTLOAD, 831 LAST_LOADEXT_TYPE 832 }; 833 834 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 835 836 //===--------------------------------------------------------------------===// 837 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 838 /// below work out, when considering SETFALSE (something that never exists 839 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 840 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 841 /// to. If the "N" column is 1, the result of the comparison is undefined if 842 /// the input is a NAN. 843 /// 844 /// All of these (except for the 'always folded ops') should be handled for 845 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 846 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 847 /// 848 /// Note that these are laid out in a specific order to allow bit-twiddling 849 /// to transform conditions. 850 enum CondCode { 851 // Opcode N U L G E Intuitive operation 852 SETFALSE, // 0 0 0 0 Always false (always folded) 853 SETOEQ, // 0 0 0 1 True if ordered and equal 854 SETOGT, // 0 0 1 0 True if ordered and greater than 855 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 856 SETOLT, // 0 1 0 0 True if ordered and less than 857 SETOLE, // 0 1 0 1 True if ordered and less than or equal 858 SETONE, // 0 1 1 0 True if ordered and operands are unequal 859 SETO, // 0 1 1 1 True if ordered (no nans) 860 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 861 SETUEQ, // 1 0 0 1 True if unordered or equal 862 SETUGT, // 1 0 1 0 True if unordered or greater than 863 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 864 SETULT, // 1 1 0 0 True if unordered or less than 865 SETULE, // 1 1 0 1 True if unordered, less than, or equal 866 SETUNE, // 1 1 1 0 True if unordered or not equal 867 SETTRUE, // 1 1 1 1 Always true (always folded) 868 // Don't care operations: undefined if the input is a nan. 869 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 870 SETEQ, // 1 X 0 0 1 True if equal 871 SETGT, // 1 X 0 1 0 True if greater than 872 SETGE, // 1 X 0 1 1 True if greater than or equal 873 SETLT, // 1 X 1 0 0 True if less than 874 SETLE, // 1 X 1 0 1 True if less than or equal 875 SETNE, // 1 X 1 1 0 True if not equal 876 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 877 878 SETCC_INVALID // Marker value. 879 }; 880 881 /// Return true if this is a setcc instruction that performs a signed 882 /// comparison when used with integer operands. 883 inline bool isSignedIntSetCC(CondCode Code) { 884 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 885 } 886 887 /// Return true if this is a setcc instruction that performs an unsigned 888 /// comparison when used with integer operands. 889 inline bool isUnsignedIntSetCC(CondCode Code) { 890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 891 } 892 893 /// Return true if the specified condition returns true if the two operands to 894 /// the condition are equal. Note that if one of the two operands is a NaN, 895 /// this value is meaningless. 896 inline bool isTrueWhenEqual(CondCode Cond) { 897 return ((int)Cond & 1) != 0; 898 } 899 900 /// This function returns 0 if the condition is always false if an operand is 901 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if 902 /// the condition is undefined if the operand is a NaN. 903 inline unsigned getUnorderedFlavor(CondCode Cond) { 904 return ((int)Cond >> 3) & 3; 905 } 906 907 /// Return the operation corresponding to !(X op Y), where 'op' is a valid 908 /// SetCC operation. 909 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 910 911 /// Return the operation corresponding to (Y op X) when given the operation 912 /// for (X op Y). 913 CondCode getSetCCSwappedOperands(CondCode Operation); 914 915 /// Return the result of a logical OR between different comparisons of 916 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns 917 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 918 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 919 920 /// Return the result of a logical AND between different comparisons of 921 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns 922 /// SETCC_INVALID if it is not possible to represent the resultant comparison. 923 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 924 925 //===--------------------------------------------------------------------===// 926 /// This enum defines the various converts CONVERT_RNDSAT supports. 927 enum CvtCode { 928 CVT_FF, /// Float from Float 929 CVT_FS, /// Float from Signed 930 CVT_FU, /// Float from Unsigned 931 CVT_SF, /// Signed from Float 932 CVT_UF, /// Unsigned from Float 933 CVT_SS, /// Signed from Signed 934 CVT_SU, /// Signed from Unsigned 935 CVT_US, /// Unsigned from Signed 936 CVT_UU, /// Unsigned from Unsigned 937 CVT_INVALID /// Marker - Invalid opcode 938 }; 939 940} // end llvm::ISD namespace 941 942} // end llvm namespace 943 944#endif 945