MCInst.h revision cf3f89249deabb47c48f21abe3dcf44dbff3401f 
1//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the declaration of the MCInst and MCOperand classes, which
11// is the basic representation used to represent low-level machine code
12// instructions.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_MC_MCINST_H
17#define LLVM_MC_MCINST_H
18
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/System/DataTypes.h"
21
22namespace llvm {
23class raw_ostream;
24class MCAsmInfo;
25class MCExpr;
26
27/// MCOperand - Instances of this class represent operands of the MCInst class.
28/// This is a simple discriminated union.
29class MCOperand {
30  enum MachineOperandType {
31    kInvalid,                 ///< Uninitialized.
32    kRegister,                ///< Register operand.
33    kImmediate,               ///< Immediate operand.
34    kExpr                     ///< Relocatable immediate operand.
35  };
36  unsigned char Kind;
37
38  union {
39    unsigned RegVal;
40    int64_t ImmVal;
41    const MCExpr *ExprVal;
42  };
43public:
44
45  MCOperand() : Kind(kInvalid) {}
46
47  bool isValid() const { return Kind != kInvalid; }
48  bool isReg() const { return Kind == kRegister; }
49  bool isImm() const { return Kind == kImmediate; }
50  bool isExpr() const { return Kind == kExpr; }
51
52  /// getReg - Returns the register number.
53  unsigned getReg() const {
54    assert(isReg() && "This is not a register operand!");
55    return RegVal;
56  }
57
58  /// setReg - Set the register number.
59  void setReg(unsigned Reg) {
60    assert(isReg() && "This is not a register operand!");
61    RegVal = Reg;
62  }
63
64  int64_t getImm() const {
65    assert(isImm() && "This is not an immediate");
66    return ImmVal;
67  }
68  void setImm(int64_t Val) {
69    assert(isImm() && "This is not an immediate");
70    ImmVal = Val;
71  }
72
73  const MCExpr *getExpr() const {
74    assert(isExpr() && "This is not an expression");
75    return ExprVal;
76  }
77  void setExpr(const MCExpr *Val) {
78    assert(isExpr() && "This is not an expression");
79    ExprVal = Val;
80  }
81
82  static MCOperand CreateReg(unsigned Reg) {
83    MCOperand Op;
84    Op.Kind = kRegister;
85    Op.RegVal = Reg;
86    return Op;
87  }
88  static MCOperand CreateImm(int64_t Val) {
89    MCOperand Op;
90    Op.Kind = kImmediate;
91    Op.ImmVal = Val;
92    return Op;
93  }
94  static MCOperand CreateExpr(const MCExpr *Val) {
95    MCOperand Op;
96    Op.Kind = kExpr;
97    Op.ExprVal = Val;
98    return Op;
99  }
100
101  void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
102  void dump() const;
103};
104
105
106/// MCInst - Instances of this class represent a single low-level machine
107/// instruction.
108class MCInst {
109  unsigned Opcode;
110  SmallVector<MCOperand, 8> Operands;
111public:
112  MCInst() : Opcode(0) {}
113
114  void setOpcode(unsigned Op) { Opcode = Op; }
115
116  unsigned getOpcode() const { return Opcode; }
117
118  const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
119  MCOperand &getOperand(unsigned i) { return Operands[i]; }
120  unsigned getNumOperands() const { return Operands.size(); }
121
122  void addOperand(const MCOperand &Op) {
123    Operands.push_back(Op);
124  }
125
126  void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
127  void dump() const;
128};
129
130
131} // end namespace llvm
132
133#endif
134