Target.td revision 37ed9c199ca639565f6ce88105f9e39e898d82d0
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/IR/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex<int size, int offset = 0> { 26 string Namespace = ""; 27 28 // Size - Size (in bits) of the sub-registers represented by this index. 29 int Size = size; 30 31 // Offset - Offset of the first bit that is part of this sub-register index. 32 // Set it to -1 if the same index is used to represent sub-registers that can 33 // be at different offsets (for example when using an index to access an 34 // element in a register tuple). 35 int Offset = offset; 36 37 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 38 // This indicates that this SubRegIndex is the result of composing A and B. 39 // See ComposedSubRegIndex. 40 list<SubRegIndex> ComposedOf = []; 41 42 // CoveringSubRegIndices - A list of two or more sub-register indexes that 43 // cover this sub-register. 44 // 45 // This field should normally be left blank as TableGen can infer it. 46 // 47 // TableGen automatically detects sub-registers that straddle the registers 48 // in the SubRegs field of a Register definition. For example: 49 // 50 // Q0 = dsub_0 -> D0, dsub_1 -> D1 51 // Q1 = dsub_0 -> D2, dsub_1 -> D3 52 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 53 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 54 // 55 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 57 // CoveringSubRegIndices = [dsub_1, dsub_2]. 58 list<SubRegIndex> CoveringSubRegIndices = []; 59} 60 61// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 62// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 63class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, 65 !if(!eq(B.Offset, -1), -1, 66 !add(A.Offset, B.Offset)))> { 67 // See SubRegIndex. 68 let ComposedOf = [A, B]; 69} 70 71// RegAltNameIndex - The alternate name set to use for register operands of 72// this register class when printing. 73class RegAltNameIndex { 74 string Namespace = ""; 75} 76def NoRegAltName : RegAltNameIndex; 77 78// Register - You should define one instance of this class for each register 79// in the target machine. String n will become the "name" of the register. 80class Register<string n, list<string> altNames = []> { 81 string Namespace = ""; 82 string AsmName = n; 83 list<string> AltNames = altNames; 84 85 // Aliases - A list of registers that this register overlaps with. A read or 86 // modification of this register can potentially read or modify the aliased 87 // registers. 88 list<Register> Aliases = []; 89 90 // SubRegs - A list of registers that are parts of this register. Note these 91 // are "immediate" sub-registers and the registers within the list do not 92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 93 // not [AX, AH, AL]. 94 list<Register> SubRegs = []; 95 96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 97 // to address it. Sub-sub-register indices are automatically inherited from 98 // SubRegs. 99 list<SubRegIndex> SubRegIndices = []; 100 101 // RegAltNameIndices - The alternate name indices which are valid for this 102 // register. 103 list<RegAltNameIndex> RegAltNameIndices = []; 104 105 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 106 // These values can be determined by locating the <target>.h file in the 107 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 108 // order of these names correspond to the enumeration used by gcc. A value of 109 // -1 indicates that the gcc number is undefined and -2 that register number 110 // is invalid for this mode/flavour. 111 list<int> DwarfNumbers = []; 112 113 // CostPerUse - Additional cost of instructions using this register compared 114 // to other registers in its class. The register allocator will try to 115 // minimize the number of instructions using a register with a CostPerUse. 116 // This is used by the x86-64 and ARM Thumb targets where some registers 117 // require larger instruction encodings. 118 int CostPerUse = 0; 119 120 // CoveredBySubRegs - When this bit is set, the value of this register is 121 // completely determined by the value of its sub-registers. For example, the 122 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 123 // covered by its sub-register AX. 124 bit CoveredBySubRegs = 0; 125 126 // HWEncoding - The target specific hardware encoding for this register. 127 bits<16> HWEncoding = 0; 128} 129 130// RegisterWithSubRegs - This can be used to define instances of Register which 131// need to specify sub-registers. 132// List "subregs" specifies which registers are sub-registers to this one. This 133// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 134// This allows the code generator to be careful not to put two values with 135// overlapping live ranges into registers which alias. 136class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 137 let SubRegs = subregs; 138} 139 140// DAGOperand - An empty base class that unifies RegisterClass's and other forms 141// of Operand's that are legal as type qualifiers in DAG patterns. This should 142// only ever be used for defining multiclasses that are polymorphic over both 143// RegisterClass's and other Operand's. 144class DAGOperand { } 145 146// RegisterClass - Now that all of the registers are defined, and aliases 147// between registers are defined, specify which registers belong to which 148// register classes. This also defines the default allocation order of 149// registers by register allocators. 150// 151class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 152 dag regList, RegAltNameIndex idx = NoRegAltName> 153 : DAGOperand { 154 string Namespace = namespace; 155 156 // RegType - Specify the list ValueType of the registers in this register 157 // class. Note that all registers in a register class must have the same 158 // ValueTypes. This is a list because some targets permit storing different 159 // types in same register, for example vector values with 128-bit total size, 160 // but different count/size of items, like SSE on x86. 161 // 162 list<ValueType> RegTypes = regTypes; 163 164 // Size - Specify the spill size in bits of the registers. A default value of 165 // zero lets tablgen pick an appropriate size. 166 int Size = 0; 167 168 // Alignment - Specify the alignment required of the registers when they are 169 // stored or loaded to memory. 170 // 171 int Alignment = alignment; 172 173 // CopyCost - This value is used to specify the cost of copying a value 174 // between two registers in this register class. The default value is one 175 // meaning it takes a single instruction to perform the copying. A negative 176 // value means copying is extremely expensive or impossible. 177 int CopyCost = 1; 178 179 // MemberList - Specify which registers are in this class. If the 180 // allocation_order_* method are not specified, this also defines the order of 181 // allocation used by the register allocator. 182 // 183 dag MemberList = regList; 184 185 // AltNameIndex - The alternate register name to use when printing operands 186 // of this register class. Every register in the register class must have 187 // a valid alternate name for the given index. 188 RegAltNameIndex altNameIndex = idx; 189 190 // isAllocatable - Specify that the register class can be used for virtual 191 // registers and register allocation. Some register classes are only used to 192 // model instruction operand constraints, and should have isAllocatable = 0. 193 bit isAllocatable = 1; 194 195 // AltOrders - List of alternative allocation orders. The default order is 196 // MemberList itself, and that is good enough for most targets since the 197 // register allocators automatically remove reserved registers and move 198 // callee-saved registers to the end. 199 list<dag> AltOrders = []; 200 201 // AltOrderSelect - The body of a function that selects the allocation order 202 // to use in a given machine function. The code will be inserted in a 203 // function like this: 204 // 205 // static inline unsigned f(const MachineFunction &MF) { ... } 206 // 207 // The function should return 0 to select the default order defined by 208 // MemberList, 1 to select the first AltOrders entry and so on. 209 code AltOrderSelect = [{}]; 210} 211 212// The memberList in a RegisterClass is a dag of set operations. TableGen 213// evaluates these set operations and expand them into register lists. These 214// are the most common operation, see test/TableGen/SetTheory.td for more 215// examples of what is possible: 216// 217// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 218// register class, or a sub-expression. This is also the way to simply list 219// registers. 220// 221// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 222// 223// (and GPR, CSR) - Set intersection. All registers from the first set that are 224// also in the second set. 225// 226// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 227// numbered registers. Takes an optional 4th operand which is a stride to use 228// when generating the sequence. 229// 230// (shl GPR, 4) - Remove the first N elements. 231// 232// (trunc GPR, 4) - Truncate after the first N elements. 233// 234// (rotl GPR, 1) - Rotate N places to the left. 235// 236// (rotr GPR, 1) - Rotate N places to the right. 237// 238// (decimate GPR, 2) - Pick every N'th element, starting with the first. 239// 240// (interleave A, B, ...) - Interleave the elements from each argument list. 241// 242// All of these operators work on ordered sets, not lists. That means 243// duplicates are removed from sub-expressions. 244 245// Set operators. The rest is defined in TargetSelectionDAG.td. 246def sequence; 247def decimate; 248def interleave; 249 250// RegisterTuples - Automatically generate super-registers by forming tuples of 251// sub-registers. This is useful for modeling register sequence constraints 252// with pseudo-registers that are larger than the architectural registers. 253// 254// The sub-register lists are zipped together: 255// 256// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 257// 258// Generates the same registers as: 259// 260// let SubRegIndices = [sube, subo] in { 261// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 262// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 263// } 264// 265// The generated pseudo-registers inherit super-classes and fields from their 266// first sub-register. Most fields from the Register class are inferred, and 267// the AsmName and Dwarf numbers are cleared. 268// 269// RegisterTuples instances can be used in other set operations to form 270// register classes and so on. This is the only way of using the generated 271// registers. 272class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 273 // SubRegs - N lists of registers to be zipped up. Super-registers are 274 // synthesized from the first element of each SubRegs list, the second 275 // element and so on. 276 list<dag> SubRegs = Regs; 277 278 // SubRegIndices - N SubRegIndex instances. This provides the names of the 279 // sub-registers in the synthesized super-registers. 280 list<SubRegIndex> SubRegIndices = Indices; 281} 282 283 284//===----------------------------------------------------------------------===// 285// DwarfRegNum - This class provides a mapping of the llvm register enumeration 286// to the register numbering used by gcc and gdb. These values are used by a 287// debug information writer to describe where values may be located during 288// execution. 289class DwarfRegNum<list<int> Numbers> { 290 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 291 // These values can be determined by locating the <target>.h file in the 292 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 293 // order of these names correspond to the enumeration used by gcc. A value of 294 // -1 indicates that the gcc number is undefined and -2 that register number 295 // is invalid for this mode/flavour. 296 list<int> DwarfNumbers = Numbers; 297} 298 299// DwarfRegAlias - This class declares that a given register uses the same dwarf 300// numbers as another one. This is useful for making it clear that the two 301// registers do have the same number. It also lets us build a mapping 302// from dwarf register number to llvm register. 303class DwarfRegAlias<Register reg> { 304 Register DwarfAlias = reg; 305} 306 307//===----------------------------------------------------------------------===// 308// Pull in the common support for scheduling 309// 310include "llvm/Target/TargetSchedule.td" 311 312class Predicate; // Forward def 313 314//===----------------------------------------------------------------------===// 315// Instruction set description - These classes correspond to the C++ classes in 316// the Target/TargetInstrInfo.h file. 317// 318class Instruction { 319 string Namespace = ""; 320 321 dag OutOperandList; // An dag containing the MI def operand list. 322 dag InOperandList; // An dag containing the MI use operand list. 323 string AsmString = ""; // The .s format to print the instruction with. 324 325 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 326 // otherwise, uninitialized. 327 list<dag> Pattern; 328 329 // The follow state will eventually be inferred automatically from the 330 // instruction pattern. 331 332 list<Register> Uses = []; // Default to using no non-operand registers 333 list<Register> Defs = []; // Default to modifying no non-operand registers 334 335 // Predicates - List of predicates which will be turned into isel matching 336 // code. 337 list<Predicate> Predicates = []; 338 339 // Size - Size of encoded instruction, or zero if the size cannot be determined 340 // from the opcode. 341 int Size = 0; 342 343 // DecoderNamespace - The "namespace" in which this instruction exists, on 344 // targets like ARM which multiple ISA namespaces exist. 345 string DecoderNamespace = ""; 346 347 // Code size, for instruction selection. 348 // FIXME: What does this actually mean? 349 int CodeSize = 0; 350 351 // Added complexity passed onto matching pattern. 352 int AddedComplexity = 0; 353 354 // These bits capture information about the high-level semantics of the 355 // instruction. 356 bit isReturn = 0; // Is this instruction a return instruction? 357 bit isBranch = 0; // Is this instruction a branch instruction? 358 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 359 bit isCompare = 0; // Is this instruction a comparison instruction? 360 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 361 bit isBitcast = 0; // Is this instruction a bitcast instruction? 362 bit isSelect = 0; // Is this instruction a select instruction? 363 bit isBarrier = 0; // Can control flow fall through this instruction? 364 bit isCall = 0; // Is this instruction a call instruction? 365 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 366 bit mayLoad = ?; // Is it possible for this inst to read memory? 367 bit mayStore = ?; // Is it possible for this inst to write memory? 368 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 369 bit isCommutable = 0; // Is this 3 operand instruction commutable? 370 bit isTerminator = 0; // Is this part of the terminator for a basic block? 371 bit isReMaterializable = 0; // Is this instruction re-materializable? 372 bit isPredicable = 0; // Is this instruction predicable? 373 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 374 bit usesCustomInserter = 0; // Pseudo instr needing special help. 375 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 376 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 377 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 378 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 379 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 380 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 381 bit isRegSequence = 0; // Is this instruction a kind of reg sequence? 382 // If so, make sure to override 383 // TargetInstrInfo::getRegSequenceLikeInputs. 384 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 385 // If so, won't have encoding information for 386 // the [MC]CodeEmitter stuff. 387 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg? 388 // If so, make sure to override 389 // TargetInstrInfo::getExtractSubregLikeInputs. 390 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg? 391 // If so, make sure to override 392 // TargetInstrInfo::getInsertSubregLikeInputs. 393 394 // Side effect flags - When set, the flags have these meanings: 395 // 396 // hasSideEffects - The instruction has side effects that are not 397 // captured by any operands of the instruction or other flags. 398 // 399 // neverHasSideEffects (deprecated) - Set on an instruction with no pattern 400 // if it has no side effects. This is now equivalent to setting 401 // "hasSideEffects = 0". 402 bit hasSideEffects = ?; 403 bit neverHasSideEffects = 0; 404 405 // Is this instruction a "real" instruction (with a distinct machine 406 // encoding), or is it a pseudo instruction used for codegen modeling 407 // purposes. 408 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 409 // instructions can (and often do) still have encoding information 410 // associated with them. Once we've migrated all of them over to true 411 // pseudo-instructions that are lowered to real instructions prior to 412 // the printer/emitter, we can remove this attribute and just use isPseudo. 413 // 414 // The intended use is: 415 // isPseudo: Does not have encoding information and should be expanded, 416 // at the latest, during lowering to MCInst. 417 // 418 // isCodeGenOnly: Does have encoding information and can go through to the 419 // CodeEmitter unchanged, but duplicates a canonical instruction 420 // definition's encoding and should be ignored when constructing the 421 // assembler match tables. 422 bit isCodeGenOnly = 0; 423 424 // Is this instruction a pseudo instruction for use by the assembler parser. 425 bit isAsmParserOnly = 0; 426 427 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 428 429 // Scheduling information from TargetSchedule.td. 430 list<SchedReadWrite> SchedRW; 431 432 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 433 434 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 435 /// be encoded into the output machineinstr. 436 string DisableEncoding = ""; 437 438 string PostEncoderMethod = ""; 439 string DecoderMethod = ""; 440 441 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 442 bits<64> TSFlags = 0; 443 444 ///@name Assembler Parser Support 445 ///@{ 446 447 string AsmMatchConverter = ""; 448 449 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 450 /// two-operand matcher inst-alias for a three operand instruction. 451 /// For example, the arm instruction "add r3, r3, r5" can be written 452 /// as "add r3, r5". The constraint is of the same form as a tied-operand 453 /// constraint. For example, "$Rn = $Rd". 454 string TwoOperandAliasConstraint = ""; 455 456 ///@} 457 458 /// UseNamedOperandTable - If set, the operand indices of this instruction 459 /// can be queried via the getNamedOperandIdx() function which is generated 460 /// by TableGen. 461 bit UseNamedOperandTable = 0; 462} 463 464/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 465/// Which instruction it expands to and how the operands map from the 466/// pseudo. 467class PseudoInstExpansion<dag Result> { 468 dag ResultInst = Result; // The instruction to generate. 469 bit isPseudo = 1; 470} 471 472/// Predicates - These are extra conditionals which are turned into instruction 473/// selector matching code. Currently each predicate is just a string. 474class Predicate<string cond> { 475 string CondString = cond; 476 477 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 478 /// matcher, this is true. Targets should set this by inheriting their 479 /// feature from the AssemblerPredicate class in addition to Predicate. 480 bit AssemblerMatcherPredicate = 0; 481 482 /// AssemblerCondString - Name of the subtarget feature being tested used 483 /// as alternative condition string used for assembler matcher. 484 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 485 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 486 /// It can also list multiple features separated by ",". 487 /// e.g. "ModeThumb,FeatureThumb2" is translated to 488 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 489 string AssemblerCondString = ""; 490 491 /// PredicateName - User-level name to use for the predicate. Mainly for use 492 /// in diagnostics such as missing feature errors in the asm matcher. 493 string PredicateName = ""; 494} 495 496/// NoHonorSignDependentRounding - This predicate is true if support for 497/// sign-dependent-rounding is not enabled. 498def NoHonorSignDependentRounding 499 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 500 501class Requires<list<Predicate> preds> { 502 list<Predicate> Predicates = preds; 503} 504 505/// ops definition - This is just a simple marker used to identify the operand 506/// list for an instruction. outs and ins are identical both syntactically and 507/// semanticallyr; they are used to define def operands and use operands to 508/// improve readibility. This should be used like this: 509/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 510def ops; 511def outs; 512def ins; 513 514/// variable_ops definition - Mark this instruction as taking a variable number 515/// of operands. 516def variable_ops; 517 518 519/// PointerLikeRegClass - Values that are designed to have pointer width are 520/// derived from this. TableGen treats the register class as having a symbolic 521/// type that it doesn't know, and resolves the actual regclass to use by using 522/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 523class PointerLikeRegClass<int Kind> { 524 int RegClassKind = Kind; 525} 526 527 528/// ptr_rc definition - Mark this operand as being a pointer value whose 529/// register class is resolved dynamically via a callback to TargetInstrInfo. 530/// FIXME: We should probably change this to a class which contain a list of 531/// flags. But currently we have but one flag. 532def ptr_rc : PointerLikeRegClass<0>; 533 534/// unknown definition - Mark this operand as being of unknown type, causing 535/// it to be resolved by inference in the context it is used. 536class unknown_class; 537def unknown : unknown_class; 538 539/// AsmOperandClass - Representation for the kinds of operands which the target 540/// specific parser can create and the assembly matcher may need to distinguish. 541/// 542/// Operand classes are used to define the order in which instructions are 543/// matched, to ensure that the instruction which gets matched for any 544/// particular list of operands is deterministic. 545/// 546/// The target specific parser must be able to classify a parsed operand into a 547/// unique class which does not partially overlap with any other classes. It can 548/// match a subset of some other class, in which case the super class field 549/// should be defined. 550class AsmOperandClass { 551 /// The name to use for this class, which should be usable as an enum value. 552 string Name = ?; 553 554 /// The super classes of this operand. 555 list<AsmOperandClass> SuperClasses = []; 556 557 /// The name of the method on the target specific operand to call to test 558 /// whether the operand is an instance of this class. If not set, this will 559 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 560 /// signature should be: 561 /// bool isFoo() const; 562 string PredicateMethod = ?; 563 564 /// The name of the method on the target specific operand to call to add the 565 /// target specific operand to an MCInst. If not set, this will default to 566 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 567 /// signature should be: 568 /// void addFooOperands(MCInst &Inst, unsigned N) const; 569 string RenderMethod = ?; 570 571 /// The name of the method on the target specific operand to call to custom 572 /// handle the operand parsing. This is useful when the operands do not relate 573 /// to immediates or registers and are very instruction specific (as flags to 574 /// set in a processor register, coprocessor number, ...). 575 string ParserMethod = ?; 576 577 // The diagnostic type to present when referencing this operand in a 578 // match failure error message. By default, use a generic "invalid operand" 579 // diagnostic. The target AsmParser maps these codes to text. 580 string DiagnosticType = ""; 581} 582 583def ImmAsmOperand : AsmOperandClass { 584 let Name = "Imm"; 585} 586 587/// Operand Types - These provide the built-in operand types that may be used 588/// by a target. Targets can optionally provide their own operand types as 589/// needed, though this should not be needed for RISC targets. 590class Operand<ValueType ty> : DAGOperand { 591 ValueType Type = ty; 592 string PrintMethod = "printOperand"; 593 string EncoderMethod = ""; 594 string DecoderMethod = ""; 595 string OperandType = "OPERAND_UNKNOWN"; 596 dag MIOperandInfo = (ops); 597 598 // MCOperandPredicate - Optionally, a code fragment operating on 599 // const MCOperand &MCOp, and returning a bool, to indicate if 600 // the value of MCOp is valid for the specific subclass of Operand 601 code MCOperandPredicate; 602 603 // ParserMatchClass - The "match class" that operands of this type fit 604 // in. Match classes are used to define the order in which instructions are 605 // match, to ensure that which instructions gets matched is deterministic. 606 // 607 // The target specific parser must be able to classify an parsed operand into 608 // a unique class, which does not partially overlap with any other classes. It 609 // can match a subset of some other class, in which case the AsmOperandClass 610 // should declare the other operand as one of its super classes. 611 AsmOperandClass ParserMatchClass = ImmAsmOperand; 612} 613 614class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 615 : DAGOperand { 616 // RegClass - The register class of the operand. 617 RegisterClass RegClass = regclass; 618 // PrintMethod - The target method to call to print register operands of 619 // this type. The method normally will just use an alt-name index to look 620 // up the name to print. Default to the generic printOperand(). 621 string PrintMethod = pm; 622 // ParserMatchClass - The "match class" that operands of this type fit 623 // in. Match classes are used to define the order in which instructions are 624 // match, to ensure that which instructions gets matched is deterministic. 625 // 626 // The target specific parser must be able to classify an parsed operand into 627 // a unique class, which does not partially overlap with any other classes. It 628 // can match a subset of some other class, in which case the AsmOperandClass 629 // should declare the other operand as one of its super classes. 630 AsmOperandClass ParserMatchClass; 631} 632 633let OperandType = "OPERAND_IMMEDIATE" in { 634def i1imm : Operand<i1>; 635def i8imm : Operand<i8>; 636def i16imm : Operand<i16>; 637def i32imm : Operand<i32>; 638def i64imm : Operand<i64>; 639 640def f32imm : Operand<f32>; 641def f64imm : Operand<f64>; 642} 643 644/// zero_reg definition - Special node to stand for the zero register. 645/// 646def zero_reg; 647 648/// All operands which the MC layer classifies as predicates should inherit from 649/// this class in some manner. This is already handled for the most commonly 650/// used PredicateOperand, but may be useful in other circumstances. 651class PredicateOp; 652 653/// OperandWithDefaultOps - This Operand class can be used as the parent class 654/// for an Operand that needs to be initialized with a default value if 655/// no value is supplied in a pattern. This class can be used to simplify the 656/// pattern definitions for instructions that have target specific flags 657/// encoded as immediate operands. 658class OperandWithDefaultOps<ValueType ty, dag defaultops> 659 : Operand<ty> { 660 dag DefaultOps = defaultops; 661} 662 663/// PredicateOperand - This can be used to define a predicate operand for an 664/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 665/// AlwaysVal specifies the value of this predicate when set to "always 666/// execute". 667class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 668 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 669 let MIOperandInfo = OpTypes; 670} 671 672/// OptionalDefOperand - This is used to define a optional definition operand 673/// for an instruction. DefaultOps is the register the operand represents if 674/// none is supplied, e.g. zero_reg. 675class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 676 : OperandWithDefaultOps<ty, defaultops> { 677 let MIOperandInfo = OpTypes; 678} 679 680 681// InstrInfo - This class should only be instantiated once to provide parameters 682// which are global to the target machine. 683// 684class InstrInfo { 685 // Target can specify its instructions in either big or little-endian formats. 686 // For instance, while both Sparc and PowerPC are big-endian platforms, the 687 // Sparc manual specifies its instructions in the format [31..0] (big), while 688 // PowerPC specifies them using the format [0..31] (little). 689 bit isLittleEndianEncoding = 0; 690 691 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 692 // by default, and TableGen will infer their value from the instruction 693 // pattern when possible. 694 // 695 // Normally, TableGen will issue an error it it can't infer the value of a 696 // property that hasn't been set explicitly. When guessInstructionProperties 697 // is set, it will guess a safe value instead. 698 // 699 // This option is a temporary migration help. It will go away. 700 bit guessInstructionProperties = 1; 701 702 // TableGen's instruction encoder generator has support for matching operands 703 // to bit-field variables both by name and by position. While matching by 704 // name is preferred, this is currently not possible for complex operands, 705 // and some targets still reply on the positional encoding rules. When 706 // generating a decoder for such targets, the positional encoding rules must 707 // be used by the decoder generator as well. 708 // 709 // This option is temporary; it will go away once the TableGen decoder 710 // generator has better support for complex operands and targets have 711 // migrated away from using positionally encoded operands. 712 bit decodePositionallyEncodedOperands = 0; 713 714 // When set, this indicates that there will be no overlap between those 715 // operands that are matched by ordering (positional operands) and those 716 // matched by name. 717 // 718 // This option is temporary; it will go away once the TableGen decoder 719 // generator has better support for complex operands and targets have 720 // migrated away from using positionally encoded operands. 721 bit noNamedPositionallyEncodedOperands = 0; 722} 723 724// Standard Pseudo Instructions. 725// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 726// Only these instructions are allowed in the TargetOpcode namespace. 727let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 728def PHI : Instruction { 729 let OutOperandList = (outs); 730 let InOperandList = (ins variable_ops); 731 let AsmString = "PHINODE"; 732} 733def INLINEASM : Instruction { 734 let OutOperandList = (outs); 735 let InOperandList = (ins variable_ops); 736 let AsmString = ""; 737 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 738} 739def CFI_INSTRUCTION : Instruction { 740 let OutOperandList = (outs); 741 let InOperandList = (ins i32imm:$id); 742 let AsmString = ""; 743 let hasCtrlDep = 1; 744 let isNotDuplicable = 1; 745} 746def EH_LABEL : Instruction { 747 let OutOperandList = (outs); 748 let InOperandList = (ins i32imm:$id); 749 let AsmString = ""; 750 let hasCtrlDep = 1; 751 let isNotDuplicable = 1; 752} 753def GC_LABEL : Instruction { 754 let OutOperandList = (outs); 755 let InOperandList = (ins i32imm:$id); 756 let AsmString = ""; 757 let hasCtrlDep = 1; 758 let isNotDuplicable = 1; 759} 760def KILL : Instruction { 761 let OutOperandList = (outs); 762 let InOperandList = (ins variable_ops); 763 let AsmString = ""; 764 let neverHasSideEffects = 1; 765} 766def EXTRACT_SUBREG : Instruction { 767 let OutOperandList = (outs unknown:$dst); 768 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 769 let AsmString = ""; 770 let neverHasSideEffects = 1; 771} 772def INSERT_SUBREG : Instruction { 773 let OutOperandList = (outs unknown:$dst); 774 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 775 let AsmString = ""; 776 let neverHasSideEffects = 1; 777 let Constraints = "$supersrc = $dst"; 778} 779def IMPLICIT_DEF : Instruction { 780 let OutOperandList = (outs unknown:$dst); 781 let InOperandList = (ins); 782 let AsmString = ""; 783 let neverHasSideEffects = 1; 784 let isReMaterializable = 1; 785 let isAsCheapAsAMove = 1; 786} 787def SUBREG_TO_REG : Instruction { 788 let OutOperandList = (outs unknown:$dst); 789 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 790 let AsmString = ""; 791 let neverHasSideEffects = 1; 792} 793def COPY_TO_REGCLASS : Instruction { 794 let OutOperandList = (outs unknown:$dst); 795 let InOperandList = (ins unknown:$src, i32imm:$regclass); 796 let AsmString = ""; 797 let neverHasSideEffects = 1; 798 let isAsCheapAsAMove = 1; 799} 800def DBG_VALUE : Instruction { 801 let OutOperandList = (outs); 802 let InOperandList = (ins variable_ops); 803 let AsmString = "DBG_VALUE"; 804 let neverHasSideEffects = 1; 805} 806def REG_SEQUENCE : Instruction { 807 let OutOperandList = (outs unknown:$dst); 808 let InOperandList = (ins unknown:$supersrc, variable_ops); 809 let AsmString = ""; 810 let neverHasSideEffects = 1; 811 let isAsCheapAsAMove = 1; 812} 813def COPY : Instruction { 814 let OutOperandList = (outs unknown:$dst); 815 let InOperandList = (ins unknown:$src); 816 let AsmString = ""; 817 let neverHasSideEffects = 1; 818 let isAsCheapAsAMove = 1; 819} 820def BUNDLE : Instruction { 821 let OutOperandList = (outs); 822 let InOperandList = (ins variable_ops); 823 let AsmString = "BUNDLE"; 824} 825def LIFETIME_START : Instruction { 826 let OutOperandList = (outs); 827 let InOperandList = (ins i32imm:$id); 828 let AsmString = "LIFETIME_START"; 829 let neverHasSideEffects = 1; 830} 831def LIFETIME_END : Instruction { 832 let OutOperandList = (outs); 833 let InOperandList = (ins i32imm:$id); 834 let AsmString = "LIFETIME_END"; 835 let neverHasSideEffects = 1; 836} 837def STACKMAP : Instruction { 838 let OutOperandList = (outs); 839 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); 840 let isCall = 1; 841 let mayLoad = 1; 842 let usesCustomInserter = 1; 843} 844def PATCHPOINT : Instruction { 845 let OutOperandList = (outs unknown:$dst); 846 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, 847 i32imm:$nargs, i32imm:$cc, variable_ops); 848 let isCall = 1; 849 let mayLoad = 1; 850 let usesCustomInserter = 1; 851} 852def LOAD_STACK_GUARD : Instruction { 853 let OutOperandList = (outs ptr_rc:$dst); 854 let InOperandList = (ins); 855 let mayLoad = 1; 856 bit isReMaterializable = 1; 857 let hasSideEffects = 0; 858 bit isPseudo = 1; 859} 860} 861 862//===----------------------------------------------------------------------===// 863// AsmParser - This class can be implemented by targets that wish to implement 864// .s file parsing. 865// 866// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 867// syntax on X86 for example). 868// 869class AsmParser { 870 // AsmParserClassName - This specifies the suffix to use for the asmparser 871 // class. Generated AsmParser classes are always prefixed with the target 872 // name. 873 string AsmParserClassName = "AsmParser"; 874 875 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 876 // function of the AsmParser class to call on every matched instruction. 877 // This can be used to perform target specific instruction post-processing. 878 string AsmParserInstCleanup = ""; 879 880 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 881 // written register name matcher 882 bit ShouldEmitMatchRegisterName = 1; 883 884 /// Does the instruction mnemonic allow '.' 885 bit MnemonicContainsDot = 0; 886} 887def DefaultAsmParser : AsmParser; 888 889//===----------------------------------------------------------------------===// 890// AsmParserVariant - Subtargets can have multiple different assembly parsers 891// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 892// implemented by targets to describe such variants. 893// 894class AsmParserVariant { 895 // Variant - AsmParsers can be of multiple different variants. Variants are 896 // used to support targets that need to parser multiple formats for the 897 // assembly language. 898 int Variant = 0; 899 900 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 901 string Name = ""; 902 903 // CommentDelimiter - If given, the delimiter string used to recognize 904 // comments which are hard coded in the .td assembler strings for individual 905 // instructions. 906 string CommentDelimiter = ""; 907 908 // RegisterPrefix - If given, the token prefix which indicates a register 909 // token. This is used by the matcher to automatically recognize hard coded 910 // register tokens as constrained registers, instead of tokens, for the 911 // purposes of matching. 912 string RegisterPrefix = ""; 913} 914def DefaultAsmParserVariant : AsmParserVariant; 915 916/// AssemblerPredicate - This is a Predicate that can be used when the assembler 917/// matches instructions and aliases. 918class AssemblerPredicate<string cond, string name = ""> { 919 bit AssemblerMatcherPredicate = 1; 920 string AssemblerCondString = cond; 921 string PredicateName = name; 922} 923 924/// TokenAlias - This class allows targets to define assembler token 925/// operand aliases. That is, a token literal operand which is equivalent 926/// to another, canonical, token literal. For example, ARM allows: 927/// vmov.u32 s4, #0 -> vmov.i32, #0 928/// 'u32' is a more specific designator for the 32-bit integer type specifier 929/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 930/// def : TokenAlias<".u32", ".i32">; 931/// 932/// This works by marking the match class of 'From' as a subclass of the 933/// match class of 'To'. 934class TokenAlias<string From, string To> { 935 string FromToken = From; 936 string ToToken = To; 937} 938 939/// MnemonicAlias - This class allows targets to define assembler mnemonic 940/// aliases. This should be used when all forms of one mnemonic are accepted 941/// with a different mnemonic. For example, X86 allows: 942/// sal %al, 1 -> shl %al, 1 943/// sal %ax, %cl -> shl %ax, %cl 944/// sal %eax, %cl -> shl %eax, %cl 945/// etc. Though "sal" is accepted with many forms, all of them are directly 946/// translated to a shl, so it can be handled with (in the case of X86, it 947/// actually has one for each suffix as well): 948/// def : MnemonicAlias<"sal", "shl">; 949/// 950/// Mnemonic aliases are mapped before any other translation in the match phase, 951/// and do allow Requires predicates, e.g.: 952/// 953/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 954/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 955/// 956/// Mnemonic aliases can also be constrained to specific variants, e.g.: 957/// 958/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 959/// 960/// If no variant (e.g., "att" or "intel") is specified then the alias is 961/// applied unconditionally. 962class MnemonicAlias<string From, string To, string VariantName = ""> { 963 string FromMnemonic = From; 964 string ToMnemonic = To; 965 string AsmVariantName = VariantName; 966 967 // Predicates - Predicates that must be true for this remapping to happen. 968 list<Predicate> Predicates = []; 969} 970 971/// InstAlias - This defines an alternate assembly syntax that is allowed to 972/// match an instruction that has a different (more canonical) assembly 973/// representation. 974class InstAlias<string Asm, dag Result, int Emit = 1> { 975 string AsmString = Asm; // The .s format to match the instruction with. 976 dag ResultInst = Result; // The MCInst to generate. 977 978 // This determines which order the InstPrinter detects aliases for 979 // printing. A larger value makes the alias more likely to be 980 // emitted. The Instruction's own definition is notionally 0.5, so 0 981 // disables printing and 1 enables it if there are no conflicting aliases. 982 int EmitPriority = Emit; 983 984 // Predicates - Predicates that must be true for this to match. 985 list<Predicate> Predicates = []; 986} 987 988//===----------------------------------------------------------------------===// 989// AsmWriter - This class can be implemented by targets that need to customize 990// the format of the .s file writer. 991// 992// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 993// on X86 for example). 994// 995class AsmWriter { 996 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 997 // class. Generated AsmWriter classes are always prefixed with the target 998 // name. 999 string AsmWriterClassName = "InstPrinter"; 1000 1001 // Variant - AsmWriters can be of multiple different variants. Variants are 1002 // used to support targets that need to emit assembly code in ways that are 1003 // mostly the same for different targets, but have minor differences in 1004 // syntax. If the asmstring contains {|} characters in them, this integer 1005 // will specify which alternative to use. For example "{x|y|z}" with Variant 1006 // == 1, will expand to "y". 1007 int Variant = 0; 1008 1009 // OperandSpacing - Space between operand columns. 1010 int OperandSpacing = -1; 1011} 1012def DefaultAsmWriter : AsmWriter; 1013 1014 1015//===----------------------------------------------------------------------===// 1016// Target - This class contains the "global" target information 1017// 1018class Target { 1019 // InstructionSet - Instruction set description for this target. 1020 InstrInfo InstructionSet; 1021 1022 // AssemblyParsers - The AsmParser instances available for this target. 1023 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 1024 1025 /// AssemblyParserVariants - The AsmParserVariant instances available for 1026 /// this target. 1027 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 1028 1029 // AssemblyWriters - The AsmWriter instances available for this target. 1030 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 1031} 1032 1033//===----------------------------------------------------------------------===// 1034// SubtargetFeature - A characteristic of the chip set. 1035// 1036class SubtargetFeature<string n, string a, string v, string d, 1037 list<SubtargetFeature> i = []> { 1038 // Name - Feature name. Used by command line (-mattr=) to determine the 1039 // appropriate target chip. 1040 // 1041 string Name = n; 1042 1043 // Attribute - Attribute to be set by feature. 1044 // 1045 string Attribute = a; 1046 1047 // Value - Value the attribute to be set to by feature. 1048 // 1049 string Value = v; 1050 1051 // Desc - Feature description. Used by command line (-mattr=) to display help 1052 // information. 1053 // 1054 string Desc = d; 1055 1056 // Implies - Features that this feature implies are present. If one of those 1057 // features isn't set, then this one shouldn't be set either. 1058 // 1059 list<SubtargetFeature> Implies = i; 1060} 1061 1062/// Specifies a Subtarget feature that this instruction is deprecated on. 1063class Deprecated<SubtargetFeature dep> { 1064 SubtargetFeature DeprecatedFeatureMask = dep; 1065} 1066 1067/// A custom predicate used to determine if an instruction is 1068/// deprecated or not. 1069class ComplexDeprecationPredicate<string dep> { 1070 string ComplexDeprecationPredicate = dep; 1071} 1072 1073//===----------------------------------------------------------------------===// 1074// Processor chip sets - These values represent each of the chip sets supported 1075// by the scheduler. Each Processor definition requires corresponding 1076// instruction itineraries. 1077// 1078class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 1079 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1080 // appropriate target chip. 1081 // 1082 string Name = n; 1083 1084 // SchedModel - The machine model for scheduling and instruction cost. 1085 // 1086 SchedMachineModel SchedModel = NoSchedModel; 1087 1088 // ProcItin - The scheduling information for the target processor. 1089 // 1090 ProcessorItineraries ProcItin = pi; 1091 1092 // Features - list of 1093 list<SubtargetFeature> Features = f; 1094} 1095 1096// ProcessorModel allows subtargets to specify the more general 1097// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1098// gradually move to this newer form. 1099// 1100// Although this class always passes NoItineraries to the Processor 1101// class, the SchedMachineModel may still define valid Itineraries. 1102class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> 1103 : Processor<n, NoItineraries, f> { 1104 let SchedModel = m; 1105} 1106 1107//===----------------------------------------------------------------------===// 1108// InstrMapping - This class is used to create mapping tables to relate 1109// instructions with each other based on the values specified in RowFields, 1110// ColFields, KeyCol and ValueCols. 1111// 1112class InstrMapping { 1113 // FilterClass - Used to limit search space only to the instructions that 1114 // define the relationship modeled by this InstrMapping record. 1115 string FilterClass; 1116 1117 // RowFields - List of fields/attributes that should be same for all the 1118 // instructions in a row of the relation table. Think of this as a set of 1119 // properties shared by all the instructions related by this relationship 1120 // model and is used to categorize instructions into subgroups. For instance, 1121 // if we want to define a relation that maps 'Add' instruction to its 1122 // predicated forms, we can define RowFields like this: 1123 // 1124 // let RowFields = BaseOp 1125 // All add instruction predicated/non-predicated will have to set their BaseOp 1126 // to the same value. 1127 // 1128 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1129 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1130 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1131 list<string> RowFields = []; 1132 1133 // List of fields/attributes that are same for all the instructions 1134 // in a column of the relation table. 1135 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1136 // based on the 'predSense' values. All the instruction in a specific 1137 // column have the same value and it is fixed for the column according 1138 // to the values set in 'ValueCols'. 1139 list<string> ColFields = []; 1140 1141 // Values for the fields/attributes listed in 'ColFields'. 1142 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1143 // that models this relation) should be non-predicated. 1144 // In the example above, 'Add' is the key instruction. 1145 list<string> KeyCol = []; 1146 1147 // List of values for the fields/attributes listed in 'ColFields', one for 1148 // each column in the relation table. 1149 // 1150 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1151 // table. First column requires all the instructions to have predSense 1152 // set to 'true' and second column requires it to be 'false'. 1153 list<list<string> > ValueCols = []; 1154} 1155 1156//===----------------------------------------------------------------------===// 1157// Pull in the common support for calling conventions. 1158// 1159include "llvm/Target/TargetCallingConv.td" 1160 1161//===----------------------------------------------------------------------===// 1162// Pull in the common support for DAG isel generation. 1163// 1164include "llvm/Target/TargetSelectionDAG.td" 1165