Target.td revision 4fda9670f0a9cd448d1905ab669421316b8864c5
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex { 26 string Namespace = ""; 27} 28 29// Register - You should define one instance of this class for each register 30// in the target machine. String n will become the "name" of the register. 31class Register<string n> { 32 string Namespace = ""; 33 string AsmName = n; 34 35 // SpillSize - If this value is set to a non-zero value, it is the size in 36 // bits of the spill slot required to hold this register. If this value is 37 // set to zero, the information is inferred from any register classes the 38 // register belongs to. 39 int SpillSize = 0; 40 41 // SpillAlignment - This value is used to specify the alignment required for 42 // spilling the register. Like SpillSize, this should only be explicitly 43 // specified if the register is not in a register class. 44 int SpillAlignment = 0; 45 46 // Aliases - A list of registers that this register overlaps with. A read or 47 // modification of this register can potentially read or modify the aliased 48 // registers. 49 list<Register> Aliases = []; 50 51 // SubRegs - A list of registers that are parts of this register. Note these 52 // are "immediate" sub-registers and the registers within the list do not 53 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 54 // not [AX, AH, AL]. 55 list<Register> SubRegs = []; 56 57 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 58 // These values can be determined by locating the <target>.h file in the 59 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 60 // order of these names correspond to the enumeration used by gcc. A value of 61 // -1 indicates that the gcc number is undefined and -2 that register number 62 // is invalid for this mode/flavour. 63 list<int> DwarfNumbers = []; 64} 65 66// RegisterWithSubRegs - This can be used to define instances of Register which 67// need to specify sub-registers. 68// List "subregs" specifies which registers are sub-registers to this one. This 69// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 70// This allows the code generator to be careful not to put two values with 71// overlapping live ranges into registers which alias. 72class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 73 let SubRegs = subregs; 74} 75 76// SubRegSet - This can be used to define a specific mapping of registers to 77// indices, for use as named subregs of a particular physical register. Each 78// register in 'subregs' becomes an addressable subregister at index 'n' of the 79// corresponding register in 'regs'. 80class SubRegSet<SubRegIndex n, list<Register> regs, list<Register> subregs> { 81 SubRegIndex Index = n; 82 83 list<Register> From = regs; 84 list<Register> To = subregs; 85} 86 87// RegisterClass - Now that all of the registers are defined, and aliases 88// between registers are defined, specify which registers belong to which 89// register classes. This also defines the default allocation order of 90// registers by register allocators. 91// 92class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 93 list<Register> regList> { 94 string Namespace = namespace; 95 96 // RegType - Specify the list ValueType of the registers in this register 97 // class. Note that all registers in a register class must have the same 98 // ValueTypes. This is a list because some targets permit storing different 99 // types in same register, for example vector values with 128-bit total size, 100 // but different count/size of items, like SSE on x86. 101 // 102 list<ValueType> RegTypes = regTypes; 103 104 // Size - Specify the spill size in bits of the registers. A default value of 105 // zero lets tablgen pick an appropriate size. 106 int Size = 0; 107 108 // Alignment - Specify the alignment required of the registers when they are 109 // stored or loaded to memory. 110 // 111 int Alignment = alignment; 112 113 // CopyCost - This value is used to specify the cost of copying a value 114 // between two registers in this register class. The default value is one 115 // meaning it takes a single instruction to perform the copying. A negative 116 // value means copying is extremely expensive or impossible. 117 int CopyCost = 1; 118 119 // MemberList - Specify which registers are in this class. If the 120 // allocation_order_* method are not specified, this also defines the order of 121 // allocation used by the register allocator. 122 // 123 list<Register> MemberList = regList; 124 125 // SubRegClasses - Specify the register class of subregisters as a list of 126 // dags: (RegClass SubRegIndex, SubRegindex, ...) 127 list<dag> SubRegClasses = []; 128 129 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 130 // code into a generated register class. The normal usage of this is to 131 // overload virtual methods. 132 code MethodProtos = [{}]; 133 code MethodBodies = [{}]; 134} 135 136 137//===----------------------------------------------------------------------===// 138// DwarfRegNum - This class provides a mapping of the llvm register enumeration 139// to the register numbering used by gcc and gdb. These values are used by a 140// debug information writer to describe where values may be located during 141// execution. 142class DwarfRegNum<list<int> Numbers> { 143 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 144 // These values can be determined by locating the <target>.h file in the 145 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 146 // order of these names correspond to the enumeration used by gcc. A value of 147 // -1 indicates that the gcc number is undefined and -2 that register number is 148 // invalid for this mode/flavour. 149 list<int> DwarfNumbers = Numbers; 150} 151 152//===----------------------------------------------------------------------===// 153// Pull in the common support for scheduling 154// 155include "llvm/Target/TargetSchedule.td" 156 157class Predicate; // Forward def 158 159//===----------------------------------------------------------------------===// 160// Instruction set description - These classes correspond to the C++ classes in 161// the Target/TargetInstrInfo.h file. 162// 163class Instruction { 164 string Namespace = ""; 165 166 dag OutOperandList; // An dag containing the MI def operand list. 167 dag InOperandList; // An dag containing the MI use operand list. 168 string AsmString = ""; // The .s format to print the instruction with. 169 170 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 171 // otherwise, uninitialized. 172 list<dag> Pattern; 173 174 // The follow state will eventually be inferred automatically from the 175 // instruction pattern. 176 177 list<Register> Uses = []; // Default to using no non-operand registers 178 list<Register> Defs = []; // Default to modifying no non-operand registers 179 180 // Predicates - List of predicates which will be turned into isel matching 181 // code. 182 list<Predicate> Predicates = []; 183 184 // Code size. 185 int CodeSize = 0; 186 187 // Added complexity passed onto matching pattern. 188 int AddedComplexity = 0; 189 190 // These bits capture information about the high-level semantics of the 191 // instruction. 192 bit isReturn = 0; // Is this instruction a return instruction? 193 bit isBranch = 0; // Is this instruction a branch instruction? 194 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 195 bit isBarrier = 0; // Can control flow fall through this instruction? 196 bit isCall = 0; // Is this instruction a call instruction? 197 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 198 bit mayLoad = 0; // Is it possible for this inst to read memory? 199 bit mayStore = 0; // Is it possible for this inst to write memory? 200 bit isTwoAddress = 0; // Is this a two address instruction? 201 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 202 bit isCommutable = 0; // Is this 3 operand instruction commutable? 203 bit isTerminator = 0; // Is this part of the terminator for a basic block? 204 bit isReMaterializable = 0; // Is this instruction re-materializable? 205 bit isPredicable = 0; // Is this instruction predicable? 206 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 207 bit usesCustomInserter = 0; // Pseudo instr needing special help. 208 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 209 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 210 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 211 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 212 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 213 214 // Side effect flags - When set, the flags have these meanings: 215 // 216 // hasSideEffects - The instruction has side effects that are not 217 // captured by any operands of the instruction or other flags. 218 // 219 // neverHasSideEffects - Set on an instruction with no pattern if it has no 220 // side effects. 221 bit hasSideEffects = 0; 222 bit neverHasSideEffects = 0; 223 224 // Is this instruction a "real" instruction (with a distinct machine 225 // encoding), or is it a pseudo instruction used for codegen modeling 226 // purposes. 227 bit isCodeGenOnly = 0; 228 229 // Is this instruction a pseudo instruction for use by the assembler parser. 230 bit isAsmParserOnly = 0; 231 232 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 233 234 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 235 236 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 237 /// be encoded into the output machineinstr. 238 string DisableEncoding = ""; 239 240 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 241 bits<32> TSFlags = 0; 242} 243 244/// Predicates - These are extra conditionals which are turned into instruction 245/// selector matching code. Currently each predicate is just a string. 246class Predicate<string cond> { 247 string CondString = cond; 248} 249 250/// NoHonorSignDependentRounding - This predicate is true if support for 251/// sign-dependent-rounding is not enabled. 252def NoHonorSignDependentRounding 253 : Predicate<"!HonorSignDependentRoundingFPMath()">; 254 255class Requires<list<Predicate> preds> { 256 list<Predicate> Predicates = preds; 257} 258 259/// ops definition - This is just a simple marker used to identify the operands 260/// list for an instruction. outs and ins are identical both syntatically and 261/// semantically, they are used to define def operands and use operands to 262/// improve readibility. This should be used like this: 263/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 264def ops; 265def outs; 266def ins; 267 268/// variable_ops definition - Mark this instruction as taking a variable number 269/// of operands. 270def variable_ops; 271 272 273/// PointerLikeRegClass - Values that are designed to have pointer width are 274/// derived from this. TableGen treats the register class as having a symbolic 275/// type that it doesn't know, and resolves the actual regclass to use by using 276/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 277class PointerLikeRegClass<int Kind> { 278 int RegClassKind = Kind; 279} 280 281 282/// ptr_rc definition - Mark this operand as being a pointer value whose 283/// register class is resolved dynamically via a callback to TargetInstrInfo. 284/// FIXME: We should probably change this to a class which contain a list of 285/// flags. But currently we have but one flag. 286def ptr_rc : PointerLikeRegClass<0>; 287 288/// unknown definition - Mark this operand as being of unknown type, causing 289/// it to be resolved by inference in the context it is used. 290def unknown; 291 292/// AsmOperandClass - Representation for the kinds of operands which the target 293/// specific parser can create and the assembly matcher may need to distinguish. 294/// 295/// Operand classes are used to define the order in which instructions are 296/// matched, to ensure that the instruction which gets matched for any 297/// particular list of operands is deterministic. 298/// 299/// The target specific parser must be able to classify a parsed operand into a 300/// unique class which does not partially overlap with any other classes. It can 301/// match a subset of some other class, in which case the super class field 302/// should be defined. 303class AsmOperandClass { 304 /// The name to use for this class, which should be usable as an enum value. 305 string Name = ?; 306 307 /// The super classes of this operand. 308 list<AsmOperandClass> SuperClasses = []; 309 310 /// The name of the method on the target specific operand to call to test 311 /// whether the operand is an instance of this class. If not set, this will 312 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 313 /// signature should be: 314 /// bool isFoo() const; 315 string PredicateMethod = ?; 316 317 /// The name of the method on the target specific operand to call to add the 318 /// target specific operand to an MCInst. If not set, this will default to 319 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 320 /// signature should be: 321 /// void addFooOperands(MCInst &Inst, unsigned N) const; 322 string RenderMethod = ?; 323} 324 325def ImmAsmOperand : AsmOperandClass { 326 let Name = "Imm"; 327} 328 329/// Operand Types - These provide the built-in operand types that may be used 330/// by a target. Targets can optionally provide their own operand types as 331/// needed, though this should not be needed for RISC targets. 332class Operand<ValueType ty> { 333 ValueType Type = ty; 334 string PrintMethod = "printOperand"; 335 string AsmOperandLowerMethod = ?; 336 dag MIOperandInfo = (ops); 337 338 // ParserMatchClass - The "match class" that operands of this type fit 339 // in. Match classes are used to define the order in which instructions are 340 // match, to ensure that which instructions gets matched is deterministic. 341 // 342 // The target specific parser must be able to classify an parsed operand into 343 // a unique class, which does not partially overlap with any other classes. It 344 // can match a subset of some other class, in which case the AsmOperandClass 345 // should declare the other operand as one of its super classes. 346 AsmOperandClass ParserMatchClass = ImmAsmOperand; 347} 348 349def i1imm : Operand<i1>; 350def i8imm : Operand<i8>; 351def i16imm : Operand<i16>; 352def i32imm : Operand<i32>; 353def i64imm : Operand<i64>; 354 355def f32imm : Operand<f32>; 356def f64imm : Operand<f64>; 357 358/// zero_reg definition - Special node to stand for the zero register. 359/// 360def zero_reg; 361 362/// PredicateOperand - This can be used to define a predicate operand for an 363/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 364/// AlwaysVal specifies the value of this predicate when set to "always 365/// execute". 366class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 367 : Operand<ty> { 368 let MIOperandInfo = OpTypes; 369 dag DefaultOps = AlwaysVal; 370} 371 372/// OptionalDefOperand - This is used to define a optional definition operand 373/// for an instruction. DefaultOps is the register the operand represents if 374/// none is supplied, e.g. zero_reg. 375class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 376 : Operand<ty> { 377 let MIOperandInfo = OpTypes; 378 dag DefaultOps = defaultops; 379} 380 381 382// InstrInfo - This class should only be instantiated once to provide parameters 383// which are global to the target machine. 384// 385class InstrInfo { 386 // Target can specify its instructions in either big or little-endian formats. 387 // For instance, while both Sparc and PowerPC are big-endian platforms, the 388 // Sparc manual specifies its instructions in the format [31..0] (big), while 389 // PowerPC specifies them using the format [0..31] (little). 390 bit isLittleEndianEncoding = 0; 391} 392 393// Standard Pseudo Instructions. 394let isCodeGenOnly = 1 in { 395def PHI : Instruction { 396 let OutOperandList = (outs); 397 let InOperandList = (ins variable_ops); 398 let AsmString = "PHINODE"; 399 let Namespace = "TargetOpcode"; 400} 401def INLINEASM : Instruction { 402 let OutOperandList = (outs); 403 let InOperandList = (ins variable_ops); 404 let AsmString = ""; 405 let Namespace = "TargetOpcode"; 406} 407def DBG_LABEL : Instruction { 408 let OutOperandList = (outs); 409 let InOperandList = (ins i32imm:$id); 410 let AsmString = ""; 411 let Namespace = "TargetOpcode"; 412 let hasCtrlDep = 1; 413 let isNotDuplicable = 1; 414} 415def EH_LABEL : Instruction { 416 let OutOperandList = (outs); 417 let InOperandList = (ins i32imm:$id); 418 let AsmString = ""; 419 let Namespace = "TargetOpcode"; 420 let hasCtrlDep = 1; 421 let isNotDuplicable = 1; 422} 423def GC_LABEL : Instruction { 424 let OutOperandList = (outs); 425 let InOperandList = (ins i32imm:$id); 426 let AsmString = ""; 427 let Namespace = "TargetOpcode"; 428 let hasCtrlDep = 1; 429 let isNotDuplicable = 1; 430} 431def KILL : Instruction { 432 let OutOperandList = (outs); 433 let InOperandList = (ins variable_ops); 434 let AsmString = ""; 435 let Namespace = "TargetOpcode"; 436 let neverHasSideEffects = 1; 437} 438def EXTRACT_SUBREG : Instruction { 439 let OutOperandList = (outs unknown:$dst); 440 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 441 let AsmString = ""; 442 let Namespace = "TargetOpcode"; 443 let neverHasSideEffects = 1; 444} 445def INSERT_SUBREG : Instruction { 446 let OutOperandList = (outs unknown:$dst); 447 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 448 let AsmString = ""; 449 let Namespace = "TargetOpcode"; 450 let neverHasSideEffects = 1; 451 let Constraints = "$supersrc = $dst"; 452} 453def IMPLICIT_DEF : Instruction { 454 let OutOperandList = (outs unknown:$dst); 455 let InOperandList = (ins); 456 let AsmString = ""; 457 let Namespace = "TargetOpcode"; 458 let neverHasSideEffects = 1; 459 let isReMaterializable = 1; 460 let isAsCheapAsAMove = 1; 461} 462def SUBREG_TO_REG : Instruction { 463 let OutOperandList = (outs unknown:$dst); 464 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 465 let AsmString = ""; 466 let Namespace = "TargetOpcode"; 467 let neverHasSideEffects = 1; 468} 469def COPY_TO_REGCLASS : Instruction { 470 let OutOperandList = (outs unknown:$dst); 471 let InOperandList = (ins unknown:$src, i32imm:$regclass); 472 let AsmString = ""; 473 let Namespace = "TargetOpcode"; 474 let neverHasSideEffects = 1; 475 let isAsCheapAsAMove = 1; 476} 477def DBG_VALUE : Instruction { 478 let OutOperandList = (outs); 479 let InOperandList = (ins variable_ops); 480 let AsmString = "DBG_VALUE"; 481 let Namespace = "TargetOpcode"; 482 let isAsCheapAsAMove = 1; 483} 484 485def REG_SEQUENCE : Instruction { 486 let OutOperandList = (outs unknown:$dst); 487 let InOperandList = (ins variable_ops); 488 let AsmString = ""; 489 let Namespace = "TargetOpcode"; 490 let neverHasSideEffects = 1; 491 let isAsCheapAsAMove = 1; 492} 493} 494 495//===----------------------------------------------------------------------===// 496// AsmParser - This class can be implemented by targets that wish to implement 497// .s file parsing. 498// 499// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 500// syntax on X86 for example). 501// 502class AsmParser { 503 // AsmParserClassName - This specifies the suffix to use for the asmparser 504 // class. Generated AsmParser classes are always prefixed with the target 505 // name. 506 string AsmParserClassName = "AsmParser"; 507 508 // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the 509 // AsmParser class to call on every matched instruction. This can be used to 510 // perform target specific instruction post-processing. 511 string AsmParserInstCleanup = ""; 512 513 // MatchInstructionName - The name of the instruction matching function to 514 // generate. 515 string MatchInstructionName = "MatchInstruction"; 516 517 // Variant - AsmParsers can be of multiple different variants. Variants are 518 // used to support targets that need to parser multiple formats for the 519 // assembly language. 520 int Variant = 0; 521 522 // CommentDelimiter - If given, the delimiter string used to recognize 523 // comments which are hard coded in the .td assembler strings for individual 524 // instructions. 525 string CommentDelimiter = ""; 526 527 // RegisterPrefix - If given, the token prefix which indicates a register 528 // token. This is used by the matcher to automatically recognize hard coded 529 // register tokens as constrained registers, instead of tokens, for the 530 // purposes of matching. 531 string RegisterPrefix = ""; 532} 533def DefaultAsmParser : AsmParser; 534 535 536//===----------------------------------------------------------------------===// 537// AsmWriter - This class can be implemented by targets that need to customize 538// the format of the .s file writer. 539// 540// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 541// on X86 for example). 542// 543class AsmWriter { 544 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 545 // class. Generated AsmWriter classes are always prefixed with the target 546 // name. 547 string AsmWriterClassName = "AsmPrinter"; 548 549 // InstFormatName - AsmWriters can specify the name of the format string to 550 // print instructions with. 551 string InstFormatName = "AsmString"; 552 553 // Variant - AsmWriters can be of multiple different variants. Variants are 554 // used to support targets that need to emit assembly code in ways that are 555 // mostly the same for different targets, but have minor differences in 556 // syntax. If the asmstring contains {|} characters in them, this integer 557 // will specify which alternative to use. For example "{x|y|z}" with Variant 558 // == 1, will expand to "y". 559 int Variant = 0; 560 561 562 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 563 // layout, the asmwriter can actually generate output in this columns (in 564 // verbose-asm mode). These two values indicate the width of the first column 565 // (the "opcode" area) and the width to reserve for subsequent operands. When 566 // verbose asm mode is enabled, operands will be indented to respect this. 567 int FirstOperandColumn = -1; 568 569 // OperandSpacing - Space between operand columns. 570 int OperandSpacing = -1; 571} 572def DefaultAsmWriter : AsmWriter; 573 574 575//===----------------------------------------------------------------------===// 576// Target - This class contains the "global" target information 577// 578class Target { 579 // InstructionSet - Instruction set description for this target. 580 InstrInfo InstructionSet; 581 582 // AssemblyParsers - The AsmParser instances available for this target. 583 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 584 585 // AssemblyWriters - The AsmWriter instances available for this target. 586 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 587} 588 589//===----------------------------------------------------------------------===// 590// SubtargetFeature - A characteristic of the chip set. 591// 592class SubtargetFeature<string n, string a, string v, string d, 593 list<SubtargetFeature> i = []> { 594 // Name - Feature name. Used by command line (-mattr=) to determine the 595 // appropriate target chip. 596 // 597 string Name = n; 598 599 // Attribute - Attribute to be set by feature. 600 // 601 string Attribute = a; 602 603 // Value - Value the attribute to be set to by feature. 604 // 605 string Value = v; 606 607 // Desc - Feature description. Used by command line (-mattr=) to display help 608 // information. 609 // 610 string Desc = d; 611 612 // Implies - Features that this feature implies are present. If one of those 613 // features isn't set, then this one shouldn't be set either. 614 // 615 list<SubtargetFeature> Implies = i; 616} 617 618//===----------------------------------------------------------------------===// 619// Processor chip sets - These values represent each of the chip sets supported 620// by the scheduler. Each Processor definition requires corresponding 621// instruction itineraries. 622// 623class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 624 // Name - Chip set name. Used by command line (-mcpu=) to determine the 625 // appropriate target chip. 626 // 627 string Name = n; 628 629 // ProcItin - The scheduling information for the target processor. 630 // 631 ProcessorItineraries ProcItin = pi; 632 633 // Features - list of 634 list<SubtargetFeature> Features = f; 635} 636 637//===----------------------------------------------------------------------===// 638// Pull in the common support for calling conventions. 639// 640include "llvm/Target/TargetCallingConv.td" 641 642//===----------------------------------------------------------------------===// 643// Pull in the common support for DAG isel generation. 644// 645include "llvm/Target/TargetSelectionDAG.td" 646