Target.td revision 69ba413057fe5d73d95e7b51ddfe16a8b0def23c
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex { 26 string Namespace = ""; 27} 28 29// Register - You should define one instance of this class for each register 30// in the target machine. String n will become the "name" of the register. 31class Register<string n> { 32 string Namespace = ""; 33 string AsmName = n; 34 35 // Aliases - A list of registers that this register overlaps with. A read or 36 // modification of this register can potentially read or modify the aliased 37 // registers. 38 list<Register> Aliases = []; 39 40 // SubRegs - A list of registers that are parts of this register. Note these 41 // are "immediate" sub-registers and the registers within the list do not 42 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 43 // not [AX, AH, AL]. 44 list<Register> SubRegs = []; 45 46 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 47 // to address it. Sub-sub-register indices are automatically inherited from 48 // SubRegs. 49 list<SubRegIndex> SubRegIndices = []; 50 51 // CompositeIndices - Specify subreg indices that don't correspond directly to 52 // a register in SubRegs and are not inherited. The following formats are 53 // supported: 54 // 55 // (a) Identity - Reg:a == Reg 56 // (a b) Alias - Reg:a == Reg:b 57 // (a b,c) Composite - Reg:a == (Reg:b):c 58 // 59 // This can be used to disambiguate a sub-sub-register that exists in more 60 // than one subregister and other weird stuff. 61 list<dag> CompositeIndices = []; 62 63 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 64 // These values can be determined by locating the <target>.h file in the 65 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 66 // order of these names correspond to the enumeration used by gcc. A value of 67 // -1 indicates that the gcc number is undefined and -2 that register number 68 // is invalid for this mode/flavour. 69 list<int> DwarfNumbers = []; 70 71 // CostPerUse - Additional cost of instructions using this register compared 72 // to other registers in its class. The register allocator will try to 73 // minimize the number of instructions using a register with a CostPerUse. 74 // This is used by the x86-64 and ARM Thumb targets where some registers 75 // require larger instruction encodings. 76 int CostPerUse = 0; 77} 78 79// RegisterWithSubRegs - This can be used to define instances of Register which 80// need to specify sub-registers. 81// List "subregs" specifies which registers are sub-registers to this one. This 82// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 83// This allows the code generator to be careful not to put two values with 84// overlapping live ranges into registers which alias. 85class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 86 let SubRegs = subregs; 87} 88 89// RegisterClass - Now that all of the registers are defined, and aliases 90// between registers are defined, specify which registers belong to which 91// register classes. This also defines the default allocation order of 92// registers by register allocators. 93// 94class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 95 list<Register> regList> { 96 string Namespace = namespace; 97 98 // RegType - Specify the list ValueType of the registers in this register 99 // class. Note that all registers in a register class must have the same 100 // ValueTypes. This is a list because some targets permit storing different 101 // types in same register, for example vector values with 128-bit total size, 102 // but different count/size of items, like SSE on x86. 103 // 104 list<ValueType> RegTypes = regTypes; 105 106 // Size - Specify the spill size in bits of the registers. A default value of 107 // zero lets tablgen pick an appropriate size. 108 int Size = 0; 109 110 // Alignment - Specify the alignment required of the registers when they are 111 // stored or loaded to memory. 112 // 113 int Alignment = alignment; 114 115 // CopyCost - This value is used to specify the cost of copying a value 116 // between two registers in this register class. The default value is one 117 // meaning it takes a single instruction to perform the copying. A negative 118 // value means copying is extremely expensive or impossible. 119 int CopyCost = 1; 120 121 // MemberList - Specify which registers are in this class. If the 122 // allocation_order_* method are not specified, this also defines the order of 123 // allocation used by the register allocator. 124 // 125 list<Register> MemberList = regList; 126 127 // SubRegClasses - Specify the register class of subregisters as a list of 128 // dags: (RegClass SubRegIndex, SubRegindex, ...) 129 list<dag> SubRegClasses = []; 130 131 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 132 // code into a generated register class. The normal usage of this is to 133 // overload virtual methods. 134 code MethodProtos = [{}]; 135 code MethodBodies = [{}]; 136} 137 138 139//===----------------------------------------------------------------------===// 140// DwarfRegNum - This class provides a mapping of the llvm register enumeration 141// to the register numbering used by gcc and gdb. These values are used by a 142// debug information writer to describe where values may be located during 143// execution. 144class DwarfRegNum<list<int> Numbers> { 145 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 146 // These values can be determined by locating the <target>.h file in the 147 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 148 // order of these names correspond to the enumeration used by gcc. A value of 149 // -1 indicates that the gcc number is undefined and -2 that register number 150 // is invalid for this mode/flavour. 151 list<int> DwarfNumbers = Numbers; 152} 153 154//===----------------------------------------------------------------------===// 155// Pull in the common support for scheduling 156// 157include "llvm/Target/TargetSchedule.td" 158 159class Predicate; // Forward def 160 161//===----------------------------------------------------------------------===// 162// Instruction set description - These classes correspond to the C++ classes in 163// the Target/TargetInstrInfo.h file. 164// 165class Instruction { 166 string Namespace = ""; 167 168 dag OutOperandList; // An dag containing the MI def operand list. 169 dag InOperandList; // An dag containing the MI use operand list. 170 string AsmString = ""; // The .s format to print the instruction with. 171 172 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 173 // otherwise, uninitialized. 174 list<dag> Pattern; 175 176 // The follow state will eventually be inferred automatically from the 177 // instruction pattern. 178 179 list<Register> Uses = []; // Default to using no non-operand registers 180 list<Register> Defs = []; // Default to modifying no non-operand registers 181 182 // Predicates - List of predicates which will be turned into isel matching 183 // code. 184 list<Predicate> Predicates = []; 185 186 // Code size. 187 int CodeSize = 0; 188 189 // Added complexity passed onto matching pattern. 190 int AddedComplexity = 0; 191 192 // These bits capture information about the high-level semantics of the 193 // instruction. 194 bit isReturn = 0; // Is this instruction a return instruction? 195 bit isBranch = 0; // Is this instruction a branch instruction? 196 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 197 bit isCompare = 0; // Is this instruction a comparison instruction? 198 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 199 bit isBitcast = 0; // Is this instruction a bitcast instruction? 200 bit isBarrier = 0; // Can control flow fall through this instruction? 201 bit isCall = 0; // Is this instruction a call instruction? 202 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 203 bit mayLoad = 0; // Is it possible for this inst to read memory? 204 bit mayStore = 0; // Is it possible for this inst to write memory? 205 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 206 bit isCommutable = 0; // Is this 3 operand instruction commutable? 207 bit isTerminator = 0; // Is this part of the terminator for a basic block? 208 bit isReMaterializable = 0; // Is this instruction re-materializable? 209 bit isPredicable = 0; // Is this instruction predicable? 210 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 211 bit usesCustomInserter = 0; // Pseudo instr needing special help. 212 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 213 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 214 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 215 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 216 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 217 218 // Side effect flags - When set, the flags have these meanings: 219 // 220 // hasSideEffects - The instruction has side effects that are not 221 // captured by any operands of the instruction or other flags. 222 // 223 // neverHasSideEffects - Set on an instruction with no pattern if it has no 224 // side effects. 225 bit hasSideEffects = 0; 226 bit neverHasSideEffects = 0; 227 228 // Is this instruction a "real" instruction (with a distinct machine 229 // encoding), or is it a pseudo instruction used for codegen modeling 230 // purposes. 231 bit isCodeGenOnly = 0; 232 233 // Is this instruction a pseudo instruction for use by the assembler parser. 234 bit isAsmParserOnly = 0; 235 236 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 237 238 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 239 240 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 241 /// be encoded into the output machineinstr. 242 string DisableEncoding = ""; 243 244 string PostEncoderMethod = ""; 245 string DecoderMethod = ""; 246 247 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 248 bits<64> TSFlags = 0; 249 250 ///@name Assembler Parser Support 251 ///@{ 252 253 string AsmMatchConverter = ""; 254 255 ///@} 256} 257 258/// Predicates - These are extra conditionals which are turned into instruction 259/// selector matching code. Currently each predicate is just a string. 260class Predicate<string cond> { 261 string CondString = cond; 262 263 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 264 /// matcher, this is true. Targets should set this by inheriting their 265 /// feature from the AssemblerPredicate class in addition to Predicate. 266 bit AssemblerMatcherPredicate = 0; 267} 268 269/// NoHonorSignDependentRounding - This predicate is true if support for 270/// sign-dependent-rounding is not enabled. 271def NoHonorSignDependentRounding 272 : Predicate<"!HonorSignDependentRoundingFPMath()">; 273 274class Requires<list<Predicate> preds> { 275 list<Predicate> Predicates = preds; 276} 277 278/// ops definition - This is just a simple marker used to identify the operand 279/// list for an instruction. outs and ins are identical both syntactically and 280/// semanticallyr; they are used to define def operands and use operands to 281/// improve readibility. This should be used like this: 282/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 283def ops; 284def outs; 285def ins; 286 287/// variable_ops definition - Mark this instruction as taking a variable number 288/// of operands. 289def variable_ops; 290 291 292/// PointerLikeRegClass - Values that are designed to have pointer width are 293/// derived from this. TableGen treats the register class as having a symbolic 294/// type that it doesn't know, and resolves the actual regclass to use by using 295/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 296class PointerLikeRegClass<int Kind> { 297 int RegClassKind = Kind; 298} 299 300 301/// ptr_rc definition - Mark this operand as being a pointer value whose 302/// register class is resolved dynamically via a callback to TargetInstrInfo. 303/// FIXME: We should probably change this to a class which contain a list of 304/// flags. But currently we have but one flag. 305def ptr_rc : PointerLikeRegClass<0>; 306 307/// unknown definition - Mark this operand as being of unknown type, causing 308/// it to be resolved by inference in the context it is used. 309def unknown; 310 311/// AsmOperandClass - Representation for the kinds of operands which the target 312/// specific parser can create and the assembly matcher may need to distinguish. 313/// 314/// Operand classes are used to define the order in which instructions are 315/// matched, to ensure that the instruction which gets matched for any 316/// particular list of operands is deterministic. 317/// 318/// The target specific parser must be able to classify a parsed operand into a 319/// unique class which does not partially overlap with any other classes. It can 320/// match a subset of some other class, in which case the super class field 321/// should be defined. 322class AsmOperandClass { 323 /// The name to use for this class, which should be usable as an enum value. 324 string Name = ?; 325 326 /// The super classes of this operand. 327 list<AsmOperandClass> SuperClasses = []; 328 329 /// The name of the method on the target specific operand to call to test 330 /// whether the operand is an instance of this class. If not set, this will 331 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 332 /// signature should be: 333 /// bool isFoo() const; 334 string PredicateMethod = ?; 335 336 /// The name of the method on the target specific operand to call to add the 337 /// target specific operand to an MCInst. If not set, this will default to 338 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 339 /// signature should be: 340 /// void addFooOperands(MCInst &Inst, unsigned N) const; 341 string RenderMethod = ?; 342 343 /// The name of the method on the target specific operand to call to custom 344 /// handle the operand parsing. This is useful when the operands do not relate 345 /// to immediates or registers and are very instruction specific (as flags to 346 /// set in a processor register, coprocessor number, ...). 347 string ParserMethod = ?; 348} 349 350def ImmAsmOperand : AsmOperandClass { 351 let Name = "Imm"; 352} 353 354/// Operand Types - These provide the built-in operand types that may be used 355/// by a target. Targets can optionally provide their own operand types as 356/// needed, though this should not be needed for RISC targets. 357class Operand<ValueType ty> { 358 ValueType Type = ty; 359 string PrintMethod = "printOperand"; 360 string EncoderMethod = ""; 361 string DecoderMethod = ""; 362 string AsmOperandLowerMethod = ?; 363 dag MIOperandInfo = (ops); 364 365 // ParserMatchClass - The "match class" that operands of this type fit 366 // in. Match classes are used to define the order in which instructions are 367 // match, to ensure that which instructions gets matched is deterministic. 368 // 369 // The target specific parser must be able to classify an parsed operand into 370 // a unique class, which does not partially overlap with any other classes. It 371 // can match a subset of some other class, in which case the AsmOperandClass 372 // should declare the other operand as one of its super classes. 373 AsmOperandClass ParserMatchClass = ImmAsmOperand; 374} 375 376def i1imm : Operand<i1>; 377def i8imm : Operand<i8>; 378def i16imm : Operand<i16>; 379def i32imm : Operand<i32>; 380def i64imm : Operand<i64>; 381 382def f32imm : Operand<f32>; 383def f64imm : Operand<f64>; 384 385/// zero_reg definition - Special node to stand for the zero register. 386/// 387def zero_reg; 388 389/// PredicateOperand - This can be used to define a predicate operand for an 390/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 391/// AlwaysVal specifies the value of this predicate when set to "always 392/// execute". 393class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 394 : Operand<ty> { 395 let MIOperandInfo = OpTypes; 396 dag DefaultOps = AlwaysVal; 397} 398 399/// OptionalDefOperand - This is used to define a optional definition operand 400/// for an instruction. DefaultOps is the register the operand represents if 401/// none is supplied, e.g. zero_reg. 402class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 403 : Operand<ty> { 404 let MIOperandInfo = OpTypes; 405 dag DefaultOps = defaultops; 406} 407 408 409// InstrInfo - This class should only be instantiated once to provide parameters 410// which are global to the target machine. 411// 412class InstrInfo { 413 // Target can specify its instructions in either big or little-endian formats. 414 // For instance, while both Sparc and PowerPC are big-endian platforms, the 415 // Sparc manual specifies its instructions in the format [31..0] (big), while 416 // PowerPC specifies them using the format [0..31] (little). 417 bit isLittleEndianEncoding = 0; 418} 419 420// Standard Pseudo Instructions. 421// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 422// Only these instructions are allowed in the TargetOpcode namespace. 423let isCodeGenOnly = 1, Namespace = "TargetOpcode" in { 424def PHI : Instruction { 425 let OutOperandList = (outs); 426 let InOperandList = (ins variable_ops); 427 let AsmString = "PHINODE"; 428} 429def INLINEASM : Instruction { 430 let OutOperandList = (outs); 431 let InOperandList = (ins variable_ops); 432 let AsmString = ""; 433 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 434} 435def PROLOG_LABEL : Instruction { 436 let OutOperandList = (outs); 437 let InOperandList = (ins i32imm:$id); 438 let AsmString = ""; 439 let hasCtrlDep = 1; 440 let isNotDuplicable = 1; 441} 442def EH_LABEL : Instruction { 443 let OutOperandList = (outs); 444 let InOperandList = (ins i32imm:$id); 445 let AsmString = ""; 446 let hasCtrlDep = 1; 447 let isNotDuplicable = 1; 448} 449def GC_LABEL : Instruction { 450 let OutOperandList = (outs); 451 let InOperandList = (ins i32imm:$id); 452 let AsmString = ""; 453 let hasCtrlDep = 1; 454 let isNotDuplicable = 1; 455} 456def KILL : Instruction { 457 let OutOperandList = (outs); 458 let InOperandList = (ins variable_ops); 459 let AsmString = ""; 460 let neverHasSideEffects = 1; 461} 462def EXTRACT_SUBREG : Instruction { 463 let OutOperandList = (outs unknown:$dst); 464 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 465 let AsmString = ""; 466 let neverHasSideEffects = 1; 467} 468def INSERT_SUBREG : Instruction { 469 let OutOperandList = (outs unknown:$dst); 470 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 471 let AsmString = ""; 472 let neverHasSideEffects = 1; 473 let Constraints = "$supersrc = $dst"; 474} 475def IMPLICIT_DEF : Instruction { 476 let OutOperandList = (outs unknown:$dst); 477 let InOperandList = (ins); 478 let AsmString = ""; 479 let neverHasSideEffects = 1; 480 let isReMaterializable = 1; 481 let isAsCheapAsAMove = 1; 482} 483def SUBREG_TO_REG : Instruction { 484 let OutOperandList = (outs unknown:$dst); 485 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 486 let AsmString = ""; 487 let neverHasSideEffects = 1; 488} 489def COPY_TO_REGCLASS : Instruction { 490 let OutOperandList = (outs unknown:$dst); 491 let InOperandList = (ins unknown:$src, i32imm:$regclass); 492 let AsmString = ""; 493 let neverHasSideEffects = 1; 494 let isAsCheapAsAMove = 1; 495} 496def DBG_VALUE : Instruction { 497 let OutOperandList = (outs); 498 let InOperandList = (ins variable_ops); 499 let AsmString = "DBG_VALUE"; 500 let neverHasSideEffects = 1; 501} 502def REG_SEQUENCE : Instruction { 503 let OutOperandList = (outs unknown:$dst); 504 let InOperandList = (ins variable_ops); 505 let AsmString = ""; 506 let neverHasSideEffects = 1; 507 let isAsCheapAsAMove = 1; 508} 509def COPY : Instruction { 510 let OutOperandList = (outs unknown:$dst); 511 let InOperandList = (ins unknown:$src); 512 let AsmString = ""; 513 let neverHasSideEffects = 1; 514 let isAsCheapAsAMove = 1; 515} 516} 517 518//===----------------------------------------------------------------------===// 519// AsmParser - This class can be implemented by targets that wish to implement 520// .s file parsing. 521// 522// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 523// syntax on X86 for example). 524// 525class AsmParser { 526 // AsmParserClassName - This specifies the suffix to use for the asmparser 527 // class. Generated AsmParser classes are always prefixed with the target 528 // name. 529 string AsmParserClassName = "AsmParser"; 530 531 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 532 // function of the AsmParser class to call on every matched instruction. 533 // This can be used to perform target specific instruction post-processing. 534 string AsmParserInstCleanup = ""; 535 536 // Variant - AsmParsers can be of multiple different variants. Variants are 537 // used to support targets that need to parser multiple formats for the 538 // assembly language. 539 int Variant = 0; 540 541 // CommentDelimiter - If given, the delimiter string used to recognize 542 // comments which are hard coded in the .td assembler strings for individual 543 // instructions. 544 string CommentDelimiter = ""; 545 546 // RegisterPrefix - If given, the token prefix which indicates a register 547 // token. This is used by the matcher to automatically recognize hard coded 548 // register tokens as constrained registers, instead of tokens, for the 549 // purposes of matching. 550 string RegisterPrefix = ""; 551} 552def DefaultAsmParser : AsmParser; 553 554/// AssemblerPredicate - This is a Predicate that can be used when the assembler 555/// matches instructions and aliases. 556class AssemblerPredicate { 557 bit AssemblerMatcherPredicate = 1; 558} 559 560 561 562/// MnemonicAlias - This class allows targets to define assembler mnemonic 563/// aliases. This should be used when all forms of one mnemonic are accepted 564/// with a different mnemonic. For example, X86 allows: 565/// sal %al, 1 -> shl %al, 1 566/// sal %ax, %cl -> shl %ax, %cl 567/// sal %eax, %cl -> shl %eax, %cl 568/// etc. Though "sal" is accepted with many forms, all of them are directly 569/// translated to a shl, so it can be handled with (in the case of X86, it 570/// actually has one for each suffix as well): 571/// def : MnemonicAlias<"sal", "shl">; 572/// 573/// Mnemonic aliases are mapped before any other translation in the match phase, 574/// and do allow Requires predicates, e.g.: 575/// 576/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 577/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 578/// 579class MnemonicAlias<string From, string To> { 580 string FromMnemonic = From; 581 string ToMnemonic = To; 582 583 // Predicates - Predicates that must be true for this remapping to happen. 584 list<Predicate> Predicates = []; 585} 586 587/// InstAlias - This defines an alternate assembly syntax that is allowed to 588/// match an instruction that has a different (more canonical) assembly 589/// representation. 590class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 591 string AsmString = Asm; // The .s format to match the instruction with. 592 dag ResultInst = Result; // The MCInst to generate. 593 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 594 595 // Predicates - Predicates that must be true for this to match. 596 list<Predicate> Predicates = []; 597} 598 599//===----------------------------------------------------------------------===// 600// AsmWriter - This class can be implemented by targets that need to customize 601// the format of the .s file writer. 602// 603// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 604// on X86 for example). 605// 606class AsmWriter { 607 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 608 // class. Generated AsmWriter classes are always prefixed with the target 609 // name. 610 string AsmWriterClassName = "AsmPrinter"; 611 612 // Variant - AsmWriters can be of multiple different variants. Variants are 613 // used to support targets that need to emit assembly code in ways that are 614 // mostly the same for different targets, but have minor differences in 615 // syntax. If the asmstring contains {|} characters in them, this integer 616 // will specify which alternative to use. For example "{x|y|z}" with Variant 617 // == 1, will expand to "y". 618 int Variant = 0; 619 620 621 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 622 // layout, the asmwriter can actually generate output in this columns (in 623 // verbose-asm mode). These two values indicate the width of the first column 624 // (the "opcode" area) and the width to reserve for subsequent operands. When 625 // verbose asm mode is enabled, operands will be indented to respect this. 626 int FirstOperandColumn = -1; 627 628 // OperandSpacing - Space between operand columns. 629 int OperandSpacing = -1; 630 631 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 632 // generation of the printInstruction() method. For MC printers, it takes 633 // an MCInstr* operand, otherwise it takes a MachineInstr*. 634 bit isMCAsmWriter = 0; 635} 636def DefaultAsmWriter : AsmWriter; 637 638 639//===----------------------------------------------------------------------===// 640// Target - This class contains the "global" target information 641// 642class Target { 643 // InstructionSet - Instruction set description for this target. 644 InstrInfo InstructionSet; 645 646 // AssemblyParsers - The AsmParser instances available for this target. 647 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 648 649 // AssemblyWriters - The AsmWriter instances available for this target. 650 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 651} 652 653//===----------------------------------------------------------------------===// 654// SubtargetFeature - A characteristic of the chip set. 655// 656class SubtargetFeature<string n, string a, string v, string d, 657 list<SubtargetFeature> i = []> { 658 // Name - Feature name. Used by command line (-mattr=) to determine the 659 // appropriate target chip. 660 // 661 string Name = n; 662 663 // Attribute - Attribute to be set by feature. 664 // 665 string Attribute = a; 666 667 // Value - Value the attribute to be set to by feature. 668 // 669 string Value = v; 670 671 // Desc - Feature description. Used by command line (-mattr=) to display help 672 // information. 673 // 674 string Desc = d; 675 676 // Implies - Features that this feature implies are present. If one of those 677 // features isn't set, then this one shouldn't be set either. 678 // 679 list<SubtargetFeature> Implies = i; 680} 681 682//===----------------------------------------------------------------------===// 683// Processor chip sets - These values represent each of the chip sets supported 684// by the scheduler. Each Processor definition requires corresponding 685// instruction itineraries. 686// 687class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 688 // Name - Chip set name. Used by command line (-mcpu=) to determine the 689 // appropriate target chip. 690 // 691 string Name = n; 692 693 // ProcItin - The scheduling information for the target processor. 694 // 695 ProcessorItineraries ProcItin = pi; 696 697 // Features - list of 698 list<SubtargetFeature> Features = f; 699} 700 701//===----------------------------------------------------------------------===// 702// Pull in the common support for calling conventions. 703// 704include "llvm/Target/TargetCallingConv.td" 705 706//===----------------------------------------------------------------------===// 707// Pull in the common support for DAG isel generation. 708// 709include "llvm/Target/TargetSelectionDAG.td" 710