Target.td revision a66512e59142f36ae653460891c058d5e78e07e3
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex { 26 string Namespace = ""; 27} 28 29// RegAltNameIndex - The alternate name set to use for register operands of 30// this register class when printing. 31class RegAltNameIndex { 32 string Namespace = ""; 33} 34def NoRegAltName : RegAltNameIndex; 35 36// Register - You should define one instance of this class for each register 37// in the target machine. String n will become the "name" of the register. 38class Register<string n, list<string> altNames = []> { 39 string Namespace = ""; 40 string AsmName = n; 41 list<string> AltNames = altNames; 42 43 // Aliases - A list of registers that this register overlaps with. A read or 44 // modification of this register can potentially read or modify the aliased 45 // registers. 46 list<Register> Aliases = []; 47 48 // SubRegs - A list of registers that are parts of this register. Note these 49 // are "immediate" sub-registers and the registers within the list do not 50 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 51 // not [AX, AH, AL]. 52 list<Register> SubRegs = []; 53 54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 55 // to address it. Sub-sub-register indices are automatically inherited from 56 // SubRegs. 57 list<SubRegIndex> SubRegIndices = []; 58 59 // RegAltNameIndices - The alternate name indices which are valid for this 60 // register. 61 list<RegAltNameIndex> RegAltNameIndices = []; 62 63 // CompositeIndices - Specify subreg indices that don't correspond directly to 64 // a register in SubRegs and are not inherited. The following formats are 65 // supported: 66 // 67 // (a) Identity - Reg:a == Reg 68 // (a b) Alias - Reg:a == Reg:b 69 // (a b,c) Composite - Reg:a == (Reg:b):c 70 // 71 // This can be used to disambiguate a sub-sub-register that exists in more 72 // than one subregister and other weird stuff. 73 list<dag> CompositeIndices = []; 74 75 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 76 // These values can be determined by locating the <target>.h file in the 77 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 78 // order of these names correspond to the enumeration used by gcc. A value of 79 // -1 indicates that the gcc number is undefined and -2 that register number 80 // is invalid for this mode/flavour. 81 list<int> DwarfNumbers = []; 82 83 // CostPerUse - Additional cost of instructions using this register compared 84 // to other registers in its class. The register allocator will try to 85 // minimize the number of instructions using a register with a CostPerUse. 86 // This is used by the x86-64 and ARM Thumb targets where some registers 87 // require larger instruction encodings. 88 int CostPerUse = 0; 89} 90 91// RegisterWithSubRegs - This can be used to define instances of Register which 92// need to specify sub-registers. 93// List "subregs" specifies which registers are sub-registers to this one. This 94// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 95// This allows the code generator to be careful not to put two values with 96// overlapping live ranges into registers which alias. 97class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 98 let SubRegs = subregs; 99} 100 101// RegisterClass - Now that all of the registers are defined, and aliases 102// between registers are defined, specify which registers belong to which 103// register classes. This also defines the default allocation order of 104// registers by register allocators. 105// 106class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 107 dag regList, RegAltNameIndex idx = NoRegAltName> { 108 string Namespace = namespace; 109 110 // RegType - Specify the list ValueType of the registers in this register 111 // class. Note that all registers in a register class must have the same 112 // ValueTypes. This is a list because some targets permit storing different 113 // types in same register, for example vector values with 128-bit total size, 114 // but different count/size of items, like SSE on x86. 115 // 116 list<ValueType> RegTypes = regTypes; 117 118 // Size - Specify the spill size in bits of the registers. A default value of 119 // zero lets tablgen pick an appropriate size. 120 int Size = 0; 121 122 // Alignment - Specify the alignment required of the registers when they are 123 // stored or loaded to memory. 124 // 125 int Alignment = alignment; 126 127 // CopyCost - This value is used to specify the cost of copying a value 128 // between two registers in this register class. The default value is one 129 // meaning it takes a single instruction to perform the copying. A negative 130 // value means copying is extremely expensive or impossible. 131 int CopyCost = 1; 132 133 // MemberList - Specify which registers are in this class. If the 134 // allocation_order_* method are not specified, this also defines the order of 135 // allocation used by the register allocator. 136 // 137 dag MemberList = regList; 138 139 // AltNameIndex - The alternate register name to use when printing operands 140 // of this register class. Every register in the register class must have 141 // a valid alternate name for the given index. 142 RegAltNameIndex altNameIndex = idx; 143 144 // SubRegClasses - Specify the register class of subregisters as a list of 145 // dags: (RegClass SubRegIndex, SubRegindex, ...) 146 list<dag> SubRegClasses = []; 147 148 // isAllocatable - Specify that the register class can be used for virtual 149 // registers and register allocation. Some register classes are only used to 150 // model instruction operand constraints, and should have isAllocatable = 0. 151 bit isAllocatable = 1; 152 153 // AltOrders - List of alternative allocation orders. The default order is 154 // MemberList itself, and that is good enough for most targets since the 155 // register allocators automatically remove reserved registers and move 156 // callee-saved registers to the end. 157 list<dag> AltOrders = []; 158 159 // AltOrderSelect - The body of a function that selects the allocation order 160 // to use in a given machine function. The code will be inserted in a 161 // function like this: 162 // 163 // static inline unsigned f(const MachineFunction &MF) { ... } 164 // 165 // The function should return 0 to select the default order defined by 166 // MemberList, 1 to select the first AltOrders entry and so on. 167 code AltOrderSelect = [{}]; 168} 169 170// The memberList in a RegisterClass is a dag of set operations. TableGen 171// evaluates these set operations and expand them into register lists. These 172// are the most common operation, see test/TableGen/SetTheory.td for more 173// examples of what is possible: 174// 175// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 176// register class, or a sub-expression. This is also the way to simply list 177// registers. 178// 179// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 180// 181// (and GPR, CSR) - Set intersection. All registers from the first set that are 182// also in the second set. 183// 184// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 185// numbered registers. 186// 187// (shl GPR, 4) - Remove the first N elements. 188// 189// (trunc GPR, 4) - Truncate after the first N elements. 190// 191// (rotl GPR, 1) - Rotate N places to the left. 192// 193// (rotr GPR, 1) - Rotate N places to the right. 194// 195// (decimate GPR, 2) - Pick every N'th element, starting with the first. 196// 197// All of these operators work on ordered sets, not lists. That means 198// duplicates are removed from sub-expressions. 199 200// Set operators. The rest is defined in TargetSelectionDAG.td. 201def sequence; 202def decimate; 203 204// RegisterTuples - Automatically generate super-registers by forming tuples of 205// sub-registers. This is useful for modeling register sequence constraints 206// with pseudo-registers that are larger than the architectural registers. 207// 208// The sub-register lists are zipped together: 209// 210// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 211// 212// Generates the same registers as: 213// 214// let SubRegIndices = [sube, subo] in { 215// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 216// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 217// } 218// 219// The generated pseudo-registers inherit super-classes and fields from their 220// first sub-register. Most fields from the Register class are inferred, and 221// the AsmName and Dwarf numbers are cleared. 222// 223// RegisterTuples instances can be used in other set operations to form 224// register classes and so on. This is the only way of using the generated 225// registers. 226class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 227 // SubRegs - N lists of registers to be zipped up. Super-registers are 228 // synthesized from the first element of each SubRegs list, the second 229 // element and so on. 230 list<dag> SubRegs = Regs; 231 232 // SubRegIndices - N SubRegIndex instances. This provides the names of the 233 // sub-registers in the synthesized super-registers. 234 list<SubRegIndex> SubRegIndices = Indices; 235 236 // Compose sub-register indices like in a normal Register. 237 list<dag> CompositeIndices = []; 238} 239 240 241//===----------------------------------------------------------------------===// 242// DwarfRegNum - This class provides a mapping of the llvm register enumeration 243// to the register numbering used by gcc and gdb. These values are used by a 244// debug information writer to describe where values may be located during 245// execution. 246class DwarfRegNum<list<int> Numbers> { 247 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 248 // These values can be determined by locating the <target>.h file in the 249 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 250 // order of these names correspond to the enumeration used by gcc. A value of 251 // -1 indicates that the gcc number is undefined and -2 that register number 252 // is invalid for this mode/flavour. 253 list<int> DwarfNumbers = Numbers; 254} 255 256// DwarfRegAlias - This class declares that a given register uses the same dwarf 257// numbers as another one. This is useful for making it clear that the two 258// registers do have the same number. It also lets us build a mapping 259// from dwarf register number to llvm register. 260class DwarfRegAlias<Register reg> { 261 Register DwarfAlias = reg; 262} 263 264//===----------------------------------------------------------------------===// 265// Pull in the common support for scheduling 266// 267include "llvm/Target/TargetSchedule.td" 268 269class Predicate; // Forward def 270 271//===----------------------------------------------------------------------===// 272// Instruction set description - These classes correspond to the C++ classes in 273// the Target/TargetInstrInfo.h file. 274// 275class Instruction { 276 string Namespace = ""; 277 278 dag OutOperandList; // An dag containing the MI def operand list. 279 dag InOperandList; // An dag containing the MI use operand list. 280 string AsmString = ""; // The .s format to print the instruction with. 281 282 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 283 // otherwise, uninitialized. 284 list<dag> Pattern; 285 286 // The follow state will eventually be inferred automatically from the 287 // instruction pattern. 288 289 list<Register> Uses = []; // Default to using no non-operand registers 290 list<Register> Defs = []; // Default to modifying no non-operand registers 291 292 // Predicates - List of predicates which will be turned into isel matching 293 // code. 294 list<Predicate> Predicates = []; 295 296 // Size - Size of encoded instruction, or zero if the size cannot be determined 297 // from the opcode. 298 int Size = 0; 299 300 // DecoderNamespace - The "namespace" in which this instruction exists, on 301 // targets like ARM which multiple ISA namespaces exist. 302 string DecoderNamespace = ""; 303 304 // Code size, for instruction selection. 305 // FIXME: What does this actually mean? 306 int CodeSize = 0; 307 308 // Added complexity passed onto matching pattern. 309 int AddedComplexity = 0; 310 311 // These bits capture information about the high-level semantics of the 312 // instruction. 313 bit isReturn = 0; // Is this instruction a return instruction? 314 bit isBranch = 0; // Is this instruction a branch instruction? 315 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 316 bit isCompare = 0; // Is this instruction a comparison instruction? 317 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 318 bit isBitcast = 0; // Is this instruction a bitcast instruction? 319 bit isBarrier = 0; // Can control flow fall through this instruction? 320 bit isCall = 0; // Is this instruction a call instruction? 321 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 322 bit mayLoad = 0; // Is it possible for this inst to read memory? 323 bit mayStore = 0; // Is it possible for this inst to write memory? 324 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 325 bit isCommutable = 0; // Is this 3 operand instruction commutable? 326 bit isTerminator = 0; // Is this part of the terminator for a basic block? 327 bit isReMaterializable = 0; // Is this instruction re-materializable? 328 bit isPredicable = 0; // Is this instruction predicable? 329 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 330 bit usesCustomInserter = 0; // Pseudo instr needing special help. 331 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 332 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 333 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 334 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 335 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 336 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 337 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 338 // If so, won't have encoding information for 339 // the [MC]CodeEmitter stuff. 340 341 // Side effect flags - When set, the flags have these meanings: 342 // 343 // hasSideEffects - The instruction has side effects that are not 344 // captured by any operands of the instruction or other flags. 345 // 346 // neverHasSideEffects - Set on an instruction with no pattern if it has no 347 // side effects. 348 bit hasSideEffects = 0; 349 bit neverHasSideEffects = 0; 350 351 // Is this instruction a "real" instruction (with a distinct machine 352 // encoding), or is it a pseudo instruction used for codegen modeling 353 // purposes. 354 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 355 // instructions can (and often do) still have encoding information 356 // associated with them. Once we've migrated all of them over to true 357 // pseudo-instructions that are lowered to real instructions prior to 358 // the printer/emitter, we can remove this attribute and just use isPseudo. 359 // 360 // The intended use is: 361 // isPseudo: Does not have encoding information and should be expanded, 362 // at the latest, during lowering to MCInst. 363 // 364 // isCodeGenOnly: Does have encoding information and can go through to the 365 // CodeEmitter unchanged, but duplicates a canonical instruction 366 // definition's encoding and should be ignored when constructing the 367 // assembler match tables. 368 bit isCodeGenOnly = 0; 369 370 // Is this instruction a pseudo instruction for use by the assembler parser. 371 bit isAsmParserOnly = 0; 372 373 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 374 375 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 376 377 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 378 /// be encoded into the output machineinstr. 379 string DisableEncoding = ""; 380 381 string PostEncoderMethod = ""; 382 string DecoderMethod = ""; 383 384 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 385 bits<64> TSFlags = 0; 386 387 ///@name Assembler Parser Support 388 ///@{ 389 390 string AsmMatchConverter = ""; 391 392 ///@} 393} 394 395/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 396/// Which instruction it expands to and how the operands map from the 397/// pseudo. 398class PseudoInstExpansion<dag Result> { 399 dag ResultInst = Result; // The instruction to generate. 400 bit isPseudo = 1; 401} 402 403/// Predicates - These are extra conditionals which are turned into instruction 404/// selector matching code. Currently each predicate is just a string. 405class Predicate<string cond> { 406 string CondString = cond; 407 408 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 409 /// matcher, this is true. Targets should set this by inheriting their 410 /// feature from the AssemblerPredicate class in addition to Predicate. 411 bit AssemblerMatcherPredicate = 0; 412 413 /// AssemblerCondString - Name of the subtarget feature being tested used 414 /// as alternative condition string used for assembler matcher. 415 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 416 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 417 /// It can also list multiple features separated by ",". 418 /// e.g. "ModeThumb,FeatureThumb2" is translated to 419 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 420 string AssemblerCondString = ""; 421} 422 423/// NoHonorSignDependentRounding - This predicate is true if support for 424/// sign-dependent-rounding is not enabled. 425def NoHonorSignDependentRounding 426 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 427 428class Requires<list<Predicate> preds> { 429 list<Predicate> Predicates = preds; 430} 431 432/// ops definition - This is just a simple marker used to identify the operand 433/// list for an instruction. outs and ins are identical both syntactically and 434/// semanticallyr; they are used to define def operands and use operands to 435/// improve readibility. This should be used like this: 436/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 437def ops; 438def outs; 439def ins; 440 441/// variable_ops definition - Mark this instruction as taking a variable number 442/// of operands. 443def variable_ops; 444 445 446/// PointerLikeRegClass - Values that are designed to have pointer width are 447/// derived from this. TableGen treats the register class as having a symbolic 448/// type that it doesn't know, and resolves the actual regclass to use by using 449/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 450class PointerLikeRegClass<int Kind> { 451 int RegClassKind = Kind; 452} 453 454 455/// ptr_rc definition - Mark this operand as being a pointer value whose 456/// register class is resolved dynamically via a callback to TargetInstrInfo. 457/// FIXME: We should probably change this to a class which contain a list of 458/// flags. But currently we have but one flag. 459def ptr_rc : PointerLikeRegClass<0>; 460 461/// unknown definition - Mark this operand as being of unknown type, causing 462/// it to be resolved by inference in the context it is used. 463def unknown; 464 465/// AsmOperandClass - Representation for the kinds of operands which the target 466/// specific parser can create and the assembly matcher may need to distinguish. 467/// 468/// Operand classes are used to define the order in which instructions are 469/// matched, to ensure that the instruction which gets matched for any 470/// particular list of operands is deterministic. 471/// 472/// The target specific parser must be able to classify a parsed operand into a 473/// unique class which does not partially overlap with any other classes. It can 474/// match a subset of some other class, in which case the super class field 475/// should be defined. 476class AsmOperandClass { 477 /// The name to use for this class, which should be usable as an enum value. 478 string Name = ?; 479 480 /// The super classes of this operand. 481 list<AsmOperandClass> SuperClasses = []; 482 483 /// The name of the method on the target specific operand to call to test 484 /// whether the operand is an instance of this class. If not set, this will 485 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 486 /// signature should be: 487 /// bool isFoo() const; 488 string PredicateMethod = ?; 489 490 /// The name of the method on the target specific operand to call to add the 491 /// target specific operand to an MCInst. If not set, this will default to 492 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 493 /// signature should be: 494 /// void addFooOperands(MCInst &Inst, unsigned N) const; 495 string RenderMethod = ?; 496 497 /// The name of the method on the target specific operand to call to custom 498 /// handle the operand parsing. This is useful when the operands do not relate 499 /// to immediates or registers and are very instruction specific (as flags to 500 /// set in a processor register, coprocessor number, ...). 501 string ParserMethod = ?; 502} 503 504def ImmAsmOperand : AsmOperandClass { 505 let Name = "Imm"; 506} 507 508/// Operand Types - These provide the built-in operand types that may be used 509/// by a target. Targets can optionally provide their own operand types as 510/// needed, though this should not be needed for RISC targets. 511class Operand<ValueType ty> { 512 ValueType Type = ty; 513 string PrintMethod = "printOperand"; 514 string EncoderMethod = ""; 515 string DecoderMethod = ""; 516 string AsmOperandLowerMethod = ?; 517 string OperandType = "OPERAND_UNKNOWN"; 518 dag MIOperandInfo = (ops); 519 520 // ParserMatchClass - The "match class" that operands of this type fit 521 // in. Match classes are used to define the order in which instructions are 522 // match, to ensure that which instructions gets matched is deterministic. 523 // 524 // The target specific parser must be able to classify an parsed operand into 525 // a unique class, which does not partially overlap with any other classes. It 526 // can match a subset of some other class, in which case the AsmOperandClass 527 // should declare the other operand as one of its super classes. 528 AsmOperandClass ParserMatchClass = ImmAsmOperand; 529} 530 531class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> { 532 // RegClass - The register class of the operand. 533 RegisterClass RegClass = regclass; 534 // PrintMethod - The target method to call to print register operands of 535 // this type. The method normally will just use an alt-name index to look 536 // up the name to print. Default to the generic printOperand(). 537 string PrintMethod = pm; 538 // ParserMatchClass - The "match class" that operands of this type fit 539 // in. Match classes are used to define the order in which instructions are 540 // match, to ensure that which instructions gets matched is deterministic. 541 // 542 // The target specific parser must be able to classify an parsed operand into 543 // a unique class, which does not partially overlap with any other classes. It 544 // can match a subset of some other class, in which case the AsmOperandClass 545 // should declare the other operand as one of its super classes. 546 AsmOperandClass ParserMatchClass; 547} 548 549let OperandType = "OPERAND_IMMEDIATE" in { 550def i1imm : Operand<i1>; 551def i8imm : Operand<i8>; 552def i16imm : Operand<i16>; 553def i32imm : Operand<i32>; 554def i64imm : Operand<i64>; 555 556def f32imm : Operand<f32>; 557def f64imm : Operand<f64>; 558} 559 560/// zero_reg definition - Special node to stand for the zero register. 561/// 562def zero_reg; 563 564/// PredicateOperand - This can be used to define a predicate operand for an 565/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 566/// AlwaysVal specifies the value of this predicate when set to "always 567/// execute". 568class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 569 : Operand<ty> { 570 let MIOperandInfo = OpTypes; 571 dag DefaultOps = AlwaysVal; 572} 573 574/// OptionalDefOperand - This is used to define a optional definition operand 575/// for an instruction. DefaultOps is the register the operand represents if 576/// none is supplied, e.g. zero_reg. 577class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 578 : Operand<ty> { 579 let MIOperandInfo = OpTypes; 580 dag DefaultOps = defaultops; 581} 582 583 584// InstrInfo - This class should only be instantiated once to provide parameters 585// which are global to the target machine. 586// 587class InstrInfo { 588 // Target can specify its instructions in either big or little-endian formats. 589 // For instance, while both Sparc and PowerPC are big-endian platforms, the 590 // Sparc manual specifies its instructions in the format [31..0] (big), while 591 // PowerPC specifies them using the format [0..31] (little). 592 bit isLittleEndianEncoding = 0; 593} 594 595// Standard Pseudo Instructions. 596// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 597// Only these instructions are allowed in the TargetOpcode namespace. 598let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 599def PHI : Instruction { 600 let OutOperandList = (outs); 601 let InOperandList = (ins variable_ops); 602 let AsmString = "PHINODE"; 603} 604def INLINEASM : Instruction { 605 let OutOperandList = (outs); 606 let InOperandList = (ins variable_ops); 607 let AsmString = ""; 608 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 609} 610def PROLOG_LABEL : Instruction { 611 let OutOperandList = (outs); 612 let InOperandList = (ins i32imm:$id); 613 let AsmString = ""; 614 let hasCtrlDep = 1; 615 let isNotDuplicable = 1; 616} 617def EH_LABEL : Instruction { 618 let OutOperandList = (outs); 619 let InOperandList = (ins i32imm:$id); 620 let AsmString = ""; 621 let hasCtrlDep = 1; 622 let isNotDuplicable = 1; 623} 624def GC_LABEL : Instruction { 625 let OutOperandList = (outs); 626 let InOperandList = (ins i32imm:$id); 627 let AsmString = ""; 628 let hasCtrlDep = 1; 629 let isNotDuplicable = 1; 630} 631def KILL : Instruction { 632 let OutOperandList = (outs); 633 let InOperandList = (ins variable_ops); 634 let AsmString = ""; 635 let neverHasSideEffects = 1; 636} 637def EXTRACT_SUBREG : Instruction { 638 let OutOperandList = (outs unknown:$dst); 639 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 640 let AsmString = ""; 641 let neverHasSideEffects = 1; 642} 643def INSERT_SUBREG : Instruction { 644 let OutOperandList = (outs unknown:$dst); 645 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 646 let AsmString = ""; 647 let neverHasSideEffects = 1; 648 let Constraints = "$supersrc = $dst"; 649} 650def IMPLICIT_DEF : Instruction { 651 let OutOperandList = (outs unknown:$dst); 652 let InOperandList = (ins); 653 let AsmString = ""; 654 let neverHasSideEffects = 1; 655 let isReMaterializable = 1; 656 let isAsCheapAsAMove = 1; 657} 658def SUBREG_TO_REG : Instruction { 659 let OutOperandList = (outs unknown:$dst); 660 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 661 let AsmString = ""; 662 let neverHasSideEffects = 1; 663} 664def COPY_TO_REGCLASS : Instruction { 665 let OutOperandList = (outs unknown:$dst); 666 let InOperandList = (ins unknown:$src, i32imm:$regclass); 667 let AsmString = ""; 668 let neverHasSideEffects = 1; 669 let isAsCheapAsAMove = 1; 670} 671def DBG_VALUE : Instruction { 672 let OutOperandList = (outs); 673 let InOperandList = (ins variable_ops); 674 let AsmString = "DBG_VALUE"; 675 let neverHasSideEffects = 1; 676} 677def REG_SEQUENCE : Instruction { 678 let OutOperandList = (outs unknown:$dst); 679 let InOperandList = (ins variable_ops); 680 let AsmString = ""; 681 let neverHasSideEffects = 1; 682 let isAsCheapAsAMove = 1; 683} 684def COPY : Instruction { 685 let OutOperandList = (outs unknown:$dst); 686 let InOperandList = (ins unknown:$src); 687 let AsmString = ""; 688 let neverHasSideEffects = 1; 689 let isAsCheapAsAMove = 1; 690} 691def BUNDLE : Instruction { 692 let OutOperandList = (outs); 693 let InOperandList = (ins variable_ops); 694 let AsmString = "BUNDLE"; 695} 696} 697 698//===----------------------------------------------------------------------===// 699// AsmParser - This class can be implemented by targets that wish to implement 700// .s file parsing. 701// 702// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 703// syntax on X86 for example). 704// 705class AsmParser { 706 // AsmParserClassName - This specifies the suffix to use for the asmparser 707 // class. Generated AsmParser classes are always prefixed with the target 708 // name. 709 string AsmParserClassName = "AsmParser"; 710 711 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 712 // function of the AsmParser class to call on every matched instruction. 713 // This can be used to perform target specific instruction post-processing. 714 string AsmParserInstCleanup = ""; 715 716 // Variant - AsmParsers can be of multiple different variants. Variants are 717 // used to support targets that need to parser multiple formats for the 718 // assembly language. 719 int Variant = 0; 720 721 // CommentDelimiter - If given, the delimiter string used to recognize 722 // comments which are hard coded in the .td assembler strings for individual 723 // instructions. 724 string CommentDelimiter = ""; 725 726 // RegisterPrefix - If given, the token prefix which indicates a register 727 // token. This is used by the matcher to automatically recognize hard coded 728 // register tokens as constrained registers, instead of tokens, for the 729 // purposes of matching. 730 string RegisterPrefix = ""; 731} 732def DefaultAsmParser : AsmParser; 733 734/// AssemblerPredicate - This is a Predicate that can be used when the assembler 735/// matches instructions and aliases. 736class AssemblerPredicate<string cond> { 737 bit AssemblerMatcherPredicate = 1; 738 string AssemblerCondString = cond; 739} 740 741/// TokenAlias - This class allows targets to define assembler token 742/// operand aliases. That is, a token literal operand which is equivalent 743/// to another, canonical, token literal. For example, ARM allows: 744/// vmov.u32 s4, #0 -> vmov.i32, #0 745/// 'u32' is a more specific designator for the 32-bit integer type specifier 746/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 747/// def : TokenAlias<".u32", ".i32">; 748/// 749/// This works by marking the match class of 'From' as a subclass of the 750/// match class of 'To'. 751class TokenAlias<string From, string To> { 752 string FromToken = From; 753 string ToToken = To; 754} 755 756/// MnemonicAlias - This class allows targets to define assembler mnemonic 757/// aliases. This should be used when all forms of one mnemonic are accepted 758/// with a different mnemonic. For example, X86 allows: 759/// sal %al, 1 -> shl %al, 1 760/// sal %ax, %cl -> shl %ax, %cl 761/// sal %eax, %cl -> shl %eax, %cl 762/// etc. Though "sal" is accepted with many forms, all of them are directly 763/// translated to a shl, so it can be handled with (in the case of X86, it 764/// actually has one for each suffix as well): 765/// def : MnemonicAlias<"sal", "shl">; 766/// 767/// Mnemonic aliases are mapped before any other translation in the match phase, 768/// and do allow Requires predicates, e.g.: 769/// 770/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 771/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 772/// 773class MnemonicAlias<string From, string To> { 774 string FromMnemonic = From; 775 string ToMnemonic = To; 776 777 // Predicates - Predicates that must be true for this remapping to happen. 778 list<Predicate> Predicates = []; 779} 780 781/// InstAlias - This defines an alternate assembly syntax that is allowed to 782/// match an instruction that has a different (more canonical) assembly 783/// representation. 784class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 785 string AsmString = Asm; // The .s format to match the instruction with. 786 dag ResultInst = Result; // The MCInst to generate. 787 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 788 789 // Predicates - Predicates that must be true for this to match. 790 list<Predicate> Predicates = []; 791} 792 793//===----------------------------------------------------------------------===// 794// AsmWriter - This class can be implemented by targets that need to customize 795// the format of the .s file writer. 796// 797// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 798// on X86 for example). 799// 800class AsmWriter { 801 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 802 // class. Generated AsmWriter classes are always prefixed with the target 803 // name. 804 string AsmWriterClassName = "AsmPrinter"; 805 806 // Variant - AsmWriters can be of multiple different variants. Variants are 807 // used to support targets that need to emit assembly code in ways that are 808 // mostly the same for different targets, but have minor differences in 809 // syntax. If the asmstring contains {|} characters in them, this integer 810 // will specify which alternative to use. For example "{x|y|z}" with Variant 811 // == 1, will expand to "y". 812 int Variant = 0; 813 814 815 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 816 // layout, the asmwriter can actually generate output in this columns (in 817 // verbose-asm mode). These two values indicate the width of the first column 818 // (the "opcode" area) and the width to reserve for subsequent operands. When 819 // verbose asm mode is enabled, operands will be indented to respect this. 820 int FirstOperandColumn = -1; 821 822 // OperandSpacing - Space between operand columns. 823 int OperandSpacing = -1; 824 825 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 826 // generation of the printInstruction() method. For MC printers, it takes 827 // an MCInstr* operand, otherwise it takes a MachineInstr*. 828 bit isMCAsmWriter = 0; 829} 830def DefaultAsmWriter : AsmWriter; 831 832 833//===----------------------------------------------------------------------===// 834// Target - This class contains the "global" target information 835// 836class Target { 837 // InstructionSet - Instruction set description for this target. 838 InstrInfo InstructionSet; 839 840 // AssemblyParsers - The AsmParser instances available for this target. 841 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 842 843 // AssemblyWriters - The AsmWriter instances available for this target. 844 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 845} 846 847//===----------------------------------------------------------------------===// 848// SubtargetFeature - A characteristic of the chip set. 849// 850class SubtargetFeature<string n, string a, string v, string d, 851 list<SubtargetFeature> i = []> { 852 // Name - Feature name. Used by command line (-mattr=) to determine the 853 // appropriate target chip. 854 // 855 string Name = n; 856 857 // Attribute - Attribute to be set by feature. 858 // 859 string Attribute = a; 860 861 // Value - Value the attribute to be set to by feature. 862 // 863 string Value = v; 864 865 // Desc - Feature description. Used by command line (-mattr=) to display help 866 // information. 867 // 868 string Desc = d; 869 870 // Implies - Features that this feature implies are present. If one of those 871 // features isn't set, then this one shouldn't be set either. 872 // 873 list<SubtargetFeature> Implies = i; 874} 875 876//===----------------------------------------------------------------------===// 877// Processor chip sets - These values represent each of the chip sets supported 878// by the scheduler. Each Processor definition requires corresponding 879// instruction itineraries. 880// 881class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 882 // Name - Chip set name. Used by command line (-mcpu=) to determine the 883 // appropriate target chip. 884 // 885 string Name = n; 886 887 // ProcItin - The scheduling information for the target processor. 888 // 889 ProcessorItineraries ProcItin = pi; 890 891 // Features - list of 892 list<SubtargetFeature> Features = f; 893} 894 895//===----------------------------------------------------------------------===// 896// Pull in the common support for calling conventions. 897// 898include "llvm/Target/TargetCallingConv.td" 899 900//===----------------------------------------------------------------------===// 901// Pull in the common support for DAG isel generation. 902// 903include "llvm/Target/TargetSelectionDAG.td" 904