Target.td revision cf000c130ffc49ee2c2f82bc0187dafb73acae73
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex { 26 string Namespace = ""; 27} 28 29// Register - You should define one instance of this class for each register 30// in the target machine. String n will become the "name" of the register. 31class Register<string n> { 32 string Namespace = ""; 33 string AsmName = n; 34 35 // SpillSize - If this value is set to a non-zero value, it is the size in 36 // bits of the spill slot required to hold this register. If this value is 37 // set to zero, the information is inferred from any register classes the 38 // register belongs to. 39 int SpillSize = 0; 40 41 // SpillAlignment - This value is used to specify the alignment required for 42 // spilling the register. Like SpillSize, this should only be explicitly 43 // specified if the register is not in a register class. 44 int SpillAlignment = 0; 45 46 // Aliases - A list of registers that this register overlaps with. A read or 47 // modification of this register can potentially read or modify the aliased 48 // registers. 49 list<Register> Aliases = []; 50 51 // SubRegs - A list of registers that are parts of this register. Note these 52 // are "immediate" sub-registers and the registers within the list do not 53 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 54 // not [AX, AH, AL]. 55 list<Register> SubRegs = []; 56 57 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 58 // to address it. Sub-sub-register indices are automatically inherited from 59 // SubRegs. 60 list<SubRegIndex> SubRegIndices = []; 61 62 // CompositeIndices - Specify subreg indices that don't correspond directly to 63 // a register in SubRegs and are not inherited. The following formats are 64 // supported: 65 // 66 // (a) Identity - Reg:a == Reg 67 // (a b) Alias - Reg:a == Reg:b 68 // (a b,c) Composite - Reg:a == (Reg:b):c 69 // 70 // This can be used to disambiguate a sub-sub-register that exists in more 71 // than one subregister and other weird stuff. 72 list<dag> CompositeIndices = []; 73 74 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 75 // These values can be determined by locating the <target>.h file in the 76 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 77 // order of these names correspond to the enumeration used by gcc. A value of 78 // -1 indicates that the gcc number is undefined and -2 that register number 79 // is invalid for this mode/flavour. 80 list<int> DwarfNumbers = []; 81} 82 83// RegisterWithSubRegs - This can be used to define instances of Register which 84// need to specify sub-registers. 85// List "subregs" specifies which registers are sub-registers to this one. This 86// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 87// This allows the code generator to be careful not to put two values with 88// overlapping live ranges into registers which alias. 89class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 90 let SubRegs = subregs; 91} 92 93// RegisterClass - Now that all of the registers are defined, and aliases 94// between registers are defined, specify which registers belong to which 95// register classes. This also defines the default allocation order of 96// registers by register allocators. 97// 98class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 99 list<Register> regList> { 100 string Namespace = namespace; 101 102 // RegType - Specify the list ValueType of the registers in this register 103 // class. Note that all registers in a register class must have the same 104 // ValueTypes. This is a list because some targets permit storing different 105 // types in same register, for example vector values with 128-bit total size, 106 // but different count/size of items, like SSE on x86. 107 // 108 list<ValueType> RegTypes = regTypes; 109 110 // Size - Specify the spill size in bits of the registers. A default value of 111 // zero lets tablgen pick an appropriate size. 112 int Size = 0; 113 114 // Alignment - Specify the alignment required of the registers when they are 115 // stored or loaded to memory. 116 // 117 int Alignment = alignment; 118 119 // CopyCost - This value is used to specify the cost of copying a value 120 // between two registers in this register class. The default value is one 121 // meaning it takes a single instruction to perform the copying. A negative 122 // value means copying is extremely expensive or impossible. 123 int CopyCost = 1; 124 125 // MemberList - Specify which registers are in this class. If the 126 // allocation_order_* method are not specified, this also defines the order of 127 // allocation used by the register allocator. 128 // 129 list<Register> MemberList = regList; 130 131 // SubRegClasses - Specify the register class of subregisters as a list of 132 // dags: (RegClass SubRegIndex, SubRegindex, ...) 133 list<dag> SubRegClasses = []; 134 135 // MethodProtos/MethodBodies - These members can be used to insert arbitrary 136 // code into a generated register class. The normal usage of this is to 137 // overload virtual methods. 138 code MethodProtos = [{}]; 139 code MethodBodies = [{}]; 140} 141 142 143//===----------------------------------------------------------------------===// 144// DwarfRegNum - This class provides a mapping of the llvm register enumeration 145// to the register numbering used by gcc and gdb. These values are used by a 146// debug information writer to describe where values may be located during 147// execution. 148class DwarfRegNum<list<int> Numbers> { 149 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 150 // These values can be determined by locating the <target>.h file in the 151 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 152 // order of these names correspond to the enumeration used by gcc. A value of 153 // -1 indicates that the gcc number is undefined and -2 that register number 154 // is invalid for this mode/flavour. 155 list<int> DwarfNumbers = Numbers; 156} 157 158//===----------------------------------------------------------------------===// 159// Pull in the common support for scheduling 160// 161include "llvm/Target/TargetSchedule.td" 162 163class Predicate; // Forward def 164 165//===----------------------------------------------------------------------===// 166// Instruction set description - These classes correspond to the C++ classes in 167// the Target/TargetInstrInfo.h file. 168// 169class Instruction { 170 string Namespace = ""; 171 172 dag OutOperandList; // An dag containing the MI def operand list. 173 dag InOperandList; // An dag containing the MI use operand list. 174 string AsmString = ""; // The .s format to print the instruction with. 175 176 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 177 // otherwise, uninitialized. 178 list<dag> Pattern; 179 180 // The follow state will eventually be inferred automatically from the 181 // instruction pattern. 182 183 list<Register> Uses = []; // Default to using no non-operand registers 184 list<Register> Defs = []; // Default to modifying no non-operand registers 185 186 // Predicates - List of predicates which will be turned into isel matching 187 // code. 188 list<Predicate> Predicates = []; 189 190 // Code size. 191 int CodeSize = 0; 192 193 // Added complexity passed onto matching pattern. 194 int AddedComplexity = 0; 195 196 // These bits capture information about the high-level semantics of the 197 // instruction. 198 bit isReturn = 0; // Is this instruction a return instruction? 199 bit isBranch = 0; // Is this instruction a branch instruction? 200 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 201 bit isCompare = 0; // Is this instruction a comparison instruction? 202 bit isBarrier = 0; // Can control flow fall through this instruction? 203 bit isCall = 0; // Is this instruction a call instruction? 204 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 205 bit mayLoad = 0; // Is it possible for this inst to read memory? 206 bit mayStore = 0; // Is it possible for this inst to write memory? 207 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 208 bit isCommutable = 0; // Is this 3 operand instruction commutable? 209 bit isTerminator = 0; // Is this part of the terminator for a basic block? 210 bit isReMaterializable = 0; // Is this instruction re-materializable? 211 bit isPredicable = 0; // Is this instruction predicable? 212 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 213 bit usesCustomInserter = 0; // Pseudo instr needing special help. 214 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 215 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 216 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 217 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 218 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 219 220 // Side effect flags - When set, the flags have these meanings: 221 // 222 // hasSideEffects - The instruction has side effects that are not 223 // captured by any operands of the instruction or other flags. 224 // 225 // neverHasSideEffects - Set on an instruction with no pattern if it has no 226 // side effects. 227 bit hasSideEffects = 0; 228 bit neverHasSideEffects = 0; 229 230 // Is this instruction a "real" instruction (with a distinct machine 231 // encoding), or is it a pseudo instruction used for codegen modeling 232 // purposes. 233 bit isCodeGenOnly = 0; 234 235 // Is this instruction a pseudo instruction for use by the assembler parser. 236 bit isAsmParserOnly = 0; 237 238 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 239 240 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 241 242 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 243 /// be encoded into the output machineinstr. 244 string DisableEncoding = ""; 245 246 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 247 bits<64> TSFlags = 0; 248} 249 250/// Predicates - These are extra conditionals which are turned into instruction 251/// selector matching code. Currently each predicate is just a string. 252class Predicate<string cond> { 253 string CondString = cond; 254} 255 256/// NoHonorSignDependentRounding - This predicate is true if support for 257/// sign-dependent-rounding is not enabled. 258def NoHonorSignDependentRounding 259 : Predicate<"!HonorSignDependentRoundingFPMath()">; 260 261class Requires<list<Predicate> preds> { 262 list<Predicate> Predicates = preds; 263} 264 265/// ops definition - This is just a simple marker used to identify the operands 266/// list for an instruction. outs and ins are identical both syntatically and 267/// semantically, they are used to define def operands and use operands to 268/// improve readibility. This should be used like this: 269/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 270def ops; 271def outs; 272def ins; 273 274/// variable_ops definition - Mark this instruction as taking a variable number 275/// of operands. 276def variable_ops; 277 278 279/// PointerLikeRegClass - Values that are designed to have pointer width are 280/// derived from this. TableGen treats the register class as having a symbolic 281/// type that it doesn't know, and resolves the actual regclass to use by using 282/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 283class PointerLikeRegClass<int Kind> { 284 int RegClassKind = Kind; 285} 286 287 288/// ptr_rc definition - Mark this operand as being a pointer value whose 289/// register class is resolved dynamically via a callback to TargetInstrInfo. 290/// FIXME: We should probably change this to a class which contain a list of 291/// flags. But currently we have but one flag. 292def ptr_rc : PointerLikeRegClass<0>; 293 294/// unknown definition - Mark this operand as being of unknown type, causing 295/// it to be resolved by inference in the context it is used. 296def unknown; 297 298/// AsmOperandClass - Representation for the kinds of operands which the target 299/// specific parser can create and the assembly matcher may need to distinguish. 300/// 301/// Operand classes are used to define the order in which instructions are 302/// matched, to ensure that the instruction which gets matched for any 303/// particular list of operands is deterministic. 304/// 305/// The target specific parser must be able to classify a parsed operand into a 306/// unique class which does not partially overlap with any other classes. It can 307/// match a subset of some other class, in which case the super class field 308/// should be defined. 309class AsmOperandClass { 310 /// The name to use for this class, which should be usable as an enum value. 311 string Name = ?; 312 313 /// The super classes of this operand. 314 list<AsmOperandClass> SuperClasses = []; 315 316 /// The name of the method on the target specific operand to call to test 317 /// whether the operand is an instance of this class. If not set, this will 318 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 319 /// signature should be: 320 /// bool isFoo() const; 321 string PredicateMethod = ?; 322 323 /// The name of the method on the target specific operand to call to add the 324 /// target specific operand to an MCInst. If not set, this will default to 325 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 326 /// signature should be: 327 /// void addFooOperands(MCInst &Inst, unsigned N) const; 328 string RenderMethod = ?; 329} 330 331def ImmAsmOperand : AsmOperandClass { 332 let Name = "Imm"; 333} 334 335/// Operand Types - These provide the built-in operand types that may be used 336/// by a target. Targets can optionally provide their own operand types as 337/// needed, though this should not be needed for RISC targets. 338class Operand<ValueType ty> { 339 ValueType Type = ty; 340 string PrintMethod = "printOperand"; 341 string AsmOperandLowerMethod = ?; 342 dag MIOperandInfo = (ops); 343 344 // ParserMatchClass - The "match class" that operands of this type fit 345 // in. Match classes are used to define the order in which instructions are 346 // match, to ensure that which instructions gets matched is deterministic. 347 // 348 // The target specific parser must be able to classify an parsed operand into 349 // a unique class, which does not partially overlap with any other classes. It 350 // can match a subset of some other class, in which case the AsmOperandClass 351 // should declare the other operand as one of its super classes. 352 AsmOperandClass ParserMatchClass = ImmAsmOperand; 353} 354 355def i1imm : Operand<i1>; 356def i8imm : Operand<i8>; 357def i16imm : Operand<i16>; 358def i32imm : Operand<i32>; 359def i64imm : Operand<i64>; 360 361def f32imm : Operand<f32>; 362def f64imm : Operand<f64>; 363 364/// zero_reg definition - Special node to stand for the zero register. 365/// 366def zero_reg; 367 368/// PredicateOperand - This can be used to define a predicate operand for an 369/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 370/// AlwaysVal specifies the value of this predicate when set to "always 371/// execute". 372class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 373 : Operand<ty> { 374 let MIOperandInfo = OpTypes; 375 dag DefaultOps = AlwaysVal; 376} 377 378/// OptionalDefOperand - This is used to define a optional definition operand 379/// for an instruction. DefaultOps is the register the operand represents if 380/// none is supplied, e.g. zero_reg. 381class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 382 : Operand<ty> { 383 let MIOperandInfo = OpTypes; 384 dag DefaultOps = defaultops; 385} 386 387 388// InstrInfo - This class should only be instantiated once to provide parameters 389// which are global to the target machine. 390// 391class InstrInfo { 392 // Target can specify its instructions in either big or little-endian formats. 393 // For instance, while both Sparc and PowerPC are big-endian platforms, the 394 // Sparc manual specifies its instructions in the format [31..0] (big), while 395 // PowerPC specifies them using the format [0..31] (little). 396 bit isLittleEndianEncoding = 0; 397} 398 399// Standard Pseudo Instructions. 400// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 401// Only these instructions are allowed in the TargetOpcode namespace. 402let isCodeGenOnly = 1, Namespace = "TargetOpcode" in { 403def PHI : Instruction { 404 let OutOperandList = (outs); 405 let InOperandList = (ins variable_ops); 406 let AsmString = "PHINODE"; 407} 408def INLINEASM : Instruction { 409 let OutOperandList = (outs); 410 let InOperandList = (ins variable_ops); 411 let AsmString = ""; 412} 413def PROLOG_LABEL : Instruction { 414 let OutOperandList = (outs); 415 let InOperandList = (ins i32imm:$id); 416 let AsmString = ""; 417 let hasCtrlDep = 1; 418 let isNotDuplicable = 1; 419} 420def EH_LABEL : Instruction { 421 let OutOperandList = (outs); 422 let InOperandList = (ins i32imm:$id); 423 let AsmString = ""; 424 let hasCtrlDep = 1; 425 let isNotDuplicable = 1; 426} 427def GC_LABEL : Instruction { 428 let OutOperandList = (outs); 429 let InOperandList = (ins i32imm:$id); 430 let AsmString = ""; 431 let hasCtrlDep = 1; 432 let isNotDuplicable = 1; 433} 434def KILL : Instruction { 435 let OutOperandList = (outs); 436 let InOperandList = (ins variable_ops); 437 let AsmString = ""; 438 let neverHasSideEffects = 1; 439} 440def EXTRACT_SUBREG : Instruction { 441 let OutOperandList = (outs unknown:$dst); 442 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 443 let AsmString = ""; 444 let neverHasSideEffects = 1; 445} 446def INSERT_SUBREG : Instruction { 447 let OutOperandList = (outs unknown:$dst); 448 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 449 let AsmString = ""; 450 let neverHasSideEffects = 1; 451 let Constraints = "$supersrc = $dst"; 452} 453def IMPLICIT_DEF : Instruction { 454 let OutOperandList = (outs unknown:$dst); 455 let InOperandList = (ins); 456 let AsmString = ""; 457 let neverHasSideEffects = 1; 458 let isReMaterializable = 1; 459 let isAsCheapAsAMove = 1; 460} 461def SUBREG_TO_REG : Instruction { 462 let OutOperandList = (outs unknown:$dst); 463 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 464 let AsmString = ""; 465 let neverHasSideEffects = 1; 466} 467def COPY_TO_REGCLASS : Instruction { 468 let OutOperandList = (outs unknown:$dst); 469 let InOperandList = (ins unknown:$src, i32imm:$regclass); 470 let AsmString = ""; 471 let neverHasSideEffects = 1; 472 let isAsCheapAsAMove = 1; 473} 474def DBG_VALUE : Instruction { 475 let OutOperandList = (outs); 476 let InOperandList = (ins variable_ops); 477 let AsmString = "DBG_VALUE"; 478 let isAsCheapAsAMove = 1; 479} 480def REG_SEQUENCE : Instruction { 481 let OutOperandList = (outs unknown:$dst); 482 let InOperandList = (ins variable_ops); 483 let AsmString = ""; 484 let neverHasSideEffects = 1; 485 let isAsCheapAsAMove = 1; 486} 487def COPY : Instruction { 488 let OutOperandList = (outs unknown:$dst); 489 let InOperandList = (ins unknown:$src); 490 let AsmString = ""; 491 let neverHasSideEffects = 1; 492 let isAsCheapAsAMove = 1; 493} 494} 495 496//===----------------------------------------------------------------------===// 497// AsmParser - This class can be implemented by targets that wish to implement 498// .s file parsing. 499// 500// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 501// syntax on X86 for example). 502// 503class AsmParser { 504 // AsmParserClassName - This specifies the suffix to use for the asmparser 505 // class. Generated AsmParser classes are always prefixed with the target 506 // name. 507 string AsmParserClassName = "AsmParser"; 508 509 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 510 // function of the AsmParser class to call on every matched instruction. 511 // This can be used to perform target specific instruction post-processing. 512 string AsmParserInstCleanup = ""; 513 514 // Variant - AsmParsers can be of multiple different variants. Variants are 515 // used to support targets that need to parser multiple formats for the 516 // assembly language. 517 int Variant = 0; 518 519 // CommentDelimiter - If given, the delimiter string used to recognize 520 // comments which are hard coded in the .td assembler strings for individual 521 // instructions. 522 string CommentDelimiter = ""; 523 524 // RegisterPrefix - If given, the token prefix which indicates a register 525 // token. This is used by the matcher to automatically recognize hard coded 526 // register tokens as constrained registers, instead of tokens, for the 527 // purposes of matching. 528 string RegisterPrefix = ""; 529} 530def DefaultAsmParser : AsmParser; 531 532 533//===----------------------------------------------------------------------===// 534// AsmWriter - This class can be implemented by targets that need to customize 535// the format of the .s file writer. 536// 537// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 538// on X86 for example). 539// 540class AsmWriter { 541 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 542 // class. Generated AsmWriter classes are always prefixed with the target 543 // name. 544 string AsmWriterClassName = "AsmPrinter"; 545 546 // InstFormatName - AsmWriters can specify the name of the format string to 547 // print instructions with. 548 string InstFormatName = "AsmString"; 549 550 // Variant - AsmWriters can be of multiple different variants. Variants are 551 // used to support targets that need to emit assembly code in ways that are 552 // mostly the same for different targets, but have minor differences in 553 // syntax. If the asmstring contains {|} characters in them, this integer 554 // will specify which alternative to use. For example "{x|y|z}" with Variant 555 // == 1, will expand to "y". 556 int Variant = 0; 557 558 559 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 560 // layout, the asmwriter can actually generate output in this columns (in 561 // verbose-asm mode). These two values indicate the width of the first column 562 // (the "opcode" area) and the width to reserve for subsequent operands. When 563 // verbose asm mode is enabled, operands will be indented to respect this. 564 int FirstOperandColumn = -1; 565 566 // OperandSpacing - Space between operand columns. 567 int OperandSpacing = -1; 568 569 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 570 // generation of the printInstruction() method. For MC printers, it takes 571 // an MCInstr* operand, otherwise it takes a MachineInstr*. 572 bit isMCAsmWriter = 0; 573} 574def DefaultAsmWriter : AsmWriter; 575 576 577//===----------------------------------------------------------------------===// 578// Target - This class contains the "global" target information 579// 580class Target { 581 // InstructionSet - Instruction set description for this target. 582 InstrInfo InstructionSet; 583 584 // AssemblyParsers - The AsmParser instances available for this target. 585 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 586 587 // AssemblyWriters - The AsmWriter instances available for this target. 588 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 589} 590 591//===----------------------------------------------------------------------===// 592// SubtargetFeature - A characteristic of the chip set. 593// 594class SubtargetFeature<string n, string a, string v, string d, 595 list<SubtargetFeature> i = []> { 596 // Name - Feature name. Used by command line (-mattr=) to determine the 597 // appropriate target chip. 598 // 599 string Name = n; 600 601 // Attribute - Attribute to be set by feature. 602 // 603 string Attribute = a; 604 605 // Value - Value the attribute to be set to by feature. 606 // 607 string Value = v; 608 609 // Desc - Feature description. Used by command line (-mattr=) to display help 610 // information. 611 // 612 string Desc = d; 613 614 // Implies - Features that this feature implies are present. If one of those 615 // features isn't set, then this one shouldn't be set either. 616 // 617 list<SubtargetFeature> Implies = i; 618} 619 620//===----------------------------------------------------------------------===// 621// Processor chip sets - These values represent each of the chip sets supported 622// by the scheduler. Each Processor definition requires corresponding 623// instruction itineraries. 624// 625class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 626 // Name - Chip set name. Used by command line (-mcpu=) to determine the 627 // appropriate target chip. 628 // 629 string Name = n; 630 631 // ProcItin - The scheduling information for the target processor. 632 // 633 ProcessorItineraries ProcItin = pi; 634 635 // Features - list of 636 list<SubtargetFeature> Features = f; 637} 638 639//===----------------------------------------------------------------------===// 640// Pull in the common support for calling conventions. 641// 642include "llvm/Target/TargetCallingConv.td" 643 644//===----------------------------------------------------------------------===// 645// Pull in the common support for DAG isel generation. 646// 647include "llvm/Target/TargetSelectionDAG.td" 648