Target.td revision f3ef5332fa3f4d5ec72c178a2b19dac363a19383
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/IR/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex<int size, int offset = 0> { 26 string Namespace = ""; 27 28 // Size - Size (in bits) of the sub-registers represented by this index. 29 int Size = size; 30 31 // Offset - Offset of the first bit that is part of this sub-register index. 32 // Set it to -1 if the same index is used to represent sub-registers that can 33 // be at different offsets (for example when using an index to access an 34 // element in a register tuple). 35 int Offset = offset; 36 37 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 38 // This indicates that this SubRegIndex is the result of composing A and B. 39 // See ComposedSubRegIndex. 40 list<SubRegIndex> ComposedOf = []; 41 42 // CoveringSubRegIndices - A list of two or more sub-register indexes that 43 // cover this sub-register. 44 // 45 // This field should normally be left blank as TableGen can infer it. 46 // 47 // TableGen automatically detects sub-registers that straddle the registers 48 // in the SubRegs field of a Register definition. For example: 49 // 50 // Q0 = dsub_0 -> D0, dsub_1 -> D1 51 // Q1 = dsub_0 -> D2, dsub_1 -> D3 52 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 53 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 54 // 55 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 57 // CoveringSubRegIndices = [dsub_1, dsub_2]. 58 list<SubRegIndex> CoveringSubRegIndices = []; 59} 60 61// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 62// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 63class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, 65 !if(!eq(B.Offset, -1), -1, 66 !add(A.Offset, B.Offset)))> { 67 // See SubRegIndex. 68 let ComposedOf = [A, B]; 69} 70 71// RegAltNameIndex - The alternate name set to use for register operands of 72// this register class when printing. 73class RegAltNameIndex { 74 string Namespace = ""; 75} 76def NoRegAltName : RegAltNameIndex; 77 78// Register - You should define one instance of this class for each register 79// in the target machine. String n will become the "name" of the register. 80class Register<string n, list<string> altNames = []> { 81 string Namespace = ""; 82 string AsmName = n; 83 list<string> AltNames = altNames; 84 85 // Aliases - A list of registers that this register overlaps with. A read or 86 // modification of this register can potentially read or modify the aliased 87 // registers. 88 list<Register> Aliases = []; 89 90 // SubRegs - A list of registers that are parts of this register. Note these 91 // are "immediate" sub-registers and the registers within the list do not 92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 93 // not [AX, AH, AL]. 94 list<Register> SubRegs = []; 95 96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 97 // to address it. Sub-sub-register indices are automatically inherited from 98 // SubRegs. 99 list<SubRegIndex> SubRegIndices = []; 100 101 // RegAltNameIndices - The alternate name indices which are valid for this 102 // register. 103 list<RegAltNameIndex> RegAltNameIndices = []; 104 105 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 106 // These values can be determined by locating the <target>.h file in the 107 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 108 // order of these names correspond to the enumeration used by gcc. A value of 109 // -1 indicates that the gcc number is undefined and -2 that register number 110 // is invalid for this mode/flavour. 111 list<int> DwarfNumbers = []; 112 113 // CostPerUse - Additional cost of instructions using this register compared 114 // to other registers in its class. The register allocator will try to 115 // minimize the number of instructions using a register with a CostPerUse. 116 // This is used by the x86-64 and ARM Thumb targets where some registers 117 // require larger instruction encodings. 118 int CostPerUse = 0; 119 120 // CoveredBySubRegs - When this bit is set, the value of this register is 121 // completely determined by the value of its sub-registers. For example, the 122 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 123 // covered by its sub-register AX. 124 bit CoveredBySubRegs = 0; 125 126 // HWEncoding - The target specific hardware encoding for this register. 127 bits<16> HWEncoding = 0; 128} 129 130// RegisterWithSubRegs - This can be used to define instances of Register which 131// need to specify sub-registers. 132// List "subregs" specifies which registers are sub-registers to this one. This 133// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 134// This allows the code generator to be careful not to put two values with 135// overlapping live ranges into registers which alias. 136class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 137 let SubRegs = subregs; 138} 139 140// DAGOperand - An empty base class that unifies RegisterClass's and other forms 141// of Operand's that are legal as type qualifiers in DAG patterns. This should 142// only ever be used for defining multiclasses that are polymorphic over both 143// RegisterClass's and other Operand's. 144class DAGOperand { } 145 146// RegisterClass - Now that all of the registers are defined, and aliases 147// between registers are defined, specify which registers belong to which 148// register classes. This also defines the default allocation order of 149// registers by register allocators. 150// 151class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 152 dag regList, RegAltNameIndex idx = NoRegAltName> 153 : DAGOperand { 154 string Namespace = namespace; 155 156 // RegType - Specify the list ValueType of the registers in this register 157 // class. Note that all registers in a register class must have the same 158 // ValueTypes. This is a list because some targets permit storing different 159 // types in same register, for example vector values with 128-bit total size, 160 // but different count/size of items, like SSE on x86. 161 // 162 list<ValueType> RegTypes = regTypes; 163 164 // Size - Specify the spill size in bits of the registers. A default value of 165 // zero lets tablgen pick an appropriate size. 166 int Size = 0; 167 168 // Alignment - Specify the alignment required of the registers when they are 169 // stored or loaded to memory. 170 // 171 int Alignment = alignment; 172 173 // CopyCost - This value is used to specify the cost of copying a value 174 // between two registers in this register class. The default value is one 175 // meaning it takes a single instruction to perform the copying. A negative 176 // value means copying is extremely expensive or impossible. 177 int CopyCost = 1; 178 179 // MemberList - Specify which registers are in this class. If the 180 // allocation_order_* method are not specified, this also defines the order of 181 // allocation used by the register allocator. 182 // 183 dag MemberList = regList; 184 185 // AltNameIndex - The alternate register name to use when printing operands 186 // of this register class. Every register in the register class must have 187 // a valid alternate name for the given index. 188 RegAltNameIndex altNameIndex = idx; 189 190 // isAllocatable - Specify that the register class can be used for virtual 191 // registers and register allocation. Some register classes are only used to 192 // model instruction operand constraints, and should have isAllocatable = 0. 193 bit isAllocatable = 1; 194 195 // AltOrders - List of alternative allocation orders. The default order is 196 // MemberList itself, and that is good enough for most targets since the 197 // register allocators automatically remove reserved registers and move 198 // callee-saved registers to the end. 199 list<dag> AltOrders = []; 200 201 // AltOrderSelect - The body of a function that selects the allocation order 202 // to use in a given machine function. The code will be inserted in a 203 // function like this: 204 // 205 // static inline unsigned f(const MachineFunction &MF) { ... } 206 // 207 // The function should return 0 to select the default order defined by 208 // MemberList, 1 to select the first AltOrders entry and so on. 209 code AltOrderSelect = [{}]; 210 211 // Specify allocation priority for register allocators using a greedy 212 // heuristic. Classes with higher priority values are assigned first. This is 213 // useful as it is sometimes beneficial to assign registers to highly 214 // constrained classes first. The value has to be in the range [0,63]. 215 int AllocationPriority = 0; 216} 217 218// The memberList in a RegisterClass is a dag of set operations. TableGen 219// evaluates these set operations and expand them into register lists. These 220// are the most common operation, see test/TableGen/SetTheory.td for more 221// examples of what is possible: 222// 223// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 224// register class, or a sub-expression. This is also the way to simply list 225// registers. 226// 227// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 228// 229// (and GPR, CSR) - Set intersection. All registers from the first set that are 230// also in the second set. 231// 232// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 233// numbered registers. Takes an optional 4th operand which is a stride to use 234// when generating the sequence. 235// 236// (shl GPR, 4) - Remove the first N elements. 237// 238// (trunc GPR, 4) - Truncate after the first N elements. 239// 240// (rotl GPR, 1) - Rotate N places to the left. 241// 242// (rotr GPR, 1) - Rotate N places to the right. 243// 244// (decimate GPR, 2) - Pick every N'th element, starting with the first. 245// 246// (interleave A, B, ...) - Interleave the elements from each argument list. 247// 248// All of these operators work on ordered sets, not lists. That means 249// duplicates are removed from sub-expressions. 250 251// Set operators. The rest is defined in TargetSelectionDAG.td. 252def sequence; 253def decimate; 254def interleave; 255 256// RegisterTuples - Automatically generate super-registers by forming tuples of 257// sub-registers. This is useful for modeling register sequence constraints 258// with pseudo-registers that are larger than the architectural registers. 259// 260// The sub-register lists are zipped together: 261// 262// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 263// 264// Generates the same registers as: 265// 266// let SubRegIndices = [sube, subo] in { 267// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 268// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 269// } 270// 271// The generated pseudo-registers inherit super-classes and fields from their 272// first sub-register. Most fields from the Register class are inferred, and 273// the AsmName and Dwarf numbers are cleared. 274// 275// RegisterTuples instances can be used in other set operations to form 276// register classes and so on. This is the only way of using the generated 277// registers. 278class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 279 // SubRegs - N lists of registers to be zipped up. Super-registers are 280 // synthesized from the first element of each SubRegs list, the second 281 // element and so on. 282 list<dag> SubRegs = Regs; 283 284 // SubRegIndices - N SubRegIndex instances. This provides the names of the 285 // sub-registers in the synthesized super-registers. 286 list<SubRegIndex> SubRegIndices = Indices; 287} 288 289 290//===----------------------------------------------------------------------===// 291// DwarfRegNum - This class provides a mapping of the llvm register enumeration 292// to the register numbering used by gcc and gdb. These values are used by a 293// debug information writer to describe where values may be located during 294// execution. 295class DwarfRegNum<list<int> Numbers> { 296 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 297 // These values can be determined by locating the <target>.h file in the 298 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 299 // order of these names correspond to the enumeration used by gcc. A value of 300 // -1 indicates that the gcc number is undefined and -2 that register number 301 // is invalid for this mode/flavour. 302 list<int> DwarfNumbers = Numbers; 303} 304 305// DwarfRegAlias - This class declares that a given register uses the same dwarf 306// numbers as another one. This is useful for making it clear that the two 307// registers do have the same number. It also lets us build a mapping 308// from dwarf register number to llvm register. 309class DwarfRegAlias<Register reg> { 310 Register DwarfAlias = reg; 311} 312 313//===----------------------------------------------------------------------===// 314// Pull in the common support for scheduling 315// 316include "llvm/Target/TargetSchedule.td" 317 318class Predicate; // Forward def 319 320//===----------------------------------------------------------------------===// 321// Instruction set description - These classes correspond to the C++ classes in 322// the Target/TargetInstrInfo.h file. 323// 324class Instruction { 325 string Namespace = ""; 326 327 dag OutOperandList; // An dag containing the MI def operand list. 328 dag InOperandList; // An dag containing the MI use operand list. 329 string AsmString = ""; // The .s format to print the instruction with. 330 331 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 332 // otherwise, uninitialized. 333 list<dag> Pattern; 334 335 // The follow state will eventually be inferred automatically from the 336 // instruction pattern. 337 338 list<Register> Uses = []; // Default to using no non-operand registers 339 list<Register> Defs = []; // Default to modifying no non-operand registers 340 341 // Predicates - List of predicates which will be turned into isel matching 342 // code. 343 list<Predicate> Predicates = []; 344 345 // Size - Size of encoded instruction, or zero if the size cannot be determined 346 // from the opcode. 347 int Size = 0; 348 349 // DecoderNamespace - The "namespace" in which this instruction exists, on 350 // targets like ARM which multiple ISA namespaces exist. 351 string DecoderNamespace = ""; 352 353 // Code size, for instruction selection. 354 // FIXME: What does this actually mean? 355 int CodeSize = 0; 356 357 // Added complexity passed onto matching pattern. 358 int AddedComplexity = 0; 359 360 // These bits capture information about the high-level semantics of the 361 // instruction. 362 bit isReturn = 0; // Is this instruction a return instruction? 363 bit isBranch = 0; // Is this instruction a branch instruction? 364 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 365 bit isCompare = 0; // Is this instruction a comparison instruction? 366 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 367 bit isBitcast = 0; // Is this instruction a bitcast instruction? 368 bit isSelect = 0; // Is this instruction a select instruction? 369 bit isBarrier = 0; // Can control flow fall through this instruction? 370 bit isCall = 0; // Is this instruction a call instruction? 371 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 372 bit mayLoad = ?; // Is it possible for this inst to read memory? 373 bit mayStore = ?; // Is it possible for this inst to write memory? 374 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 375 bit isCommutable = 0; // Is this 3 operand instruction commutable? 376 bit isTerminator = 0; // Is this part of the terminator for a basic block? 377 bit isReMaterializable = 0; // Is this instruction re-materializable? 378 bit isPredicable = 0; // Is this instruction predicable? 379 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 380 bit usesCustomInserter = 0; // Pseudo instr needing special help. 381 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 382 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 383 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 384 bit isConvergent = 0; // Is this instruction convergent? 385 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 386 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 387 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 388 bit isRegSequence = 0; // Is this instruction a kind of reg sequence? 389 // If so, make sure to override 390 // TargetInstrInfo::getRegSequenceLikeInputs. 391 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 392 // If so, won't have encoding information for 393 // the [MC]CodeEmitter stuff. 394 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg? 395 // If so, make sure to override 396 // TargetInstrInfo::getExtractSubregLikeInputs. 397 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg? 398 // If so, make sure to override 399 // TargetInstrInfo::getInsertSubregLikeInputs. 400 401 // Side effect flags - When set, the flags have these meanings: 402 // 403 // hasSideEffects - The instruction has side effects that are not 404 // captured by any operands of the instruction or other flags. 405 // 406 bit hasSideEffects = ?; 407 408 // Is this instruction a "real" instruction (with a distinct machine 409 // encoding), or is it a pseudo instruction used for codegen modeling 410 // purposes. 411 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 412 // instructions can (and often do) still have encoding information 413 // associated with them. Once we've migrated all of them over to true 414 // pseudo-instructions that are lowered to real instructions prior to 415 // the printer/emitter, we can remove this attribute and just use isPseudo. 416 // 417 // The intended use is: 418 // isPseudo: Does not have encoding information and should be expanded, 419 // at the latest, during lowering to MCInst. 420 // 421 // isCodeGenOnly: Does have encoding information and can go through to the 422 // CodeEmitter unchanged, but duplicates a canonical instruction 423 // definition's encoding and should be ignored when constructing the 424 // assembler match tables. 425 bit isCodeGenOnly = 0; 426 427 // Is this instruction a pseudo instruction for use by the assembler parser. 428 bit isAsmParserOnly = 0; 429 430 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 431 432 // Scheduling information from TargetSchedule.td. 433 list<SchedReadWrite> SchedRW; 434 435 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 436 437 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 438 /// be encoded into the output machineinstr. 439 string DisableEncoding = ""; 440 441 string PostEncoderMethod = ""; 442 string DecoderMethod = ""; 443 444 // Is the instruction decoder method able to completely determine if the 445 // given instruction is valid or not. If the TableGen definition of the 446 // instruction specifies bitpattern A??B where A and B are static bits, the 447 // hasCompleteDecoder flag says whether the decoder method fully handles the 448 // ?? space, i.e. if it is a final arbiter for the instruction validity. 449 // If not then the decoder attempts to continue decoding when the decoder 450 // method fails. 451 // 452 // This allows to handle situations where the encoding is not fully 453 // orthogonal. Example: 454 // * InstA with bitpattern 0b0000????, 455 // * InstB with bitpattern 0b000000?? but the associated decoder method 456 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11. 457 // 458 // The decoder tries to decode a bitpattern that matches both InstA and 459 // InstB bitpatterns first as InstB (because it is the most specific 460 // encoding). In the default case (hasCompleteDecoder = 1), when 461 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting 462 // hasCompleteDecoder = 0 in InstB, the decoder is informed that 463 // DecodeInstB() is not able to determine if all possible values of ?? are 464 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to 465 // decode the bitpattern as InstA too. 466 bit hasCompleteDecoder = 1; 467 468 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 469 bits<64> TSFlags = 0; 470 471 ///@name Assembler Parser Support 472 ///@{ 473 474 string AsmMatchConverter = ""; 475 476 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 477 /// two-operand matcher inst-alias for a three operand instruction. 478 /// For example, the arm instruction "add r3, r3, r5" can be written 479 /// as "add r3, r5". The constraint is of the same form as a tied-operand 480 /// constraint. For example, "$Rn = $Rd". 481 string TwoOperandAliasConstraint = ""; 482 483 ///@} 484 485 /// UseNamedOperandTable - If set, the operand indices of this instruction 486 /// can be queried via the getNamedOperandIdx() function which is generated 487 /// by TableGen. 488 bit UseNamedOperandTable = 0; 489} 490 491/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 492/// Which instruction it expands to and how the operands map from the 493/// pseudo. 494class PseudoInstExpansion<dag Result> { 495 dag ResultInst = Result; // The instruction to generate. 496 bit isPseudo = 1; 497} 498 499/// Predicates - These are extra conditionals which are turned into instruction 500/// selector matching code. Currently each predicate is just a string. 501class Predicate<string cond> { 502 string CondString = cond; 503 504 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 505 /// matcher, this is true. Targets should set this by inheriting their 506 /// feature from the AssemblerPredicate class in addition to Predicate. 507 bit AssemblerMatcherPredicate = 0; 508 509 /// AssemblerCondString - Name of the subtarget feature being tested used 510 /// as alternative condition string used for assembler matcher. 511 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 512 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 513 /// It can also list multiple features separated by ",". 514 /// e.g. "ModeThumb,FeatureThumb2" is translated to 515 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 516 string AssemblerCondString = ""; 517 518 /// PredicateName - User-level name to use for the predicate. Mainly for use 519 /// in diagnostics such as missing feature errors in the asm matcher. 520 string PredicateName = ""; 521} 522 523/// NoHonorSignDependentRounding - This predicate is true if support for 524/// sign-dependent-rounding is not enabled. 525def NoHonorSignDependentRounding 526 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 527 528class Requires<list<Predicate> preds> { 529 list<Predicate> Predicates = preds; 530} 531 532/// ops definition - This is just a simple marker used to identify the operand 533/// list for an instruction. outs and ins are identical both syntactically and 534/// semantically; they are used to define def operands and use operands to 535/// improve readibility. This should be used like this: 536/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 537def ops; 538def outs; 539def ins; 540 541/// variable_ops definition - Mark this instruction as taking a variable number 542/// of operands. 543def variable_ops; 544 545 546/// PointerLikeRegClass - Values that are designed to have pointer width are 547/// derived from this. TableGen treats the register class as having a symbolic 548/// type that it doesn't know, and resolves the actual regclass to use by using 549/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 550class PointerLikeRegClass<int Kind> { 551 int RegClassKind = Kind; 552} 553 554 555/// ptr_rc definition - Mark this operand as being a pointer value whose 556/// register class is resolved dynamically via a callback to TargetInstrInfo. 557/// FIXME: We should probably change this to a class which contain a list of 558/// flags. But currently we have but one flag. 559def ptr_rc : PointerLikeRegClass<0>; 560 561/// unknown definition - Mark this operand as being of unknown type, causing 562/// it to be resolved by inference in the context it is used. 563class unknown_class; 564def unknown : unknown_class; 565 566/// AsmOperandClass - Representation for the kinds of operands which the target 567/// specific parser can create and the assembly matcher may need to distinguish. 568/// 569/// Operand classes are used to define the order in which instructions are 570/// matched, to ensure that the instruction which gets matched for any 571/// particular list of operands is deterministic. 572/// 573/// The target specific parser must be able to classify a parsed operand into a 574/// unique class which does not partially overlap with any other classes. It can 575/// match a subset of some other class, in which case the super class field 576/// should be defined. 577class AsmOperandClass { 578 /// The name to use for this class, which should be usable as an enum value. 579 string Name = ?; 580 581 /// The super classes of this operand. 582 list<AsmOperandClass> SuperClasses = []; 583 584 /// The name of the method on the target specific operand to call to test 585 /// whether the operand is an instance of this class. If not set, this will 586 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 587 /// signature should be: 588 /// bool isFoo() const; 589 string PredicateMethod = ?; 590 591 /// The name of the method on the target specific operand to call to add the 592 /// target specific operand to an MCInst. If not set, this will default to 593 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 594 /// signature should be: 595 /// void addFooOperands(MCInst &Inst, unsigned N) const; 596 string RenderMethod = ?; 597 598 /// The name of the method on the target specific operand to call to custom 599 /// handle the operand parsing. This is useful when the operands do not relate 600 /// to immediates or registers and are very instruction specific (as flags to 601 /// set in a processor register, coprocessor number, ...). 602 string ParserMethod = ?; 603 604 // The diagnostic type to present when referencing this operand in a 605 // match failure error message. By default, use a generic "invalid operand" 606 // diagnostic. The target AsmParser maps these codes to text. 607 string DiagnosticType = ""; 608} 609 610def ImmAsmOperand : AsmOperandClass { 611 let Name = "Imm"; 612} 613 614/// Operand Types - These provide the built-in operand types that may be used 615/// by a target. Targets can optionally provide their own operand types as 616/// needed, though this should not be needed for RISC targets. 617class Operand<ValueType ty> : DAGOperand { 618 ValueType Type = ty; 619 string PrintMethod = "printOperand"; 620 string EncoderMethod = ""; 621 string DecoderMethod = ""; 622 bit hasCompleteDecoder = 1; 623 string OperandType = "OPERAND_UNKNOWN"; 624 dag MIOperandInfo = (ops); 625 626 // MCOperandPredicate - Optionally, a code fragment operating on 627 // const MCOperand &MCOp, and returning a bool, to indicate if 628 // the value of MCOp is valid for the specific subclass of Operand 629 code MCOperandPredicate; 630 631 // ParserMatchClass - The "match class" that operands of this type fit 632 // in. Match classes are used to define the order in which instructions are 633 // match, to ensure that which instructions gets matched is deterministic. 634 // 635 // The target specific parser must be able to classify an parsed operand into 636 // a unique class, which does not partially overlap with any other classes. It 637 // can match a subset of some other class, in which case the AsmOperandClass 638 // should declare the other operand as one of its super classes. 639 AsmOperandClass ParserMatchClass = ImmAsmOperand; 640} 641 642class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 643 : DAGOperand { 644 // RegClass - The register class of the operand. 645 RegisterClass RegClass = regclass; 646 // PrintMethod - The target method to call to print register operands of 647 // this type. The method normally will just use an alt-name index to look 648 // up the name to print. Default to the generic printOperand(). 649 string PrintMethod = pm; 650 // ParserMatchClass - The "match class" that operands of this type fit 651 // in. Match classes are used to define the order in which instructions are 652 // match, to ensure that which instructions gets matched is deterministic. 653 // 654 // The target specific parser must be able to classify an parsed operand into 655 // a unique class, which does not partially overlap with any other classes. It 656 // can match a subset of some other class, in which case the AsmOperandClass 657 // should declare the other operand as one of its super classes. 658 AsmOperandClass ParserMatchClass; 659 660 string OperandNamespace = "MCOI"; 661 string OperandType = "OPERAND_REGISTER"; 662} 663 664let OperandType = "OPERAND_IMMEDIATE" in { 665def i1imm : Operand<i1>; 666def i8imm : Operand<i8>; 667def i16imm : Operand<i16>; 668def i32imm : Operand<i32>; 669def i64imm : Operand<i64>; 670 671def f32imm : Operand<f32>; 672def f64imm : Operand<f64>; 673} 674 675/// zero_reg definition - Special node to stand for the zero register. 676/// 677def zero_reg; 678 679/// All operands which the MC layer classifies as predicates should inherit from 680/// this class in some manner. This is already handled for the most commonly 681/// used PredicateOperand, but may be useful in other circumstances. 682class PredicateOp; 683 684/// OperandWithDefaultOps - This Operand class can be used as the parent class 685/// for an Operand that needs to be initialized with a default value if 686/// no value is supplied in a pattern. This class can be used to simplify the 687/// pattern definitions for instructions that have target specific flags 688/// encoded as immediate operands. 689class OperandWithDefaultOps<ValueType ty, dag defaultops> 690 : Operand<ty> { 691 dag DefaultOps = defaultops; 692} 693 694/// PredicateOperand - This can be used to define a predicate operand for an 695/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 696/// AlwaysVal specifies the value of this predicate when set to "always 697/// execute". 698class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 699 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 700 let MIOperandInfo = OpTypes; 701} 702 703/// OptionalDefOperand - This is used to define a optional definition operand 704/// for an instruction. DefaultOps is the register the operand represents if 705/// none is supplied, e.g. zero_reg. 706class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 707 : OperandWithDefaultOps<ty, defaultops> { 708 let MIOperandInfo = OpTypes; 709} 710 711 712// InstrInfo - This class should only be instantiated once to provide parameters 713// which are global to the target machine. 714// 715class InstrInfo { 716 // Target can specify its instructions in either big or little-endian formats. 717 // For instance, while both Sparc and PowerPC are big-endian platforms, the 718 // Sparc manual specifies its instructions in the format [31..0] (big), while 719 // PowerPC specifies them using the format [0..31] (little). 720 bit isLittleEndianEncoding = 0; 721 722 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 723 // by default, and TableGen will infer their value from the instruction 724 // pattern when possible. 725 // 726 // Normally, TableGen will issue an error it it can't infer the value of a 727 // property that hasn't been set explicitly. When guessInstructionProperties 728 // is set, it will guess a safe value instead. 729 // 730 // This option is a temporary migration help. It will go away. 731 bit guessInstructionProperties = 1; 732 733 // TableGen's instruction encoder generator has support for matching operands 734 // to bit-field variables both by name and by position. While matching by 735 // name is preferred, this is currently not possible for complex operands, 736 // and some targets still reply on the positional encoding rules. When 737 // generating a decoder for such targets, the positional encoding rules must 738 // be used by the decoder generator as well. 739 // 740 // This option is temporary; it will go away once the TableGen decoder 741 // generator has better support for complex operands and targets have 742 // migrated away from using positionally encoded operands. 743 bit decodePositionallyEncodedOperands = 0; 744 745 // When set, this indicates that there will be no overlap between those 746 // operands that are matched by ordering (positional operands) and those 747 // matched by name. 748 // 749 // This option is temporary; it will go away once the TableGen decoder 750 // generator has better support for complex operands and targets have 751 // migrated away from using positionally encoded operands. 752 bit noNamedPositionallyEncodedOperands = 0; 753} 754 755// Standard Pseudo Instructions. 756// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 757// Only these instructions are allowed in the TargetOpcode namespace. 758let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 759def PHI : Instruction { 760 let OutOperandList = (outs); 761 let InOperandList = (ins variable_ops); 762 let AsmString = "PHINODE"; 763} 764def INLINEASM : Instruction { 765 let OutOperandList = (outs); 766 let InOperandList = (ins variable_ops); 767 let AsmString = ""; 768 let hasSideEffects = 0; // Note side effect is encoded in an operand. 769} 770def CFI_INSTRUCTION : Instruction { 771 let OutOperandList = (outs); 772 let InOperandList = (ins i32imm:$id); 773 let AsmString = ""; 774 let hasCtrlDep = 1; 775 let isNotDuplicable = 1; 776} 777def EH_LABEL : Instruction { 778 let OutOperandList = (outs); 779 let InOperandList = (ins i32imm:$id); 780 let AsmString = ""; 781 let hasCtrlDep = 1; 782 let isNotDuplicable = 1; 783} 784def GC_LABEL : Instruction { 785 let OutOperandList = (outs); 786 let InOperandList = (ins i32imm:$id); 787 let AsmString = ""; 788 let hasCtrlDep = 1; 789 let isNotDuplicable = 1; 790} 791def KILL : Instruction { 792 let OutOperandList = (outs); 793 let InOperandList = (ins variable_ops); 794 let AsmString = ""; 795 let hasSideEffects = 0; 796} 797def EXTRACT_SUBREG : Instruction { 798 let OutOperandList = (outs unknown:$dst); 799 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 800 let AsmString = ""; 801 let hasSideEffects = 0; 802} 803def INSERT_SUBREG : Instruction { 804 let OutOperandList = (outs unknown:$dst); 805 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 806 let AsmString = ""; 807 let hasSideEffects = 0; 808 let Constraints = "$supersrc = $dst"; 809} 810def IMPLICIT_DEF : Instruction { 811 let OutOperandList = (outs unknown:$dst); 812 let InOperandList = (ins); 813 let AsmString = ""; 814 let hasSideEffects = 0; 815 let isReMaterializable = 1; 816 let isAsCheapAsAMove = 1; 817} 818def SUBREG_TO_REG : Instruction { 819 let OutOperandList = (outs unknown:$dst); 820 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 821 let AsmString = ""; 822 let hasSideEffects = 0; 823} 824def COPY_TO_REGCLASS : Instruction { 825 let OutOperandList = (outs unknown:$dst); 826 let InOperandList = (ins unknown:$src, i32imm:$regclass); 827 let AsmString = ""; 828 let hasSideEffects = 0; 829 let isAsCheapAsAMove = 1; 830} 831def DBG_VALUE : Instruction { 832 let OutOperandList = (outs); 833 let InOperandList = (ins variable_ops); 834 let AsmString = "DBG_VALUE"; 835 let hasSideEffects = 0; 836} 837def REG_SEQUENCE : Instruction { 838 let OutOperandList = (outs unknown:$dst); 839 let InOperandList = (ins unknown:$supersrc, variable_ops); 840 let AsmString = ""; 841 let hasSideEffects = 0; 842 let isAsCheapAsAMove = 1; 843} 844def COPY : Instruction { 845 let OutOperandList = (outs unknown:$dst); 846 let InOperandList = (ins unknown:$src); 847 let AsmString = ""; 848 let hasSideEffects = 0; 849 let isAsCheapAsAMove = 1; 850} 851def BUNDLE : Instruction { 852 let OutOperandList = (outs); 853 let InOperandList = (ins variable_ops); 854 let AsmString = "BUNDLE"; 855} 856def LIFETIME_START : Instruction { 857 let OutOperandList = (outs); 858 let InOperandList = (ins i32imm:$id); 859 let AsmString = "LIFETIME_START"; 860 let hasSideEffects = 0; 861} 862def LIFETIME_END : Instruction { 863 let OutOperandList = (outs); 864 let InOperandList = (ins i32imm:$id); 865 let AsmString = "LIFETIME_END"; 866 let hasSideEffects = 0; 867} 868def STACKMAP : Instruction { 869 let OutOperandList = (outs); 870 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); 871 let isCall = 1; 872 let mayLoad = 1; 873 let usesCustomInserter = 1; 874} 875def PATCHPOINT : Instruction { 876 let OutOperandList = (outs unknown:$dst); 877 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, 878 i32imm:$nargs, i32imm:$cc, variable_ops); 879 let isCall = 1; 880 let mayLoad = 1; 881 let usesCustomInserter = 1; 882} 883def STATEPOINT : Instruction { 884 let OutOperandList = (outs); 885 let InOperandList = (ins variable_ops); 886 let usesCustomInserter = 1; 887 let mayLoad = 1; 888 let mayStore = 1; 889 let hasSideEffects = 1; 890 let isCall = 1; 891} 892def LOAD_STACK_GUARD : Instruction { 893 let OutOperandList = (outs ptr_rc:$dst); 894 let InOperandList = (ins); 895 let mayLoad = 1; 896 bit isReMaterializable = 1; 897 let hasSideEffects = 0; 898 bit isPseudo = 1; 899} 900def LOCAL_ESCAPE : Instruction { 901 // This instruction is really just a label. It has to be part of the chain so 902 // that it doesn't get dropped from the DAG, but it produces nothing and has 903 // no side effects. 904 let OutOperandList = (outs); 905 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id); 906 let hasSideEffects = 0; 907 let hasCtrlDep = 1; 908} 909def FAULTING_LOAD_OP : Instruction { 910 let OutOperandList = (outs unknown:$dst); 911 let InOperandList = (ins variable_ops); 912 let usesCustomInserter = 1; 913 let mayLoad = 1; 914} 915} 916 917//===----------------------------------------------------------------------===// 918// AsmParser - This class can be implemented by targets that wish to implement 919// .s file parsing. 920// 921// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 922// syntax on X86 for example). 923// 924class AsmParser { 925 // AsmParserClassName - This specifies the suffix to use for the asmparser 926 // class. Generated AsmParser classes are always prefixed with the target 927 // name. 928 string AsmParserClassName = "AsmParser"; 929 930 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 931 // function of the AsmParser class to call on every matched instruction. 932 // This can be used to perform target specific instruction post-processing. 933 string AsmParserInstCleanup = ""; 934 935 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 936 // written register name matcher 937 bit ShouldEmitMatchRegisterName = 1; 938 939 /// Does the instruction mnemonic allow '.' 940 bit MnemonicContainsDot = 0; 941} 942def DefaultAsmParser : AsmParser; 943 944//===----------------------------------------------------------------------===// 945// AsmParserVariant - Subtargets can have multiple different assembly parsers 946// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 947// implemented by targets to describe such variants. 948// 949class AsmParserVariant { 950 // Variant - AsmParsers can be of multiple different variants. Variants are 951 // used to support targets that need to parser multiple formats for the 952 // assembly language. 953 int Variant = 0; 954 955 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 956 string Name = ""; 957 958 // CommentDelimiter - If given, the delimiter string used to recognize 959 // comments which are hard coded in the .td assembler strings for individual 960 // instructions. 961 string CommentDelimiter = ""; 962 963 // RegisterPrefix - If given, the token prefix which indicates a register 964 // token. This is used by the matcher to automatically recognize hard coded 965 // register tokens as constrained registers, instead of tokens, for the 966 // purposes of matching. 967 string RegisterPrefix = ""; 968 969 // TokenizingCharacters - Characters that are standalone tokens 970 string TokenizingCharacters = "[]*!"; 971 972 // SeparatorCharacters - Characters that are not tokens 973 string SeparatorCharacters = " \t,"; 974 975 // BreakCharacters - Characters that start new identifiers 976 string BreakCharacters = ""; 977} 978def DefaultAsmParserVariant : AsmParserVariant; 979 980/// AssemblerPredicate - This is a Predicate that can be used when the assembler 981/// matches instructions and aliases. 982class AssemblerPredicate<string cond, string name = ""> { 983 bit AssemblerMatcherPredicate = 1; 984 string AssemblerCondString = cond; 985 string PredicateName = name; 986} 987 988/// TokenAlias - This class allows targets to define assembler token 989/// operand aliases. That is, a token literal operand which is equivalent 990/// to another, canonical, token literal. For example, ARM allows: 991/// vmov.u32 s4, #0 -> vmov.i32, #0 992/// 'u32' is a more specific designator for the 32-bit integer type specifier 993/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 994/// def : TokenAlias<".u32", ".i32">; 995/// 996/// This works by marking the match class of 'From' as a subclass of the 997/// match class of 'To'. 998class TokenAlias<string From, string To> { 999 string FromToken = From; 1000 string ToToken = To; 1001} 1002 1003/// MnemonicAlias - This class allows targets to define assembler mnemonic 1004/// aliases. This should be used when all forms of one mnemonic are accepted 1005/// with a different mnemonic. For example, X86 allows: 1006/// sal %al, 1 -> shl %al, 1 1007/// sal %ax, %cl -> shl %ax, %cl 1008/// sal %eax, %cl -> shl %eax, %cl 1009/// etc. Though "sal" is accepted with many forms, all of them are directly 1010/// translated to a shl, so it can be handled with (in the case of X86, it 1011/// actually has one for each suffix as well): 1012/// def : MnemonicAlias<"sal", "shl">; 1013/// 1014/// Mnemonic aliases are mapped before any other translation in the match phase, 1015/// and do allow Requires predicates, e.g.: 1016/// 1017/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1018/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1019/// 1020/// Mnemonic aliases can also be constrained to specific variants, e.g.: 1021/// 1022/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 1023/// 1024/// If no variant (e.g., "att" or "intel") is specified then the alias is 1025/// applied unconditionally. 1026class MnemonicAlias<string From, string To, string VariantName = ""> { 1027 string FromMnemonic = From; 1028 string ToMnemonic = To; 1029 string AsmVariantName = VariantName; 1030 1031 // Predicates - Predicates that must be true for this remapping to happen. 1032 list<Predicate> Predicates = []; 1033} 1034 1035/// InstAlias - This defines an alternate assembly syntax that is allowed to 1036/// match an instruction that has a different (more canonical) assembly 1037/// representation. 1038class InstAlias<string Asm, dag Result, int Emit = 1> { 1039 string AsmString = Asm; // The .s format to match the instruction with. 1040 dag ResultInst = Result; // The MCInst to generate. 1041 1042 // This determines which order the InstPrinter detects aliases for 1043 // printing. A larger value makes the alias more likely to be 1044 // emitted. The Instruction's own definition is notionally 0.5, so 0 1045 // disables printing and 1 enables it if there are no conflicting aliases. 1046 int EmitPriority = Emit; 1047 1048 // Predicates - Predicates that must be true for this to match. 1049 list<Predicate> Predicates = []; 1050 1051 // If the instruction specified in Result has defined an AsmMatchConverter 1052 // then setting this to 1 will cause the alias to use the AsmMatchConverter 1053 // function when converting the OperandVector into an MCInst instead of the 1054 // function that is generated by the dag Result. 1055 // Setting this to 0 will cause the alias to ignore the Result instruction's 1056 // defined AsmMatchConverter and instead use the function generated by the 1057 // dag Result. 1058 bit UseInstAsmMatchConverter = 1; 1059} 1060 1061//===----------------------------------------------------------------------===// 1062// AsmWriter - This class can be implemented by targets that need to customize 1063// the format of the .s file writer. 1064// 1065// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 1066// on X86 for example). 1067// 1068class AsmWriter { 1069 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 1070 // class. Generated AsmWriter classes are always prefixed with the target 1071 // name. 1072 string AsmWriterClassName = "InstPrinter"; 1073 1074 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to 1075 // the various print methods. 1076 // FIXME: Remove after all ports are updated. 1077 int PassSubtarget = 0; 1078 1079 // Variant - AsmWriters can be of multiple different variants. Variants are 1080 // used to support targets that need to emit assembly code in ways that are 1081 // mostly the same for different targets, but have minor differences in 1082 // syntax. If the asmstring contains {|} characters in them, this integer 1083 // will specify which alternative to use. For example "{x|y|z}" with Variant 1084 // == 1, will expand to "y". 1085 int Variant = 0; 1086} 1087def DefaultAsmWriter : AsmWriter; 1088 1089 1090//===----------------------------------------------------------------------===// 1091// Target - This class contains the "global" target information 1092// 1093class Target { 1094 // InstructionSet - Instruction set description for this target. 1095 InstrInfo InstructionSet; 1096 1097 // AssemblyParsers - The AsmParser instances available for this target. 1098 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 1099 1100 /// AssemblyParserVariants - The AsmParserVariant instances available for 1101 /// this target. 1102 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 1103 1104 // AssemblyWriters - The AsmWriter instances available for this target. 1105 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 1106} 1107 1108//===----------------------------------------------------------------------===// 1109// SubtargetFeature - A characteristic of the chip set. 1110// 1111class SubtargetFeature<string n, string a, string v, string d, 1112 list<SubtargetFeature> i = []> { 1113 // Name - Feature name. Used by command line (-mattr=) to determine the 1114 // appropriate target chip. 1115 // 1116 string Name = n; 1117 1118 // Attribute - Attribute to be set by feature. 1119 // 1120 string Attribute = a; 1121 1122 // Value - Value the attribute to be set to by feature. 1123 // 1124 string Value = v; 1125 1126 // Desc - Feature description. Used by command line (-mattr=) to display help 1127 // information. 1128 // 1129 string Desc = d; 1130 1131 // Implies - Features that this feature implies are present. If one of those 1132 // features isn't set, then this one shouldn't be set either. 1133 // 1134 list<SubtargetFeature> Implies = i; 1135} 1136 1137/// Specifies a Subtarget feature that this instruction is deprecated on. 1138class Deprecated<SubtargetFeature dep> { 1139 SubtargetFeature DeprecatedFeatureMask = dep; 1140} 1141 1142/// A custom predicate used to determine if an instruction is 1143/// deprecated or not. 1144class ComplexDeprecationPredicate<string dep> { 1145 string ComplexDeprecationPredicate = dep; 1146} 1147 1148//===----------------------------------------------------------------------===// 1149// Processor chip sets - These values represent each of the chip sets supported 1150// by the scheduler. Each Processor definition requires corresponding 1151// instruction itineraries. 1152// 1153class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 1154 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1155 // appropriate target chip. 1156 // 1157 string Name = n; 1158 1159 // SchedModel - The machine model for scheduling and instruction cost. 1160 // 1161 SchedMachineModel SchedModel = NoSchedModel; 1162 1163 // ProcItin - The scheduling information for the target processor. 1164 // 1165 ProcessorItineraries ProcItin = pi; 1166 1167 // Features - list of 1168 list<SubtargetFeature> Features = f; 1169} 1170 1171// ProcessorModel allows subtargets to specify the more general 1172// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1173// gradually move to this newer form. 1174// 1175// Although this class always passes NoItineraries to the Processor 1176// class, the SchedMachineModel may still define valid Itineraries. 1177class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> 1178 : Processor<n, NoItineraries, f> { 1179 let SchedModel = m; 1180} 1181 1182//===----------------------------------------------------------------------===// 1183// InstrMapping - This class is used to create mapping tables to relate 1184// instructions with each other based on the values specified in RowFields, 1185// ColFields, KeyCol and ValueCols. 1186// 1187class InstrMapping { 1188 // FilterClass - Used to limit search space only to the instructions that 1189 // define the relationship modeled by this InstrMapping record. 1190 string FilterClass; 1191 1192 // RowFields - List of fields/attributes that should be same for all the 1193 // instructions in a row of the relation table. Think of this as a set of 1194 // properties shared by all the instructions related by this relationship 1195 // model and is used to categorize instructions into subgroups. For instance, 1196 // if we want to define a relation that maps 'Add' instruction to its 1197 // predicated forms, we can define RowFields like this: 1198 // 1199 // let RowFields = BaseOp 1200 // All add instruction predicated/non-predicated will have to set their BaseOp 1201 // to the same value. 1202 // 1203 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1204 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1205 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1206 list<string> RowFields = []; 1207 1208 // List of fields/attributes that are same for all the instructions 1209 // in a column of the relation table. 1210 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1211 // based on the 'predSense' values. All the instruction in a specific 1212 // column have the same value and it is fixed for the column according 1213 // to the values set in 'ValueCols'. 1214 list<string> ColFields = []; 1215 1216 // Values for the fields/attributes listed in 'ColFields'. 1217 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1218 // that models this relation) should be non-predicated. 1219 // In the example above, 'Add' is the key instruction. 1220 list<string> KeyCol = []; 1221 1222 // List of values for the fields/attributes listed in 'ColFields', one for 1223 // each column in the relation table. 1224 // 1225 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1226 // table. First column requires all the instructions to have predSense 1227 // set to 'true' and second column requires it to be 'false'. 1228 list<list<string> > ValueCols = []; 1229} 1230 1231//===----------------------------------------------------------------------===// 1232// Pull in the common support for calling conventions. 1233// 1234include "llvm/Target/TargetCallingConv.td" 1235 1236//===----------------------------------------------------------------------===// 1237// Pull in the common support for DAG isel generation. 1238// 1239include "llvm/Target/TargetSelectionDAG.td" 1240