TargetLowering.h revision 06f5ebc5a1604b01689cf2d482dd05f956538af6
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/ADT/DenseMap.h" 26#include "llvm/CodeGen/DAGCombine.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/CodeGen/SelectionDAGNodes.h" 29#include "llvm/IR/Attributes.h" 30#include "llvm/IR/CallingConv.h" 31#include "llvm/IR/InlineAsm.h" 32#include "llvm/Support/CallSite.h" 33#include "llvm/Target/TargetCallingConv.h" 34#include "llvm/Target/TargetMachine.h" 35#include <climits> 36#include <map> 37#include <vector> 38 39namespace llvm { 40 class CallInst; 41 class CCState; 42 class FastISel; 43 class FunctionLoweringInfo; 44 class ImmutableCallSite; 45 class IntrinsicInst; 46 class MachineBasicBlock; 47 class MachineFunction; 48 class MachineInstr; 49 class MachineJumpTableInfo; 50 class MCContext; 51 class MCExpr; 52 template<typename T> class SmallVectorImpl; 53 class DataLayout; 54 class TargetRegisterClass; 55 class TargetLibraryInfo; 56 class TargetLoweringObjectFile; 57 class Value; 58 59 namespace Sched { 60 enum Preference { 61 None, // No preference 62 Source, // Follow source order. 63 RegPressure, // Scheduling for lowest register pressure. 64 Hybrid, // Scheduling for both latency and register pressure. 65 ILP, // Scheduling for ILP in low register pressure mode. 66 VLIW // Scheduling for VLIW targets. 67 }; 68 } 69 70/// TargetLoweringBase - This base class for TargetLowering contains the 71/// SelectionDAG-independent parts that can be used from the rest of CodeGen. 72class TargetLoweringBase { 73 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 74 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 75 76public: 77 /// LegalizeAction - This enum indicates whether operations are valid for a 78 /// target, and if not, what action should be used to make them valid. 79 enum LegalizeAction { 80 Legal, // The target natively supports this operation. 81 Promote, // This operation should be executed in a larger type. 82 Expand, // Try to expand this to other ops, otherwise use a libcall. 83 Custom // Use the LowerOperation hook to implement custom lowering. 84 }; 85 86 /// LegalizeTypeAction - This enum indicates whether a types are legal for a 87 /// target, and if not, what action should be used to make them valid. 88 enum LegalizeTypeAction { 89 TypeLegal, // The target natively supports this type. 90 TypePromoteInteger, // Replace this integer with a larger one. 91 TypeExpandInteger, // Split this integer into two of half the size. 92 TypeSoftenFloat, // Convert this float to a same size integer type. 93 TypeExpandFloat, // Split this float into two of half the size. 94 TypeScalarizeVector, // Replace this one-element vector with its element. 95 TypeSplitVector, // Split this vector into two of half the size. 96 TypeWidenVector // This vector should be widened into a larger vector. 97 }; 98 99 /// LegalizeKind holds the legalization kind that needs to happen to EVT 100 /// in order to type-legalize it. 101 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; 102 103 enum BooleanContent { // How the target represents true/false values. 104 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 105 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 106 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 107 }; 108 109 enum SelectSupportKind { 110 ScalarValSelect, // The target supports scalar selects (ex: cmov). 111 ScalarCondVectorVal, // The target supports selects with a scalar condition 112 // and vector values (ex: cmov). 113 VectorMaskSelect // The target supports vector selects with a vector 114 // mask (ex: x86 blends). 115 }; 116 117 static ISD::NodeType getExtendForContent(BooleanContent Content) { 118 switch (Content) { 119 case UndefinedBooleanContent: 120 // Extend by adding rubbish bits. 121 return ISD::ANY_EXTEND; 122 case ZeroOrOneBooleanContent: 123 // Extend by adding zero bits. 124 return ISD::ZERO_EXTEND; 125 case ZeroOrNegativeOneBooleanContent: 126 // Extend by copying the sign bit. 127 return ISD::SIGN_EXTEND; 128 } 129 llvm_unreachable("Invalid content kind"); 130 } 131 132 /// NOTE: The constructor takes ownership of TLOF. 133 explicit TargetLoweringBase(const TargetMachine &TM, 134 const TargetLoweringObjectFile *TLOF); 135 virtual ~TargetLoweringBase(); 136 137protected: 138 /// \brief Initialize all of the actions to default values. 139 void initActions(); 140 141public: 142 const TargetMachine &getTargetMachine() const { return TM; } 143 const DataLayout *getDataLayout() const { return TD; } 144 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 145 146 bool isBigEndian() const { return !IsLittleEndian; } 147 bool isLittleEndian() const { return IsLittleEndian; } 148 // Return the pointer type for the given address space, defaults to 149 // the pointer type from the data layout. 150 // FIXME: The default needs to be removed once all the code is updated. 151 virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; } 152 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const; 153 154 EVT getShiftAmountTy(EVT LHSTy) const; 155 156 /// isSelectExpensive - Return true if the select operation is expensive for 157 /// this target. 158 bool isSelectExpensive() const { return SelectIsExpensive; } 159 160 virtual bool isSelectSupported(SelectSupportKind kind) const { return true; } 161 162 /// shouldSplitVectorElementType - Return true if a vector of the given type 163 /// should be split (TypeSplitVector) instead of promoted 164 /// (TypePromoteInteger) during type legalization. 165 virtual bool shouldSplitVectorElementType(EVT VT) const { return false; } 166 167 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 168 /// a sequence of several shifts, adds, and multiplies for this target. 169 bool isIntDivCheap() const { return IntDivIsCheap; } 170 171 /// isSlowDivBypassed - Returns true if target has indicated at least one 172 /// type should be bypassed. 173 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } 174 175 /// getBypassSlowDivTypes - Returns map of slow types for division or 176 /// remainder with corresponding fast types 177 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { 178 return BypassSlowDivWidths; 179 } 180 181 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 182 /// srl/add/sra. 183 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 184 185 /// isJumpExpensive() - Return true if Flow Control is an expensive operation 186 /// that should be avoided. 187 bool isJumpExpensive() const { return JumpIsExpensive; } 188 189 /// isPredictableSelectExpensive - Return true if selects are only cheaper 190 /// than branches if the branch is unlikely to be predicted right. 191 bool isPredictableSelectExpensive() const { 192 return PredictableSelectIsExpensive; 193 } 194 195 /// getSetCCResultType - Return the ValueType of the result of SETCC 196 /// operations. Also used to obtain the target's preferred type for 197 /// the condition operand of SELECT and BRCOND nodes. In the case of 198 /// BRCOND the argument passed is MVT::Other since there are no other 199 /// operands to get a type hint from. 200 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 201 202 /// getCmpLibcallReturnType - Return the ValueType for comparison 203 /// libcalls. Comparions libcalls include floating point comparion calls, 204 /// and Ordered/Unordered check calls on floating point numbers. 205 virtual 206 MVT::SimpleValueType getCmpLibcallReturnType() const; 207 208 /// getBooleanContents - For targets without i1 registers, this gives the 209 /// nature of the high-bits of boolean values held in types wider than i1. 210 /// "Boolean values" are special true/false values produced by nodes like 211 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 212 /// Not to be confused with general values promoted from i1. 213 /// Some cpus distinguish between vectors of boolean and scalars; the isVec 214 /// parameter selects between the two kinds. For example on X86 a scalar 215 /// boolean should be zero extended from i1, while the elements of a vector 216 /// of booleans should be sign extended from i1. 217 BooleanContent getBooleanContents(bool isVec) const { 218 return isVec ? BooleanVectorContents : BooleanContents; 219 } 220 221 /// getSchedulingPreference - Return target scheduling preference. 222 Sched::Preference getSchedulingPreference() const { 223 return SchedPreferenceInfo; 224 } 225 226 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 227 /// different scheduling heuristics for different nodes. This function returns 228 /// the preference (or none) for the given node. 229 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 230 return Sched::None; 231 } 232 233 /// getRegClassFor - Return the register class that should be used for the 234 /// specified value type. 235 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { 236 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 237 assert(RC && "This value type is not natively supported!"); 238 return RC; 239 } 240 241 /// getRepRegClassFor - Return the 'representative' register class for the 242 /// specified value type. The 'representative' register class is the largest 243 /// legal super-reg register class for the register class of the value type. 244 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 245 /// while the rep register class is GR64 on x86_64. 246 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 247 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; 248 return RC; 249 } 250 251 /// getRepRegClassCostFor - Return the cost of the 'representative' register 252 /// class for the specified value type. 253 virtual uint8_t getRepRegClassCostFor(MVT VT) const { 254 return RepRegClassCostForVT[VT.SimpleTy]; 255 } 256 257 /// isTypeLegal - Return true if the target has native support for the 258 /// specified value type. This means that it has a register that directly 259 /// holds it without promotions or expansions. 260 bool isTypeLegal(EVT VT) const { 261 assert(!VT.isSimple() || 262 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 263 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 264 } 265 266 class ValueTypeActionImpl { 267 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 268 /// that indicates how instruction selection should deal with the type. 269 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 270 271 public: 272 ValueTypeActionImpl() { 273 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 274 } 275 276 LegalizeTypeAction getTypeAction(MVT VT) const { 277 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; 278 } 279 280 void setTypeAction(MVT VT, LegalizeTypeAction Action) { 281 unsigned I = VT.SimpleTy; 282 ValueTypeActions[I] = Action; 283 } 284 }; 285 286 const ValueTypeActionImpl &getValueTypeActions() const { 287 return ValueTypeActions; 288 } 289 290 /// getTypeAction - Return how we should legalize values of this type, either 291 /// it is already legal (return 'Legal') or we need to promote it to a larger 292 /// type (return 'Promote'), or we need to expand it into multiple registers 293 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 294 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 295 return getTypeConversion(Context, VT).first; 296 } 297 LegalizeTypeAction getTypeAction(MVT VT) const { 298 return ValueTypeActions.getTypeAction(VT); 299 } 300 301 /// getTypeToTransformTo - For types supported by the target, this is an 302 /// identity function. For types that must be promoted to larger types, this 303 /// returns the larger type to promote to. For integer types that are larger 304 /// than the largest integer register, this contains one step in the expansion 305 /// to get to the smaller register. For illegal floating point types, this 306 /// returns the integer type to transform to. 307 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 308 return getTypeConversion(Context, VT).second; 309 } 310 311 /// getTypeToExpandTo - For types supported by the target, this is an 312 /// identity function. For types that must be expanded (i.e. integer types 313 /// that are larger than the largest integer register or illegal floating 314 /// point types), this returns the largest legal type it will be expanded to. 315 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 316 assert(!VT.isVector()); 317 while (true) { 318 switch (getTypeAction(Context, VT)) { 319 case TypeLegal: 320 return VT; 321 case TypeExpandInteger: 322 VT = getTypeToTransformTo(Context, VT); 323 break; 324 default: 325 llvm_unreachable("Type is not legal nor is it to be expanded!"); 326 } 327 } 328 } 329 330 /// getVectorTypeBreakdown - Vector types are broken down into some number of 331 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 332 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 333 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 334 /// 335 /// This method returns the number of registers needed, and the VT for each 336 /// register. It also returns the VT and quantity of the intermediate values 337 /// before they are promoted/expanded. 338 /// 339 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 340 EVT &IntermediateVT, 341 unsigned &NumIntermediates, 342 MVT &RegisterVT) const; 343 344 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 345 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 346 /// this is the case, it returns true and store the intrinsic 347 /// information into the IntrinsicInfo that was passed to the function. 348 struct IntrinsicInfo { 349 unsigned opc; // target opcode 350 EVT memVT; // memory VT 351 const Value* ptrVal; // value representing memory location 352 int offset; // offset off of ptrVal 353 unsigned align; // alignment 354 bool vol; // is volatile? 355 bool readMem; // reads memory? 356 bool writeMem; // writes memory? 357 }; 358 359 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 360 unsigned /*Intrinsic*/) const { 361 return false; 362 } 363 364 /// isFPImmLegal - Returns true if the target can instruction select the 365 /// specified FP immediate natively. If false, the legalizer will materialize 366 /// the FP immediate as a load from a constant pool. 367 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { 368 return false; 369 } 370 371 /// isShuffleMaskLegal - Targets can use this to indicate that they only 372 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 373 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 374 /// are assumed to be legal. 375 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 376 EVT /*VT*/) const { 377 return true; 378 } 379 380 /// canOpTrap - Returns true if the operation can trap for the value type. 381 /// VT must be a legal type. By default, we optimistically assume most 382 /// operations don't trap except for divide and remainder. 383 virtual bool canOpTrap(unsigned Op, EVT VT) const; 384 385 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 386 /// used by Targets can use this to indicate if there is a suitable 387 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 388 /// pool entry. 389 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 390 EVT /*VT*/) const { 391 return false; 392 } 393 394 /// getOperationAction - Return how this operation should be treated: either 395 /// it is legal, needs to be promoted to a larger size, needs to be 396 /// expanded to some other code sequence, or the target has a custom expander 397 /// for it. 398 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 399 if (VT.isExtended()) return Expand; 400 // If a target-specific SDNode requires legalization, require the target 401 // to provide custom legalization for it. 402 if (Op > array_lengthof(OpActions[0])) return Custom; 403 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 404 return (LegalizeAction)OpActions[I][Op]; 405 } 406 407 /// isOperationLegalOrCustom - Return true if the specified operation is 408 /// legal on this target or can be made legal with custom lowering. This 409 /// is used to help guide high-level lowering decisions. 410 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 411 return (VT == MVT::Other || isTypeLegal(VT)) && 412 (getOperationAction(Op, VT) == Legal || 413 getOperationAction(Op, VT) == Custom); 414 } 415 416 /// isOperationLegalOrPromote - Return true if the specified operation is 417 /// legal on this target or can be made legal using promotion. This 418 /// is used to help guide high-level lowering decisions. 419 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const { 420 return (VT == MVT::Other || isTypeLegal(VT)) && 421 (getOperationAction(Op, VT) == Legal || 422 getOperationAction(Op, VT) == Promote); 423 } 424 425 /// isOperationExpand - Return true if the specified operation is illegal on 426 /// this target or unlikely to be made legal with custom lowering. This is 427 /// used to help guide high-level lowering decisions. 428 bool isOperationExpand(unsigned Op, EVT VT) const { 429 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); 430 } 431 432 /// isOperationLegal - Return true if the specified operation is legal on this 433 /// target. 434 bool isOperationLegal(unsigned Op, EVT VT) const { 435 return (VT == MVT::Other || isTypeLegal(VT)) && 436 getOperationAction(Op, VT) == Legal; 437 } 438 439 /// getLoadExtAction - Return how this load with extension should be treated: 440 /// either it is legal, needs to be promoted to a larger size, needs to be 441 /// expanded to some other code sequence, or the target has a custom expander 442 /// for it. 443 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const { 444 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 445 "Table isn't big enough!"); 446 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType]; 447 } 448 449 /// isLoadExtLegal - Return true if the specified load with extension is legal 450 /// on this target. 451 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 452 return VT.isSimple() && 453 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal; 454 } 455 456 /// getTruncStoreAction - Return how this store with truncation should be 457 /// treated: either it is legal, needs to be promoted to a larger size, needs 458 /// to be expanded to some other code sequence, or the target has a custom 459 /// expander for it. 460 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const { 461 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 462 "Table isn't big enough!"); 463 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy] 464 [MemVT.SimpleTy]; 465 } 466 467 /// isTruncStoreLegal - Return true if the specified store with truncation is 468 /// legal on this target. 469 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 470 return isTypeLegal(ValVT) && MemVT.isSimple() && 471 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal; 472 } 473 474 /// getIndexedLoadAction - Return how the indexed load should be treated: 475 /// either it is legal, needs to be promoted to a larger size, needs to be 476 /// expanded to some other code sequence, or the target has a custom expander 477 /// for it. 478 LegalizeAction 479 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 480 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 481 "Table isn't big enough!"); 482 unsigned Ty = (unsigned)VT.SimpleTy; 483 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 484 } 485 486 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 487 /// on this target. 488 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 489 return VT.isSimple() && 490 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || 491 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); 492 } 493 494 /// getIndexedStoreAction - Return how the indexed store should be treated: 495 /// either it is legal, needs to be promoted to a larger size, needs to be 496 /// expanded to some other code sequence, or the target has a custom expander 497 /// for it. 498 LegalizeAction 499 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 500 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 501 "Table isn't big enough!"); 502 unsigned Ty = (unsigned)VT.SimpleTy; 503 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 504 } 505 506 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 507 /// on this target. 508 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 509 return VT.isSimple() && 510 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || 511 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); 512 } 513 514 /// getCondCodeAction - Return how the condition code should be treated: 515 /// either it is legal, needs to be expanded to some other code sequence, 516 /// or the target has a custom expander for it. 517 LegalizeAction 518 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 519 assert((unsigned)CC < array_lengthof(CondCodeActions) && 520 (unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 && 521 "Table isn't big enough!"); 522 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 523 /// value and the upper 27 bits index into the second dimension of the 524 /// array to select what 64bit value to use. 525 LegalizeAction Action = (LegalizeAction) 526 ((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F))) & 3); 527 assert(Action != Promote && "Can't promote condition code!"); 528 return Action; 529 } 530 531 /// isCondCodeLegal - Return true if the specified condition code is legal 532 /// on this target. 533 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 534 return 535 getCondCodeAction(CC, VT) == Legal || 536 getCondCodeAction(CC, VT) == Custom; 537 } 538 539 540 /// getTypeToPromoteTo - If the action for this operation is to promote, this 541 /// method returns the ValueType to promote to. 542 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 543 assert(getOperationAction(Op, VT) == Promote && 544 "This operation isn't promoted!"); 545 546 // See if this has an explicit type specified. 547 std::map<std::pair<unsigned, MVT::SimpleValueType>, 548 MVT::SimpleValueType>::const_iterator PTTI = 549 PromoteToType.find(std::make_pair(Op, VT.SimpleTy)); 550 if (PTTI != PromoteToType.end()) return PTTI->second; 551 552 assert((VT.isInteger() || VT.isFloatingPoint()) && 553 "Cannot autopromote this type, add it with AddPromotedToType."); 554 555 MVT NVT = VT; 556 do { 557 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1); 558 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 559 "Didn't find type to promote to!"); 560 } while (!isTypeLegal(NVT) || 561 getOperationAction(Op, NVT) == Promote); 562 return NVT; 563 } 564 565 /// getValueType - Return the EVT corresponding to this LLVM type. 566 /// This is fixed by the LLVM operations except for the pointer size. If 567 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 568 /// counterpart (e.g. structs), otherwise it will assert. 569 EVT getValueType(Type *Ty, bool AllowUnknown = false) const { 570 // Lower scalar pointers to native pointer types. 571 if (Ty->isPointerTy()) return PointerTy; 572 573 if (Ty->isVectorTy()) { 574 VectorType *VTy = cast<VectorType>(Ty); 575 Type *Elm = VTy->getElementType(); 576 // Lower vectors of pointers to native pointer types. 577 if (Elm->isPointerTy()) 578 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext()); 579 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), 580 VTy->getNumElements()); 581 } 582 return EVT::getEVT(Ty, AllowUnknown); 583 } 584 585 /// Return the MVT corresponding to this LLVM type. See getValueType. 586 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const { 587 return getValueType(Ty, AllowUnknown).getSimpleVT(); 588 } 589 590 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 591 /// function arguments in the caller parameter area. This is the actual 592 /// alignment, not its logarithm. 593 virtual unsigned getByValTypeAlignment(Type *Ty) const; 594 595 /// getRegisterType - Return the type of registers that this ValueType will 596 /// eventually require. 597 MVT getRegisterType(MVT VT) const { 598 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 599 return RegisterTypeForVT[VT.SimpleTy]; 600 } 601 602 /// getRegisterType - Return the type of registers that this ValueType will 603 /// eventually require. 604 MVT getRegisterType(LLVMContext &Context, EVT VT) const { 605 if (VT.isSimple()) { 606 assert((unsigned)VT.getSimpleVT().SimpleTy < 607 array_lengthof(RegisterTypeForVT)); 608 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 609 } 610 if (VT.isVector()) { 611 EVT VT1; 612 MVT RegisterVT; 613 unsigned NumIntermediates; 614 (void)getVectorTypeBreakdown(Context, VT, VT1, 615 NumIntermediates, RegisterVT); 616 return RegisterVT; 617 } 618 if (VT.isInteger()) { 619 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 620 } 621 llvm_unreachable("Unsupported extended type!"); 622 } 623 624 /// getNumRegisters - Return the number of registers that this ValueType will 625 /// eventually require. This is one for any types promoted to live in larger 626 /// registers, but may be more than one for types (like i64) that are split 627 /// into pieces. For types like i140, which are first promoted then expanded, 628 /// it is the number of registers needed to hold all the bits of the original 629 /// type. For an i140 on a 32 bit machine this means 5 registers. 630 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 631 if (VT.isSimple()) { 632 assert((unsigned)VT.getSimpleVT().SimpleTy < 633 array_lengthof(NumRegistersForVT)); 634 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 635 } 636 if (VT.isVector()) { 637 EVT VT1; 638 MVT VT2; 639 unsigned NumIntermediates; 640 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 641 } 642 if (VT.isInteger()) { 643 unsigned BitWidth = VT.getSizeInBits(); 644 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 645 return (BitWidth + RegWidth - 1) / RegWidth; 646 } 647 llvm_unreachable("Unsupported extended type!"); 648 } 649 650 /// ShouldShrinkFPConstant - If true, then instruction selection should 651 /// seek to shrink the FP constant of the specified type to a smaller type 652 /// in order to save space and / or reduce runtime. 653 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 654 655 /// hasTargetDAGCombine - If true, the target has custom DAG combine 656 /// transformations that it can perform for the specified node. 657 bool hasTargetDAGCombine(ISD::NodeType NT) const { 658 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 659 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 660 } 661 662 /// This function returns the maximum number of store operations permitted 663 /// to replace a call to llvm.memset. The value is set by the target at the 664 /// performance threshold for such a replacement. If OptSize is true, 665 /// return the limit for functions that have OptSize attribute. 666 /// @brief Get maximum # of store operations permitted for llvm.memset 667 unsigned getMaxStoresPerMemset(bool OptSize) const { 668 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset; 669 } 670 671 /// This function returns the maximum number of store operations permitted 672 /// to replace a call to llvm.memcpy. The value is set by the target at the 673 /// performance threshold for such a replacement. If OptSize is true, 674 /// return the limit for functions that have OptSize attribute. 675 /// @brief Get maximum # of store operations permitted for llvm.memcpy 676 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 677 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy; 678 } 679 680 /// This function returns the maximum number of store operations permitted 681 /// to replace a call to llvm.memmove. The value is set by the target at the 682 /// performance threshold for such a replacement. If OptSize is true, 683 /// return the limit for functions that have OptSize attribute. 684 /// @brief Get maximum # of store operations permitted for llvm.memmove 685 unsigned getMaxStoresPerMemmove(bool OptSize) const { 686 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove; 687 } 688 689 /// This function returns true if the target allows unaligned memory accesses. 690 /// of the specified type. If true, it also returns whether the unaligned 691 /// memory access is "fast" in the second argument by reference. This is used, 692 /// for example, in situations where an array copy/move/set is converted to a 693 /// sequence of store operations. It's use helps to ensure that such 694 /// replacements don't generate code that causes an alignment error (trap) on 695 /// the target machine. 696 /// @brief Determine if the target supports unaligned memory accesses. 697 virtual bool allowsUnalignedMemoryAccesses(EVT, bool *Fast = 0) const { 698 return false; 699 } 700 701 /// getOptimalMemOpType - Returns the target specific optimal type for load 702 /// and store operations as a result of memset, memcpy, and memmove 703 /// lowering. If DstAlign is zero that means it's safe to destination 704 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 705 /// means there isn't a need to check it against alignment requirement, 706 /// probably because the source does not need to be loaded. If 'IsMemset' is 707 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 708 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 709 /// source is constant so it does not need to be loaded. 710 /// It returns EVT::Other if the type should be determined using generic 711 /// target-independent logic. 712 virtual EVT getOptimalMemOpType(uint64_t /*Size*/, 713 unsigned /*DstAlign*/, unsigned /*SrcAlign*/, 714 bool /*IsMemset*/, 715 bool /*ZeroMemset*/, 716 bool /*MemcpyStrSrc*/, 717 MachineFunction &/*MF*/) const { 718 return MVT::Other; 719 } 720 721 /// isSafeMemOpType - Returns true if it's safe to use load / store of the 722 /// specified type to expand memcpy / memset inline. This is mostly true 723 /// for all types except for some special cases. For example, on X86 724 /// targets without SSE2 f64 load / store are done with fldl / fstpl which 725 /// also does type conversion. Note the specified type doesn't have to be 726 /// legal as the hook is used before type legalization. 727 virtual bool isSafeMemOpType(MVT VT) const { 728 return true; 729 } 730 731 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 732 /// to implement llvm.setjmp. 733 bool usesUnderscoreSetJmp() const { 734 return UseUnderscoreSetJmp; 735 } 736 737 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 738 /// to implement llvm.longjmp. 739 bool usesUnderscoreLongJmp() const { 740 return UseUnderscoreLongJmp; 741 } 742 743 /// supportJumpTables - return whether the target can generate code for 744 /// jump tables. 745 bool supportJumpTables() const { 746 return SupportJumpTables; 747 } 748 749 /// getMinimumJumpTableEntries - return integer threshold on number of 750 /// blocks to use jump tables rather than if sequence. 751 int getMinimumJumpTableEntries() const { 752 return MinimumJumpTableEntries; 753 } 754 755 /// getStackPointerRegisterToSaveRestore - If a physical register, this 756 /// specifies the register that llvm.savestack/llvm.restorestack should save 757 /// and restore. 758 unsigned getStackPointerRegisterToSaveRestore() const { 759 return StackPointerRegisterToSaveRestore; 760 } 761 762 /// getExceptionPointerRegister - If a physical register, this returns 763 /// the register that receives the exception address on entry to a landing 764 /// pad. 765 unsigned getExceptionPointerRegister() const { 766 return ExceptionPointerRegister; 767 } 768 769 /// getExceptionSelectorRegister - If a physical register, this returns 770 /// the register that receives the exception typeid on entry to a landing 771 /// pad. 772 unsigned getExceptionSelectorRegister() const { 773 return ExceptionSelectorRegister; 774 } 775 776 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 777 /// set, the default is 200) 778 unsigned getJumpBufSize() const { 779 return JumpBufSize; 780 } 781 782 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 783 /// (if never set, the default is 0) 784 unsigned getJumpBufAlignment() const { 785 return JumpBufAlignment; 786 } 787 788 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 789 /// argument. 790 unsigned getMinStackArgumentAlignment() const { 791 return MinStackArgumentAlignment; 792 } 793 794 /// getMinFunctionAlignment - return the minimum function alignment. 795 /// 796 unsigned getMinFunctionAlignment() const { 797 return MinFunctionAlignment; 798 } 799 800 /// getPrefFunctionAlignment - return the preferred function alignment. 801 /// 802 unsigned getPrefFunctionAlignment() const { 803 return PrefFunctionAlignment; 804 } 805 806 /// getPrefLoopAlignment - return the preferred loop alignment. 807 /// 808 unsigned getPrefLoopAlignment() const { 809 return PrefLoopAlignment; 810 } 811 812 /// getInsertFencesFor - return whether the DAG builder should automatically 813 /// insert fences and reduce ordering for atomics. 814 /// 815 bool getInsertFencesForAtomic() const { 816 return InsertFencesForAtomic; 817 } 818 819 /// getStackCookieLocation - Return true if the target stores stack 820 /// protector cookies at a fixed offset in some non-standard address 821 /// space, and populates the address space and offset as 822 /// appropriate. 823 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, 824 unsigned &/*Offset*/) const { 825 return false; 826 } 827 828 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 829 /// used for loads / stores from the global. 830 virtual unsigned getMaximalGlobalOffset() const { 831 return 0; 832 } 833 834 //===--------------------------------------------------------------------===// 835 /// \name Helpers for TargetTransformInfo implementations 836 /// @{ 837 838 /// Get the ISD node that corresponds to the Instruction class opcode. 839 int InstructionOpcodeToISD(unsigned Opcode) const; 840 841 /// Estimate the cost of type-legalization and the legalized type. 842 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const; 843 844 /// @} 845 846 //===--------------------------------------------------------------------===// 847 // TargetLowering Configuration Methods - These methods should be invoked by 848 // the derived class constructor to configure this object for the target. 849 // 850 851 /// \brief Reset the operation actions based on target options. 852 virtual void resetOperationActions() {} 853 854protected: 855 /// setBooleanContents - Specify how the target extends the result of a 856 /// boolean value from i1 to a wider type. See getBooleanContents. 857 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 858 /// setBooleanVectorContents - Specify how the target extends the result 859 /// of a vector boolean value from a vector of i1 to a wider type. See 860 /// getBooleanContents. 861 void setBooleanVectorContents(BooleanContent Ty) { 862 BooleanVectorContents = Ty; 863 } 864 865 /// setSchedulingPreference - Specify the target scheduling preference. 866 void setSchedulingPreference(Sched::Preference Pref) { 867 SchedPreferenceInfo = Pref; 868 } 869 870 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 871 /// use _setjmp to implement llvm.setjmp or the non _ version. 872 /// Defaults to false. 873 void setUseUnderscoreSetJmp(bool Val) { 874 UseUnderscoreSetJmp = Val; 875 } 876 877 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 878 /// use _longjmp to implement llvm.longjmp or the non _ version. 879 /// Defaults to false. 880 void setUseUnderscoreLongJmp(bool Val) { 881 UseUnderscoreLongJmp = Val; 882 } 883 884 /// setSupportJumpTables - Indicate whether the target can generate code for 885 /// jump tables. 886 void setSupportJumpTables(bool Val) { 887 SupportJumpTables = Val; 888 } 889 890 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate 891 /// jump tables rather than if sequence. 892 void setMinimumJumpTableEntries(int Val) { 893 MinimumJumpTableEntries = Val; 894 } 895 896 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 897 /// specifies the register that llvm.savestack/llvm.restorestack should save 898 /// and restore. 899 void setStackPointerRegisterToSaveRestore(unsigned R) { 900 StackPointerRegisterToSaveRestore = R; 901 } 902 903 /// setExceptionPointerRegister - If set to a physical register, this sets 904 /// the register that receives the exception address on entry to a landing 905 /// pad. 906 void setExceptionPointerRegister(unsigned R) { 907 ExceptionPointerRegister = R; 908 } 909 910 /// setExceptionSelectorRegister - If set to a physical register, this sets 911 /// the register that receives the exception typeid on entry to a landing 912 /// pad. 913 void setExceptionSelectorRegister(unsigned R) { 914 ExceptionSelectorRegister = R; 915 } 916 917 /// SelectIsExpensive - Tells the code generator not to expand operations 918 /// into sequences that use the select operations if possible. 919 void setSelectIsExpensive(bool isExpensive = true) { 920 SelectIsExpensive = isExpensive; 921 } 922 923 /// JumpIsExpensive - Tells the code generator not to expand sequence of 924 /// operations into a separate sequences that increases the amount of 925 /// flow control. 926 void setJumpIsExpensive(bool isExpensive = true) { 927 JumpIsExpensive = isExpensive; 928 } 929 930 /// setIntDivIsCheap - Tells the code generator that integer divide is 931 /// expensive, and if possible, should be replaced by an alternate sequence 932 /// of instructions not containing an integer divide. 933 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 934 935 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass. 936 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { 937 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; 938 } 939 940 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 941 /// srl/add/sra for a signed divide by power of two, and let the target handle 942 /// it. 943 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 944 945 /// addRegisterClass - Add the specified register class as an available 946 /// regclass for the specified value type. This indicates the selector can 947 /// handle values of that class natively. 948 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { 949 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); 950 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 951 RegClassForVT[VT.SimpleTy] = RC; 952 } 953 954 /// clearRegisterClasses - Remove all register classes. 955 void clearRegisterClasses() { 956 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*)); 957 958 AvailableRegClasses.clear(); 959 } 960 961 /// \brief Remove all operation actions. 962 void clearOperationActions() { 963 } 964 965 /// findRepresentativeClass - Return the largest legal super-reg register class 966 /// of the register class for the specified type and its associated "cost". 967 virtual std::pair<const TargetRegisterClass*, uint8_t> 968 findRepresentativeClass(MVT VT) const; 969 970 /// computeRegisterProperties - Once all of the register classes are added, 971 /// this allows us to compute derived properties we expose. 972 void computeRegisterProperties(); 973 974 /// setOperationAction - Indicate that the specified operation does not work 975 /// with the specified type and indicate what to do about it. 976 void setOperationAction(unsigned Op, MVT VT, 977 LegalizeAction Action) { 978 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 979 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 980 } 981 982 /// setLoadExtAction - Indicate that the specified load with extension does 983 /// not work with the specified type and indicate what to do about it. 984 void setLoadExtAction(unsigned ExtType, MVT VT, 985 LegalizeAction Action) { 986 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 987 "Table isn't big enough!"); 988 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 989 } 990 991 /// setTruncStoreAction - Indicate that the specified truncating store does 992 /// not work with the specified type and indicate what to do about it. 993 void setTruncStoreAction(MVT ValVT, MVT MemVT, 994 LegalizeAction Action) { 995 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 996 "Table isn't big enough!"); 997 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 998 } 999 1000 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1001 /// does not work with the specified type and indicate what to do abort 1002 /// it. NOTE: All indexed mode loads are initialized to Expand in 1003 /// TargetLowering.cpp 1004 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1005 LegalizeAction Action) { 1006 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1007 (unsigned)Action < 0xf && "Table isn't big enough!"); 1008 // Load action are kept in the upper half. 1009 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1010 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1011 } 1012 1013 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1014 /// does not work with the specified type and indicate what to do about 1015 /// it. NOTE: All indexed mode stores are initialized to Expand in 1016 /// TargetLowering.cpp 1017 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1018 LegalizeAction Action) { 1019 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1020 (unsigned)Action < 0xf && "Table isn't big enough!"); 1021 // Store action are kept in the lower half. 1022 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1023 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1024 } 1025 1026 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1027 /// supported on the target and indicate what to do about it. 1028 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1029 LegalizeAction Action) { 1030 assert(VT < MVT::LAST_VALUETYPE && 1031 (unsigned)CC < array_lengthof(CondCodeActions) && 1032 "Table isn't big enough!"); 1033 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 1034 /// value and the upper 27 bits index into the second dimension of the 1035 /// array to select what 64bit value to use. 1036 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1037 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2); 1038 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1039 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2; 1040 } 1041 1042 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1043 /// promotion code defaults to trying a larger integer/fp until it can find 1044 /// one that works. If that default is insufficient, this method can be used 1045 /// by the target to override the default. 1046 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1047 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1048 } 1049 1050 /// setTargetDAGCombine - Targets should invoke this method for each target 1051 /// independent node that they want to provide a custom DAG combiner for by 1052 /// implementing the PerformDAGCombine virtual method. 1053 void setTargetDAGCombine(ISD::NodeType NT) { 1054 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1055 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1056 } 1057 1058 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1059 /// bytes); default is 200 1060 void setJumpBufSize(unsigned Size) { 1061 JumpBufSize = Size; 1062 } 1063 1064 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1065 /// alignment (in bytes); default is 0 1066 void setJumpBufAlignment(unsigned Align) { 1067 JumpBufAlignment = Align; 1068 } 1069 1070 /// setMinFunctionAlignment - Set the target's minimum function alignment (in 1071 /// log2(bytes)) 1072 void setMinFunctionAlignment(unsigned Align) { 1073 MinFunctionAlignment = Align; 1074 } 1075 1076 /// setPrefFunctionAlignment - Set the target's preferred function alignment. 1077 /// This should be set if there is a performance benefit to 1078 /// higher-than-minimum alignment (in log2(bytes)) 1079 void setPrefFunctionAlignment(unsigned Align) { 1080 PrefFunctionAlignment = Align; 1081 } 1082 1083 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1084 /// alignment is zero, it means the target does not care about loop alignment. 1085 /// The alignment is specified in log2(bytes). 1086 void setPrefLoopAlignment(unsigned Align) { 1087 PrefLoopAlignment = Align; 1088 } 1089 1090 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1091 /// argument (in log2(bytes)). 1092 void setMinStackArgumentAlignment(unsigned Align) { 1093 MinStackArgumentAlignment = Align; 1094 } 1095 1096 /// setInsertFencesForAtomic - Set if the DAG builder should 1097 /// automatically insert fences and reduce the order of atomic memory 1098 /// operations to Monotonic. 1099 void setInsertFencesForAtomic(bool fence) { 1100 InsertFencesForAtomic = fence; 1101 } 1102 1103public: 1104 //===--------------------------------------------------------------------===// 1105 // Addressing mode description hooks (used by LSR etc). 1106 // 1107 1108 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the 1109 /// same BB as Load/Store instructions reading the address. This allows as 1110 /// much computation as possible to be done in the address mode for that 1111 /// operand. This hook lets targets also pass back when this should be done 1112 /// on intrinsics which load/store. 1113 virtual bool GetAddrModeArguments(IntrinsicInst *I, 1114 SmallVectorImpl<Value*> &Ops, 1115 Type *&AccessTy) const { 1116 return false; 1117 } 1118 1119 /// AddrMode - This represents an addressing mode of: 1120 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1121 /// If BaseGV is null, there is no BaseGV. 1122 /// If BaseOffs is zero, there is no base offset. 1123 /// If HasBaseReg is false, there is no base register. 1124 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1125 /// no scale. 1126 /// 1127 struct AddrMode { 1128 GlobalValue *BaseGV; 1129 int64_t BaseOffs; 1130 bool HasBaseReg; 1131 int64_t Scale; 1132 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1133 }; 1134 1135 /// isLegalAddressingMode - Return true if the addressing mode represented by 1136 /// AM is legal for this target, for a load/store of the specified type. 1137 /// The type may be VoidTy, in which case only return true if the addressing 1138 /// mode is legal for a load/store of any legal type. 1139 /// TODO: Handle pre/postinc as well. 1140 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 1141 1142 /// \brief Return the cost of the scaling factor used in the addressing 1143 /// mode represented by AM for this target, for a load/store 1144 /// of the specified type. 1145 /// If the AM is supported, the return value must be >= 0. 1146 /// If the AM is not supported, it returns a negative value. 1147 /// TODO: Handle pre/postinc as well. 1148 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const { 1149 // Default: assume that any scaling factor used in a legal AM is free. 1150 if (isLegalAddressingMode(AM, Ty)) return 0; 1151 return -1; 1152 } 1153 1154 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1155 /// icmp immediate, that is the target has icmp instructions which can compare 1156 /// a register against the immediate without having to materialize the 1157 /// immediate into a register. 1158 virtual bool isLegalICmpImmediate(int64_t) const { 1159 return true; 1160 } 1161 1162 /// isLegalAddImmediate - Return true if the specified immediate is legal 1163 /// add immediate, that is the target has add instructions which can add 1164 /// a register with the immediate without having to materialize the 1165 /// immediate into a register. 1166 virtual bool isLegalAddImmediate(int64_t) const { 1167 return true; 1168 } 1169 1170 /// isTruncateFree - Return true if it's free to truncate a value of 1171 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1172 /// register EAX to i16 by referencing its sub-register AX. 1173 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1174 return false; 1175 } 1176 1177 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { 1178 return false; 1179 } 1180 1181 /// isZExtFree - Return true if any actual instruction that defines a 1182 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1183 /// register. This does not necessarily include registers defined in 1184 /// unknown ways, such as incoming arguments, or copies from unknown 1185 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1186 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1187 /// all instructions that define 32-bit values implicit zero-extend the 1188 /// result out to 64 bits. 1189 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1190 return false; 1191 } 1192 1193 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const { 1194 return false; 1195 } 1196 1197 /// isZExtFree - Return true if zero-extending the specific node Val to type 1198 /// VT2 is free (either because it's implicitly zero-extended such as ARM 1199 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads). 1200 virtual bool isZExtFree(SDValue Val, EVT VT2) const { 1201 return isZExtFree(Val.getValueType(), VT2); 1202 } 1203 1204 /// isFNegFree - Return true if an fneg operation is free to the point where 1205 /// it is never worthwhile to replace it with a bitwise operation. 1206 virtual bool isFNegFree(EVT) const { 1207 return false; 1208 } 1209 1210 /// isFAbsFree - Return true if an fneg operation is free to the point where 1211 /// it is never worthwhile to replace it with a bitwise operation. 1212 virtual bool isFAbsFree(EVT) const { 1213 return false; 1214 } 1215 1216 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 1217 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 1218 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 1219 /// is expanded to mul + add. 1220 virtual bool isFMAFasterThanMulAndAdd(EVT) const { 1221 return false; 1222 } 1223 1224 /// isNarrowingProfitable - Return true if it's profitable to narrow 1225 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1226 /// from i32 to i8 but not from i32 to i16. 1227 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 1228 return false; 1229 } 1230 1231 //===--------------------------------------------------------------------===// 1232 // Runtime Library hooks 1233 // 1234 1235 /// setLibcallName - Rename the default libcall routine name for the specified 1236 /// libcall. 1237 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1238 LibcallRoutineNames[Call] = Name; 1239 } 1240 1241 /// getLibcallName - Get the libcall routine name for the specified libcall. 1242 /// 1243 const char *getLibcallName(RTLIB::Libcall Call) const { 1244 return LibcallRoutineNames[Call]; 1245 } 1246 1247 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1248 /// result of the comparison libcall against zero. 1249 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1250 CmpLibcallCCs[Call] = CC; 1251 } 1252 1253 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1254 /// the comparison libcall against zero. 1255 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1256 return CmpLibcallCCs[Call]; 1257 } 1258 1259 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1260 /// specified libcall. 1261 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1262 LibcallCallingConvs[Call] = CC; 1263 } 1264 1265 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1266 /// specified libcall. 1267 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1268 return LibcallCallingConvs[Call]; 1269 } 1270 1271private: 1272 const TargetMachine &TM; 1273 const DataLayout *TD; 1274 const TargetLoweringObjectFile &TLOF; 1275 1276 /// PointerTy - The type to use for pointers for the default address space, 1277 /// usually i32 or i64. 1278 /// 1279 MVT PointerTy; 1280 1281 /// IsLittleEndian - True if this is a little endian target. 1282 /// 1283 bool IsLittleEndian; 1284 1285 /// SelectIsExpensive - Tells the code generator not to expand operations 1286 /// into sequences that use the select operations if possible. 1287 bool SelectIsExpensive; 1288 1289 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1290 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1291 /// a real cost model is in place. If we ever optimize for size, this will be 1292 /// set to true unconditionally. 1293 bool IntDivIsCheap; 1294 1295 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or 1296 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the 1297 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned 1298 /// integer div/rem when the operands are positive and less than 256. 1299 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; 1300 1301 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1302 /// srl/add/sra for a signed divide by power of two, and let the target handle 1303 /// it. 1304 bool Pow2DivIsCheap; 1305 1306 /// JumpIsExpensive - Tells the code generator that it shouldn't generate 1307 /// extra flow control instructions and should attempt to combine flow 1308 /// control instructions via predication. 1309 bool JumpIsExpensive; 1310 1311 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1312 /// llvm.setjmp. Defaults to false. 1313 bool UseUnderscoreSetJmp; 1314 1315 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1316 /// llvm.longjmp. Defaults to false. 1317 bool UseUnderscoreLongJmp; 1318 1319 /// SupportJumpTables - Whether the target can generate code for jumptables. 1320 /// If it's not true, then each jumptable must be lowered into if-then-else's. 1321 bool SupportJumpTables; 1322 1323 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables. 1324 int MinimumJumpTableEntries; 1325 1326 /// BooleanContents - Information about the contents of the high-bits in 1327 /// boolean values held in a type wider than i1. See getBooleanContents. 1328 BooleanContent BooleanContents; 1329 /// BooleanVectorContents - Information about the contents of the high-bits 1330 /// in boolean vector values when the element type is wider than i1. See 1331 /// getBooleanContents. 1332 BooleanContent BooleanVectorContents; 1333 1334 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1335 /// total cycles or lowest register usage. 1336 Sched::Preference SchedPreferenceInfo; 1337 1338 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1339 unsigned JumpBufSize; 1340 1341 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1342 /// buffers 1343 unsigned JumpBufAlignment; 1344 1345 /// MinStackArgumentAlignment - The minimum alignment that any argument 1346 /// on the stack needs to have. 1347 /// 1348 unsigned MinStackArgumentAlignment; 1349 1350 /// MinFunctionAlignment - The minimum function alignment (used when 1351 /// optimizing for size, and to prevent explicitly provided alignment 1352 /// from leading to incorrect code). 1353 /// 1354 unsigned MinFunctionAlignment; 1355 1356 /// PrefFunctionAlignment - The preferred function alignment (used when 1357 /// alignment unspecified and optimizing for speed). 1358 /// 1359 unsigned PrefFunctionAlignment; 1360 1361 /// PrefLoopAlignment - The preferred loop alignment. 1362 /// 1363 unsigned PrefLoopAlignment; 1364 1365 /// InsertFencesForAtomic - Whether the DAG builder should automatically 1366 /// insert fences and reduce ordering for atomics. (This will be set for 1367 /// for most architectures with weak memory ordering.) 1368 bool InsertFencesForAtomic; 1369 1370 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1371 /// specifies the register that llvm.savestack/llvm.restorestack should save 1372 /// and restore. 1373 unsigned StackPointerRegisterToSaveRestore; 1374 1375 /// ExceptionPointerRegister - If set to a physical register, this specifies 1376 /// the register that receives the exception address on entry to a landing 1377 /// pad. 1378 unsigned ExceptionPointerRegister; 1379 1380 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1381 /// the register that receives the exception typeid on entry to a landing 1382 /// pad. 1383 unsigned ExceptionSelectorRegister; 1384 1385 /// RegClassForVT - This indicates the default register class to use for 1386 /// each ValueType the target supports natively. 1387 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1388 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1389 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1390 1391 /// RepRegClassForVT - This indicates the "representative" register class to 1392 /// use for each ValueType the target supports natively. This information is 1393 /// used by the scheduler to track register pressure. By default, the 1394 /// representative register class is the largest legal super-reg register 1395 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1396 /// and i32's representative class would be GR32. 1397 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1398 1399 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1400 /// register class for each ValueType. The cost is used by the scheduler to 1401 /// approximate register pressure. 1402 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1403 1404 /// TransformToType - For any value types we are promoting or expanding, this 1405 /// contains the value type that we are changing to. For Expanded types, this 1406 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1407 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1408 /// by the system, this holds the same type (e.g. i32 -> i32). 1409 MVT TransformToType[MVT::LAST_VALUETYPE]; 1410 1411 /// OpActions - For each operation and each value type, keep a LegalizeAction 1412 /// that indicates how instruction selection should deal with the operation. 1413 /// Most operations are Legal (aka, supported natively by the target), but 1414 /// operations that are not should be described. Note that operations on 1415 /// non-legal value types are not described here. 1416 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1417 1418 /// LoadExtActions - For each load extension type and each value type, 1419 /// keep a LegalizeAction that indicates how instruction selection should deal 1420 /// with a load of a specific value type and extension type. 1421 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1422 1423 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1424 /// indicates whether a truncating store of a specific value type and 1425 /// truncating type is legal. 1426 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1427 1428 /// IndexedModeActions - For each indexed mode and each value type, 1429 /// keep a pair of LegalizeAction that indicates how instruction 1430 /// selection should deal with the load / store. The first dimension is the 1431 /// value_type for the reference. The second dimension represents the various 1432 /// modes for load store. 1433 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1434 1435 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1436 /// LegalizeAction that indicates how instruction selection should 1437 /// deal with the condition code. 1438 /// Because each CC action takes up 2 bits, we need to have the array size 1439 /// be large enough to fit all of the value types. This can be done by 1440 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one. 1441 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1]; 1442 1443 ValueTypeActionImpl ValueTypeActions; 1444 1445public: 1446 LegalizeKind 1447 getTypeConversion(LLVMContext &Context, EVT VT) const { 1448 // If this is a simple type, use the ComputeRegisterProp mechanism. 1449 if (VT.isSimple()) { 1450 MVT SVT = VT.getSimpleVT(); 1451 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 1452 MVT NVT = TransformToType[SVT.SimpleTy]; 1453 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 1454 1455 assert( 1456 (LA == TypeLegal || 1457 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) 1458 && "Promote may not follow Expand or Promote"); 1459 1460 if (LA == TypeSplitVector) 1461 return LegalizeKind(LA, EVT::getVectorVT(Context, 1462 SVT.getVectorElementType(), 1463 SVT.getVectorNumElements()/2)); 1464 if (LA == TypeScalarizeVector) 1465 return LegalizeKind(LA, SVT.getVectorElementType()); 1466 return LegalizeKind(LA, NVT); 1467 } 1468 1469 // Handle Extended Scalar Types. 1470 if (!VT.isVector()) { 1471 assert(VT.isInteger() && "Float types must be simple"); 1472 unsigned BitSize = VT.getSizeInBits(); 1473 // First promote to a power-of-two size, then expand if necessary. 1474 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1475 EVT NVT = VT.getRoundIntegerType(Context); 1476 assert(NVT != VT && "Unable to round integer VT"); 1477 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1478 // Avoid multi-step promotion. 1479 if (NextStep.first == TypePromoteInteger) return NextStep; 1480 // Return rounded integer type. 1481 return LegalizeKind(TypePromoteInteger, NVT); 1482 } 1483 1484 return LegalizeKind(TypeExpandInteger, 1485 EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); 1486 } 1487 1488 // Handle vector types. 1489 unsigned NumElts = VT.getVectorNumElements(); 1490 EVT EltVT = VT.getVectorElementType(); 1491 1492 // Vectors with only one element are always scalarized. 1493 if (NumElts == 1) 1494 return LegalizeKind(TypeScalarizeVector, EltVT); 1495 1496 // Try to widen vector elements until a legal type is found. 1497 if (EltVT.isInteger()) { 1498 // Vectors with a number of elements that is not a power of two are always 1499 // widened, for example <3 x float> -> <4 x float>. 1500 if (!VT.isPow2VectorType()) { 1501 NumElts = (unsigned)NextPowerOf2(NumElts); 1502 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1503 return LegalizeKind(TypeWidenVector, NVT); 1504 } 1505 1506 // Examine the element type. 1507 LegalizeKind LK = getTypeConversion(Context, EltVT); 1508 1509 // If type is to be expanded, split the vector. 1510 // <4 x i140> -> <2 x i140> 1511 if (LK.first == TypeExpandInteger) 1512 return LegalizeKind(TypeSplitVector, 1513 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1514 1515 // Promote the integer element types until a legal vector type is found 1516 // or until the element integer type is too big. If a legal type was not 1517 // found, fallback to the usual mechanism of widening/splitting the 1518 // vector. 1519 EVT OldEltVT = EltVT; 1520 while (1) { 1521 // Increase the bitwidth of the element to the next pow-of-two 1522 // (which is greater than 8 bits). 1523 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() 1524 ).getRoundIntegerType(Context); 1525 1526 // Stop trying when getting a non-simple element type. 1527 // Note that vector elements may be greater than legal vector element 1528 // types. Example: X86 XMM registers hold 64bit element on 32bit systems. 1529 if (!EltVT.isSimple()) break; 1530 1531 // Build a new vector type and check if it is legal. 1532 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1533 // Found a legal promoted vector type. 1534 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1535 return LegalizeKind(TypePromoteInteger, 1536 EVT::getVectorVT(Context, EltVT, NumElts)); 1537 } 1538 1539 // Reset the type to the unexpanded type if we did not find a legal vector 1540 // type with a promoted vector element type. 1541 EltVT = OldEltVT; 1542 } 1543 1544 // Try to widen the vector until a legal type is found. 1545 // If there is no wider legal type, split the vector. 1546 while (1) { 1547 // Round up to the next power of 2. 1548 NumElts = (unsigned)NextPowerOf2(NumElts); 1549 1550 // If there is no simple vector type with this many elements then there 1551 // cannot be a larger legal vector type. Note that this assumes that 1552 // there are no skipped intermediate vector types in the simple types. 1553 if (!EltVT.isSimple()) break; 1554 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1555 if (LargerVector == MVT()) break; 1556 1557 // If this type is legal then widen the vector. 1558 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1559 return LegalizeKind(TypeWidenVector, LargerVector); 1560 } 1561 1562 // Widen odd vectors to next power of two. 1563 if (!VT.isPow2VectorType()) { 1564 EVT NVT = VT.getPow2VectorType(Context); 1565 return LegalizeKind(TypeWidenVector, NVT); 1566 } 1567 1568 // Vectors with illegal element types are expanded. 1569 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1570 return LegalizeKind(TypeSplitVector, NVT); 1571 } 1572 1573private: 1574 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses; 1575 1576 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1577 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1578 /// which sets a bit in this array. 1579 unsigned char 1580 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1581 1582 /// PromoteToType - For operations that must be promoted to a specific type, 1583 /// this holds the destination type. This map should be sparse, so don't hold 1584 /// it as an array. 1585 /// 1586 /// Targets add entries to this map with AddPromotedToType(..), clients access 1587 /// this with getTypeToPromoteTo(..). 1588 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1589 PromoteToType; 1590 1591 /// LibcallRoutineNames - Stores the name each libcall. 1592 /// 1593 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1594 1595 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1596 /// of each of the comparison libcall against zero. 1597 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1598 1599 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1600 /// libcall. 1601 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1602 1603protected: 1604 /// When lowering \@llvm.memset this field specifies the maximum number of 1605 /// store operations that may be substituted for the call to memset. Targets 1606 /// must set this value based on the cost threshold for that target. Targets 1607 /// should assume that the memset will be done using as many of the largest 1608 /// store operations first, followed by smaller ones, if necessary, per 1609 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1610 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1611 /// store. This only applies to setting a constant array of a constant size. 1612 /// @brief Specify maximum number of store instructions per memset call. 1613 unsigned MaxStoresPerMemset; 1614 1615 /// Maximum number of stores operations that may be substituted for the call 1616 /// to memset, used for functions with OptSize attribute. 1617 unsigned MaxStoresPerMemsetOptSize; 1618 1619 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1620 /// store operations that may be substituted for a call to memcpy. Targets 1621 /// must set this value based on the cost threshold for that target. Targets 1622 /// should assume that the memcpy will be done using as many of the largest 1623 /// store operations first, followed by smaller ones, if necessary, per 1624 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1625 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1626 /// and one 1-byte store. This only applies to copying a constant array of 1627 /// constant size. 1628 /// @brief Specify maximum bytes of store instructions per memcpy call. 1629 unsigned MaxStoresPerMemcpy; 1630 1631 /// Maximum number of store operations that may be substituted for a call 1632 /// to memcpy, used for functions with OptSize attribute. 1633 unsigned MaxStoresPerMemcpyOptSize; 1634 1635 /// When lowering \@llvm.memmove this field specifies the maximum number of 1636 /// store instructions that may be substituted for a call to memmove. Targets 1637 /// must set this value based on the cost threshold for that target. Targets 1638 /// should assume that the memmove will be done using as many of the largest 1639 /// store operations first, followed by smaller ones, if necessary, per 1640 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1641 /// with 8-bit alignment would result in nine 1-byte stores. This only 1642 /// applies to copying a constant array of constant size. 1643 /// @brief Specify maximum bytes of store instructions per memmove call. 1644 unsigned MaxStoresPerMemmove; 1645 1646 /// Maximum number of store instructions that may be substituted for a call 1647 /// to memmove, used for functions with OpSize attribute. 1648 unsigned MaxStoresPerMemmoveOptSize; 1649 1650 /// PredictableSelectIsExpensive - Tells the code generator that select is 1651 /// more expensive than a branch if the branch is usually predicted right. 1652 bool PredictableSelectIsExpensive; 1653 1654protected: 1655 /// isLegalRC - Return true if the value types that can be represented by the 1656 /// specified register class are all legal. 1657 bool isLegalRC(const TargetRegisterClass *RC) const; 1658}; 1659 1660//===----------------------------------------------------------------------===// 1661/// TargetLowering - This class defines information used to lower LLVM code to 1662/// legal SelectionDAG operators that the target instruction selector can accept 1663/// natively. 1664/// 1665/// This class also defines callbacks that targets must implement to lower 1666/// target-specific constructs to SelectionDAG operators. 1667/// 1668class TargetLowering : public TargetLoweringBase { 1669 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION; 1670 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; 1671 1672public: 1673 /// NOTE: The constructor takes ownership of TLOF. 1674 explicit TargetLowering(const TargetMachine &TM, 1675 const TargetLoweringObjectFile *TLOF); 1676 1677 /// getPreIndexedAddressParts - returns true by value, base pointer and 1678 /// offset pointer and addressing mode by reference if the node's address 1679 /// can be legally represented as pre-indexed load / store address. 1680 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 1681 SDValue &/*Offset*/, 1682 ISD::MemIndexedMode &/*AM*/, 1683 SelectionDAG &/*DAG*/) const { 1684 return false; 1685 } 1686 1687 /// getPostIndexedAddressParts - returns true by value, base pointer and 1688 /// offset pointer and addressing mode by reference if this node can be 1689 /// combined with a load / store to form a post-indexed load / store. 1690 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 1691 SDValue &/*Base*/, SDValue &/*Offset*/, 1692 ISD::MemIndexedMode &/*AM*/, 1693 SelectionDAG &/*DAG*/) const { 1694 return false; 1695 } 1696 1697 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 1698 /// current function. The returned value is a member of the 1699 /// MachineJumpTableInfo::JTEntryKind enum. 1700 virtual unsigned getJumpTableEncoding() const; 1701 1702 virtual const MCExpr * 1703 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 1704 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 1705 MCContext &/*Ctx*/) const { 1706 llvm_unreachable("Need to implement this hook if target has custom JTIs"); 1707 } 1708 1709 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1710 /// jumptable. 1711 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 1712 SelectionDAG &DAG) const; 1713 1714 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1715 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1716 /// MCExpr. 1717 virtual const MCExpr * 1718 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1719 unsigned JTI, MCContext &Ctx) const; 1720 1721 /// isOffsetFoldingLegal - Return true if folding a constant offset 1722 /// with the given GlobalAddress is legal. It is frequently not legal in 1723 /// PIC relocation models. 1724 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 1725 1726 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 1727 SDValue &Chain) const; 1728 1729 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, 1730 SDValue &NewLHS, SDValue &NewRHS, 1731 ISD::CondCode &CCCode, SDLoc DL) const; 1732 1733 SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, 1734 const SDValue *Ops, unsigned NumOps, 1735 bool isSigned, SDLoc dl) const; 1736 1737 //===--------------------------------------------------------------------===// 1738 // TargetLowering Optimization Methods 1739 // 1740 1741 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 1742 /// SDValues for returning information from TargetLowering to its clients 1743 /// that want to combine 1744 struct TargetLoweringOpt { 1745 SelectionDAG &DAG; 1746 bool LegalTys; 1747 bool LegalOps; 1748 SDValue Old; 1749 SDValue New; 1750 1751 explicit TargetLoweringOpt(SelectionDAG &InDAG, 1752 bool LT, bool LO) : 1753 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 1754 1755 bool LegalTypes() const { return LegalTys; } 1756 bool LegalOperations() const { return LegalOps; } 1757 1758 bool CombineTo(SDValue O, SDValue N) { 1759 Old = O; 1760 New = N; 1761 return true; 1762 } 1763 1764 /// ShrinkDemandedConstant - Check to see if the specified operand of the 1765 /// specified instruction is a constant integer. If so, check to see if 1766 /// there are any bits set in the constant that are not demanded. If so, 1767 /// shrink the constant and return true. 1768 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 1769 1770 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1771 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1772 /// cast, but it could be generalized for targets with other types of 1773 /// implicit widening casts. 1774 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 1775 SDLoc dl); 1776 }; 1777 1778 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1779 /// DemandedMask bits of the result of Op are ever used downstream. If we can 1780 /// use this information to simplify Op, create a new simplified DAG node and 1781 /// return true, returning the original and new nodes in Old and New. 1782 /// Otherwise, analyze the expression and return a mask of KnownOne and 1783 /// KnownZero bits for the expression (used to simplify the caller). 1784 /// The KnownZero/One bits may only be accurate for those bits in the 1785 /// DemandedMask. 1786 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 1787 APInt &KnownZero, APInt &KnownOne, 1788 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 1789 1790 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 1791 /// Mask are known to be either zero or one and return them in the 1792 /// KnownZero/KnownOne bitsets. 1793 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 1794 APInt &KnownZero, 1795 APInt &KnownOne, 1796 const SelectionDAG &DAG, 1797 unsigned Depth = 0) const; 1798 1799 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1800 /// targets that want to expose additional information about sign bits to the 1801 /// DAG Combiner. 1802 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 1803 unsigned Depth = 0) const; 1804 1805 struct DAGCombinerInfo { 1806 void *DC; // The DAG Combiner object. 1807 CombineLevel Level; 1808 bool CalledByLegalizer; 1809 public: 1810 SelectionDAG &DAG; 1811 1812 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc) 1813 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {} 1814 1815 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } 1816 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } 1817 bool isAfterLegalizeVectorOps() const { 1818 return Level == AfterLegalizeDAG; 1819 } 1820 CombineLevel getDAGCombineLevel() { return Level; } 1821 bool isCalledByLegalizer() const { return CalledByLegalizer; } 1822 1823 void AddToWorklist(SDNode *N); 1824 void RemoveFromWorklist(SDNode *N); 1825 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 1826 bool AddTo = true); 1827 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 1828 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 1829 1830 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 1831 }; 1832 1833 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 1834 /// and cc. If it is unable to simplify it, return a null SDValue. 1835 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1836 ISD::CondCode Cond, bool foldBooleans, 1837 DAGCombinerInfo &DCI, SDLoc dl) const; 1838 1839 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1840 /// node is a GlobalAddress + offset. 1841 virtual bool 1842 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 1843 1844 /// PerformDAGCombine - This method will be invoked for all target nodes and 1845 /// for any target-independent nodes that the target has registered with 1846 /// invoke it for. 1847 /// 1848 /// The semantics are as follows: 1849 /// Return Value: 1850 /// SDValue.Val == 0 - No change was made 1851 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 1852 /// otherwise - N should be replaced by the returned Operand. 1853 /// 1854 /// In addition, methods provided by DAGCombinerInfo may be used to perform 1855 /// more complex transformations. 1856 /// 1857 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1858 1859 /// isTypeDesirableForOp - Return true if the target has native support for 1860 /// the specified value type and it is 'desirable' to use the type for the 1861 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 1862 /// instruction encodings are longer and some i16 instructions are slow. 1863 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 1864 // By default, assume all legal types are desirable. 1865 return isTypeLegal(VT); 1866 } 1867 1868 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner 1869 /// to transform a floating point op of specified opcode to a equivalent op of 1870 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM. 1871 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 1872 EVT /*VT*/) const { 1873 return false; 1874 } 1875 1876 /// IsDesirableToPromoteOp - This method query the target whether it is 1877 /// beneficial for dag combiner to promote the specified node. If true, it 1878 /// should return the desired promotion type by reference. 1879 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 1880 return false; 1881 } 1882 1883 //===--------------------------------------------------------------------===// 1884 // Lowering methods - These methods must be implemented by targets so that 1885 // the SelectionDAGBuilder code knows how to lower these. 1886 // 1887 1888 /// LowerFormalArguments - This hook must be implemented to lower the 1889 /// incoming (formal) arguments, described by the Ins array, into the 1890 /// specified DAG. The implementation should fill in the InVals array 1891 /// with legal-type argument values, and return the resulting token 1892 /// chain value. 1893 /// 1894 virtual SDValue 1895 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1896 bool /*isVarArg*/, 1897 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1898 SDLoc /*dl*/, SelectionDAG &/*DAG*/, 1899 SmallVectorImpl<SDValue> &/*InVals*/) const { 1900 llvm_unreachable("Not Implemented"); 1901 } 1902 1903 struct ArgListEntry { 1904 SDValue Node; 1905 Type* Ty; 1906 bool isSExt : 1; 1907 bool isZExt : 1; 1908 bool isInReg : 1; 1909 bool isSRet : 1; 1910 bool isNest : 1; 1911 bool isByVal : 1; 1912 bool isReturned : 1; 1913 uint16_t Alignment; 1914 1915 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1916 isSRet(false), isNest(false), isByVal(false), isReturned(false), 1917 Alignment(0) { } 1918 }; 1919 typedef std::vector<ArgListEntry> ArgListTy; 1920 1921 /// CallLoweringInfo - This structure contains all information that is 1922 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the 1923 /// SelectionDAG builder needs to lower a call, and targets will see this 1924 /// struct in their LowerCall implementation. 1925 struct CallLoweringInfo { 1926 SDValue Chain; 1927 Type *RetTy; 1928 bool RetSExt : 1; 1929 bool RetZExt : 1; 1930 bool IsVarArg : 1; 1931 bool IsInReg : 1; 1932 bool DoesNotReturn : 1; 1933 bool IsReturnValueUsed : 1; 1934 1935 // IsTailCall should be modified by implementations of 1936 // TargetLowering::LowerCall that perform tail call conversions. 1937 bool IsTailCall; 1938 1939 unsigned NumFixedArgs; 1940 CallingConv::ID CallConv; 1941 SDValue Callee; 1942 ArgListTy &Args; 1943 SelectionDAG &DAG; 1944 SDLoc DL; 1945 ImmutableCallSite *CS; 1946 SmallVector<ISD::OutputArg, 32> Outs; 1947 SmallVector<SDValue, 32> OutVals; 1948 SmallVector<ISD::InputArg, 32> Ins; 1949 1950 1951 /// CallLoweringInfo - Constructs a call lowering context based on the 1952 /// ImmutableCallSite \p cs. 1953 CallLoweringInfo(SDValue chain, Type *retTy, 1954 FunctionType *FTy, bool isTailCall, SDValue callee, 1955 ArgListTy &args, SelectionDAG &dag, SDLoc dl, 1956 ImmutableCallSite &cs) 1957 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)), 1958 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()), 1959 IsInReg(cs.paramHasAttr(0, Attribute::InReg)), 1960 DoesNotReturn(cs.doesNotReturn()), 1961 IsReturnValueUsed(!cs.getInstruction()->use_empty()), 1962 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()), 1963 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag), 1964 DL(dl), CS(&cs) {} 1965 1966 /// CallLoweringInfo - Constructs a call lowering context based on the 1967 /// provided call information. 1968 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt, 1969 bool isVarArg, bool isInReg, unsigned numFixedArgs, 1970 CallingConv::ID callConv, bool isTailCall, 1971 bool doesNotReturn, bool isReturnValueUsed, SDValue callee, 1972 ArgListTy &args, SelectionDAG &dag, SDLoc dl) 1973 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), 1974 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), 1975 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), 1976 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee), 1977 Args(args), DAG(dag), DL(dl), CS(NULL) {} 1978 }; 1979 1980 /// LowerCallTo - This function lowers an abstract call to a function into an 1981 /// actual call. This returns a pair of operands. The first element is the 1982 /// return value for the function (if RetTy is not VoidTy). The second 1983 /// element is the outgoing token chain. It calls LowerCall to do the actual 1984 /// lowering. 1985 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; 1986 1987 /// LowerCall - This hook must be implemented to lower calls into the 1988 /// the specified DAG. The outgoing arguments to the call are described 1989 /// by the Outs array, and the values to be returned by the call are 1990 /// described by the Ins array. The implementation should fill in the 1991 /// InVals array with legal-type return values from the call, and return 1992 /// the resulting token chain value. 1993 virtual SDValue 1994 LowerCall(CallLoweringInfo &/*CLI*/, 1995 SmallVectorImpl<SDValue> &/*InVals*/) const { 1996 llvm_unreachable("Not Implemented"); 1997 } 1998 1999 /// HandleByVal - Target-specific cleanup for formal ByVal parameters. 2000 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {} 2001 2002 /// CanLowerReturn - This hook should be implemented to check whether the 2003 /// return values described by the Outs array can fit into the return 2004 /// registers. If false is returned, an sret-demotion is performed. 2005 /// 2006 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 2007 MachineFunction &/*MF*/, bool /*isVarArg*/, 2008 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2009 LLVMContext &/*Context*/) const 2010 { 2011 // Return true by default to get preexisting behavior. 2012 return true; 2013 } 2014 2015 /// LowerReturn - This hook must be implemented to lower outgoing 2016 /// return values, described by the Outs array, into the specified 2017 /// DAG. The implementation should return the resulting token chain 2018 /// value. 2019 /// 2020 virtual SDValue 2021 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 2022 bool /*isVarArg*/, 2023 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2024 const SmallVectorImpl<SDValue> &/*OutVals*/, 2025 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const { 2026 llvm_unreachable("Not Implemented"); 2027 } 2028 2029 /// isUsedByReturnOnly - Return true if result of the specified node is used 2030 /// by a return node only. It also compute and return the input chain for the 2031 /// tail call. 2032 /// This is used to determine whether it is possible 2033 /// to codegen a libcall as tail call at legalization time. 2034 virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const { 2035 return false; 2036 } 2037 2038 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the 2039 /// call instruction as a tail call. This is used by optimization passes to 2040 /// determine if it's profitable to duplicate return instructions to enable 2041 /// tailcall optimization. 2042 virtual bool mayBeEmittedAsTailCall(CallInst *) const { 2043 return false; 2044 } 2045 2046 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or 2047 /// sign extend a zeroext/signext integer argument or return value. 2048 /// FIXME: Most C calling convention requires the return type to be promoted, 2049 /// but this is not true all the time, e.g. i1 on x86-64. It is also not 2050 /// necessary for non-C calling conventions. The frontend should handle this 2051 /// and include all of the necessary information. 2052 virtual MVT getTypeForExtArgOrReturn(MVT VT, 2053 ISD::NodeType /*ExtendKind*/) const { 2054 MVT MinVT = getRegisterType(MVT::i32); 2055 return VT.bitsLT(MinVT) ? MinVT : VT; 2056 } 2057 2058 /// LowerOperationWrapper - This callback is invoked by the type legalizer 2059 /// to legalize nodes with an illegal operand type but legal result types. 2060 /// It replaces the LowerOperation callback in the type Legalizer. 2061 /// The reason we can not do away with LowerOperation entirely is that 2062 /// LegalizeDAG isn't yet ready to use this callback. 2063 /// TODO: Consider merging with ReplaceNodeResults. 2064 2065 /// The target places new result values for the node in Results (their number 2066 /// and types must exactly match those of the original return values of 2067 /// the node), or leaves Results empty, which indicates that the node is not 2068 /// to be custom lowered after all. 2069 /// The default implementation calls LowerOperation. 2070 virtual void LowerOperationWrapper(SDNode *N, 2071 SmallVectorImpl<SDValue> &Results, 2072 SelectionDAG &DAG) const; 2073 2074 /// LowerOperation - This callback is invoked for operations that are 2075 /// unsupported by the target, which are registered to use 'custom' lowering, 2076 /// and whose defined values are all legal. 2077 /// If the target has no operations that require custom lowering, it need not 2078 /// implement this. The default implementation of this aborts. 2079 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 2080 2081 /// ReplaceNodeResults - This callback is invoked when a node result type is 2082 /// illegal for the target, and the operation was registered to use 'custom' 2083 /// lowering for that result type. The target places new result values for 2084 /// the node in Results (their number and types must exactly match those of 2085 /// the original return values of the node), or leaves Results empty, which 2086 /// indicates that the node is not to be custom lowered after all. 2087 /// 2088 /// If the target has no operations that require custom lowering, it need not 2089 /// implement this. The default implementation aborts. 2090 virtual void ReplaceNodeResults(SDNode * /*N*/, 2091 SmallVectorImpl<SDValue> &/*Results*/, 2092 SelectionDAG &/*DAG*/) const { 2093 llvm_unreachable("ReplaceNodeResults not implemented for this target!"); 2094 } 2095 2096 /// getTargetNodeName() - This method returns the name of a target specific 2097 /// DAG node. 2098 virtual const char *getTargetNodeName(unsigned Opcode) const; 2099 2100 /// createFastISel - This method returns a target specific FastISel object, 2101 /// or null if the target does not support "fast" ISel. 2102 virtual FastISel *createFastISel(FunctionLoweringInfo &, 2103 const TargetLibraryInfo *) const { 2104 return 0; 2105 } 2106 2107 //===--------------------------------------------------------------------===// 2108 // Inline Asm Support hooks 2109 // 2110 2111 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 2112 /// call to be explicit llvm code if it wants to. This is useful for 2113 /// turning simple inline asms into LLVM intrinsics, which gives the 2114 /// compiler more information about the behavior of the code. 2115 virtual bool ExpandInlineAsm(CallInst *) const { 2116 return false; 2117 } 2118 2119 enum ConstraintType { 2120 C_Register, // Constraint represents specific register(s). 2121 C_RegisterClass, // Constraint represents any of register(s) in class. 2122 C_Memory, // Memory constraint. 2123 C_Other, // Something else. 2124 C_Unknown // Unsupported constraint. 2125 }; 2126 2127 enum ConstraintWeight { 2128 // Generic weights. 2129 CW_Invalid = -1, // No match. 2130 CW_Okay = 0, // Acceptable. 2131 CW_Good = 1, // Good weight. 2132 CW_Better = 2, // Better weight. 2133 CW_Best = 3, // Best weight. 2134 2135 // Well-known weights. 2136 CW_SpecificReg = CW_Okay, // Specific register operands. 2137 CW_Register = CW_Good, // Register operands. 2138 CW_Memory = CW_Better, // Memory operands. 2139 CW_Constant = CW_Best, // Constant operand. 2140 CW_Default = CW_Okay // Default or don't know type. 2141 }; 2142 2143 /// AsmOperandInfo - This contains information for each constraint that we are 2144 /// lowering. 2145 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 2146 /// ConstraintCode - This contains the actual string for the code, like "m". 2147 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 2148 /// most closely matches the operand. 2149 std::string ConstraintCode; 2150 2151 /// ConstraintType - Information about the constraint code, e.g. Register, 2152 /// RegisterClass, Memory, Other, Unknown. 2153 TargetLowering::ConstraintType ConstraintType; 2154 2155 /// CallOperandval - If this is the result output operand or a 2156 /// clobber, this is null, otherwise it is the incoming operand to the 2157 /// CallInst. This gets modified as the asm is processed. 2158 Value *CallOperandVal; 2159 2160 /// ConstraintVT - The ValueType for the operand value. 2161 MVT ConstraintVT; 2162 2163 /// isMatchingInputConstraint - Return true of this is an input operand that 2164 /// is a matching constraint like "4". 2165 bool isMatchingInputConstraint() const; 2166 2167 /// getMatchedOperand - If this is an input matching constraint, this method 2168 /// returns the output operand it matches. 2169 unsigned getMatchedOperand() const; 2170 2171 /// Copy constructor for copying from an AsmOperandInfo. 2172 AsmOperandInfo(const AsmOperandInfo &info) 2173 : InlineAsm::ConstraintInfo(info), 2174 ConstraintCode(info.ConstraintCode), 2175 ConstraintType(info.ConstraintType), 2176 CallOperandVal(info.CallOperandVal), 2177 ConstraintVT(info.ConstraintVT) { 2178 } 2179 2180 /// Copy constructor for copying from a ConstraintInfo. 2181 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 2182 : InlineAsm::ConstraintInfo(info), 2183 ConstraintType(TargetLowering::C_Unknown), 2184 CallOperandVal(0), ConstraintVT(MVT::Other) { 2185 } 2186 }; 2187 2188 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 2189 2190 /// ParseConstraints - Split up the constraint string from the inline 2191 /// assembly value into the specific constraints and their prefixes, 2192 /// and also tie in the associated operand values. 2193 /// If this returns an empty vector, and if the constraint string itself 2194 /// isn't empty, there was an error parsing. 2195 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 2196 2197 /// Examine constraint type and operand type and determine a weight value. 2198 /// The operand object must already have been set up with the operand type. 2199 virtual ConstraintWeight getMultipleConstraintMatchWeight( 2200 AsmOperandInfo &info, int maIndex) const; 2201 2202 /// Examine constraint string and operand type and determine a weight value. 2203 /// The operand object must already have been set up with the operand type. 2204 virtual ConstraintWeight getSingleConstraintMatchWeight( 2205 AsmOperandInfo &info, const char *constraint) const; 2206 2207 /// ComputeConstraintToUse - Determines the constraint code and constraint 2208 /// type to use for the specific AsmOperandInfo, setting 2209 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 2210 /// being passed in is available, it can be passed in as Op, otherwise an 2211 /// empty SDValue can be passed. 2212 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2213 SDValue Op, 2214 SelectionDAG *DAG = 0) const; 2215 2216 /// getConstraintType - Given a constraint, return the type of constraint it 2217 /// is for this target. 2218 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 2219 2220 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 2221 /// {edx}), return the register number and the register class for the 2222 /// register. 2223 /// 2224 /// Given a register class constraint, like 'r', if this corresponds directly 2225 /// to an LLVM register class, return a register of 0 and the register class 2226 /// pointer. 2227 /// 2228 /// This should only be used for C_Register constraints. On error, 2229 /// this returns a register number of 0 and a null register class pointer.. 2230 virtual std::pair<unsigned, const TargetRegisterClass*> 2231 getRegForInlineAsmConstraint(const std::string &Constraint, 2232 EVT VT) const; 2233 2234 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2235 /// with another that has more specific requirements based on the type of the 2236 /// corresponding operand. This returns null if there is no replacement to 2237 /// make. 2238 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 2239 2240 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2241 /// vector. If it is invalid, don't add anything to Ops. 2242 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 2243 std::vector<SDValue> &Ops, 2244 SelectionDAG &DAG) const; 2245 2246 //===--------------------------------------------------------------------===// 2247 // Div utility functions 2248 // 2249 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, 2250 SelectionDAG &DAG) const; 2251 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2252 std::vector<SDNode*> *Created) const; 2253 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2254 std::vector<SDNode*> *Created) const; 2255 2256 //===--------------------------------------------------------------------===// 2257 // Instruction Emitting Hooks 2258 // 2259 2260 // EmitInstrWithCustomInserter - This method should be implemented by targets 2261 // that mark instructions with the 'usesCustomInserter' flag. These 2262 // instructions are special in various ways, which require special support to 2263 // insert. The specified MachineInstr is created but not inserted into any 2264 // basic blocks, and this method is called to expand it into a sequence of 2265 // instructions, potentially also creating new basic blocks and control flow. 2266 virtual MachineBasicBlock * 2267 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 2268 2269 /// AdjustInstrPostInstrSelection - This method should be implemented by 2270 /// targets that mark instructions with the 'hasPostISelHook' flag. These 2271 /// instructions must be adjusted after instruction selection by target hooks. 2272 /// e.g. To fill in optional defs for ARM 's' setting instructions. 2273 virtual void 2274 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 2275}; 2276 2277/// GetReturnInfo - Given an LLVM IR type and return type attributes, 2278/// compute the return value EVTs and flags, and optionally also 2279/// the offsets, if the return value is being lowered to memory. 2280void GetReturnInfo(Type* ReturnType, AttributeSet attr, 2281 SmallVectorImpl<ISD::OutputArg> &Outs, 2282 const TargetLowering &TLI); 2283 2284} // end llvm namespace 2285 2286#endif 2287