TargetLowering.h revision 31959b19a72608051888160514977875a8027dfc
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Attributes.h" 28#include "llvm/ADT/SmallPtrSet.h" 29#include "llvm/CodeGen/SelectionDAGNodes.h" 30#include "llvm/CodeGen/RuntimeLibcalls.h" 31#include "llvm/Support/DebugLoc.h" 32#include "llvm/Target/TargetCallingConv.h" 33#include "llvm/Target/TargetMachine.h" 34#include <climits> 35#include <map> 36#include <vector> 37 38namespace llvm { 39 class AllocaInst; 40 class APFloat; 41 class CallInst; 42 class Function; 43 class FastISel; 44 class FunctionLoweringInfo; 45 class ImmutableCallSite; 46 class MachineBasicBlock; 47 class MachineFunction; 48 class MachineFrameInfo; 49 class MachineInstr; 50 class MachineJumpTableInfo; 51 class MCContext; 52 class MCExpr; 53 class SDNode; 54 class SDValue; 55 class SelectionDAG; 56 template<typename T> class SmallVectorImpl; 57 class TargetData; 58 class TargetMachine; 59 class TargetRegisterClass; 60 class TargetLoweringObjectFile; 61 class Value; 62 63 // FIXME: should this be here? 64 namespace TLSModel { 65 enum Model { 66 GeneralDynamic, 67 LocalDynamic, 68 InitialExec, 69 LocalExec 70 }; 71 } 72 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 73 74 75//===----------------------------------------------------------------------===// 76/// TargetLowering - This class defines information used to lower LLVM code to 77/// legal SelectionDAG operators that the target instruction selector can accept 78/// natively. 79/// 80/// This class also defines callbacks that targets must implement to lower 81/// target-specific constructs to SelectionDAG operators. 82/// 83class TargetLowering { 84 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 85 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 86public: 87 /// LegalizeAction - This enum indicates whether operations are valid for a 88 /// target, and if not, what action should be used to make them valid. 89 enum LegalizeAction { 90 Legal, // The target natively supports this operation. 91 Promote, // This operation should be executed in a larger type. 92 Expand, // Try to expand this to other ops, otherwise use a libcall. 93 Custom // Use the LowerOperation hook to implement custom lowering. 94 }; 95 96 enum BooleanContent { // How the target represents true/false values. 97 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 98 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 99 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 100 }; 101 102 /// NOTE: The constructor takes ownership of TLOF. 103 explicit TargetLowering(const TargetMachine &TM, 104 const TargetLoweringObjectFile *TLOF); 105 virtual ~TargetLowering(); 106 107 const TargetMachine &getTargetMachine() const { return TM; } 108 const TargetData *getTargetData() const { return TD; } 109 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 110 111 bool isBigEndian() const { return !IsLittleEndian; } 112 bool isLittleEndian() const { return IsLittleEndian; } 113 MVT getPointerTy() const { return PointerTy; } 114 MVT getShiftAmountTy() const { return ShiftAmountTy; } 115 116 /// isSelectExpensive - Return true if the select operation is expensive for 117 /// this target. 118 bool isSelectExpensive() const { return SelectIsExpensive; } 119 120 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 121 /// a sequence of several shifts, adds, and multiplies for this target. 122 bool isIntDivCheap() const { return IntDivIsCheap; } 123 124 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 125 /// srl/add/sra. 126 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 127 128 /// isJumpExpensive() - Return true if Flow Control is an expensive operation 129 /// that should be avoided. 130 bool isJumpExpensive() const { return JumpIsExpensive; } 131 132 /// getSetCCResultType - Return the ValueType of the result of SETCC 133 /// operations. Also used to obtain the target's preferred type for 134 /// the condition operand of SELECT and BRCOND nodes. In the case of 135 /// BRCOND the argument passed is MVT::Other since there are no other 136 /// operands to get a type hint from. 137 virtual 138 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 139 140 /// getCmpLibcallReturnType - Return the ValueType for comparison 141 /// libcalls. Comparions libcalls include floating point comparion calls, 142 /// and Ordered/Unordered check calls on floating point numbers. 143 virtual 144 MVT::SimpleValueType getCmpLibcallReturnType() const; 145 146 /// getBooleanContents - For targets without i1 registers, this gives the 147 /// nature of the high-bits of boolean values held in types wider than i1. 148 /// "Boolean values" are special true/false values produced by nodes like 149 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 150 /// Not to be confused with general values promoted from i1. 151 BooleanContent getBooleanContents() const { return BooleanContents;} 152 153 /// getSchedulingPreference - Return target scheduling preference. 154 Sched::Preference getSchedulingPreference() const { 155 return SchedPreferenceInfo; 156 } 157 158 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 159 /// different scheduling heuristics for different nodes. This function returns 160 /// the preference (or none) for the given node. 161 virtual Sched::Preference getSchedulingPreference(SDNode *N) const { 162 return Sched::None; 163 } 164 165 /// getRegClassFor - Return the register class that should be used for the 166 /// specified value type. 167 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { 168 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 169 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 170 assert(RC && "This value type is not natively supported!"); 171 return RC; 172 } 173 174 /// getRepRegClassFor - Return the 'representative' register class for the 175 /// specified value type. The 'representative' register class is the largest 176 /// legal super-reg register class for the register class of the value type. 177 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 178 /// while the rep register class is GR64 on x86_64. 179 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { 180 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!"); 181 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; 182 return RC; 183 } 184 185 /// getRepRegClassCostFor - Return the cost of the 'representative' register 186 /// class for the specified value type. 187 virtual uint8_t getRepRegClassCostFor(EVT VT) const { 188 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!"); 189 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; 190 } 191 192 /// getRegPressureLimit - Return the register pressure "high water mark" for 193 /// the specific register class. The scheduler is in high register pressure 194 /// mode (for the specific register class) if it goes over the limit. 195 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 196 MachineFunction &MF) const { 197 return 0; 198 } 199 200 /// isTypeLegal - Return true if the target has native support for the 201 /// specified value type. This means that it has a register that directly 202 /// holds it without promotions or expansions. 203 bool isTypeLegal(EVT VT) const { 204 assert(!VT.isSimple() || 205 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 206 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 207 } 208 209 class ValueTypeActionImpl { 210 /// ValueTypeActions - For each value type, keep a LegalizeAction enum 211 /// that indicates how instruction selection should deal with the type. 212 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 213 214 LegalizeAction getExtendedTypeAction(EVT VT) const { 215 // Handle non-vector integers. 216 if (!VT.isVector()) { 217 assert(VT.isInteger() && "Unsupported extended type!"); 218 unsigned BitSize = VT.getSizeInBits(); 219 // First promote to a power-of-two size, then expand if necessary. 220 if (BitSize < 8 || !isPowerOf2_32(BitSize)) 221 return Promote; 222 return Expand; 223 } 224 225 // If this is a type smaller than a legal vector type, promote to that 226 // type, e.g. <2 x float> -> <4 x float>. 227 if (VT.getVectorElementType().isSimple() && 228 VT.getVectorNumElements() != 1) { 229 MVT EltType = VT.getVectorElementType().getSimpleVT(); 230 unsigned NumElts = VT.getVectorNumElements(); 231 while (1) { 232 // Round up to the nearest power of 2. 233 NumElts = (unsigned)NextPowerOf2(NumElts); 234 235 MVT LargerVector = MVT::getVectorVT(EltType, NumElts); 236 if (LargerVector == MVT()) break; 237 238 // If this the larger type is legal, promote to it. 239 if (getTypeAction(LargerVector) == Legal) return Promote; 240 } 241 } 242 243 return VT.isPow2VectorType() ? Expand : Promote; 244 } 245 public: 246 ValueTypeActionImpl() { 247 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 248 } 249 250 LegalizeAction getTypeAction(EVT VT) const { 251 if (!VT.isExtended()) 252 return getTypeAction(VT.getSimpleVT()); 253 return getExtendedTypeAction(VT); 254 } 255 256 LegalizeAction getTypeAction(MVT VT) const { 257 return (LegalizeAction)ValueTypeActions[VT.SimpleTy]; 258 } 259 260 void setTypeAction(EVT VT, LegalizeAction Action) { 261 unsigned I = VT.getSimpleVT().SimpleTy; 262 ValueTypeActions[I] = Action; 263 } 264 }; 265 266 const ValueTypeActionImpl &getValueTypeActions() const { 267 return ValueTypeActions; 268 } 269 270 /// getTypeAction - Return how we should legalize values of this type, either 271 /// it is already legal (return 'Legal') or we need to promote it to a larger 272 /// type (return 'Promote'), or we need to expand it into multiple registers 273 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 274 LegalizeAction getTypeAction(EVT VT) const { 275 return ValueTypeActions.getTypeAction(VT); 276 } 277 LegalizeAction getTypeAction(MVT VT) const { 278 return ValueTypeActions.getTypeAction(VT); 279 } 280 281 /// getTypeToTransformTo - For types supported by the target, this is an 282 /// identity function. For types that must be promoted to larger types, this 283 /// returns the larger type to promote to. For integer types that are larger 284 /// than the largest integer register, this contains one step in the expansion 285 /// to get to the smaller register. For illegal floating point types, this 286 /// returns the integer type to transform to. 287 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 288 if (VT.isSimple()) { 289 assert((unsigned)VT.getSimpleVT().SimpleTy < 290 array_lengthof(TransformToType)); 291 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 292 assert(getTypeAction(NVT) != Promote && 293 "Promote may not follow Expand or Promote"); 294 return NVT; 295 } 296 297 if (VT.isVector()) { 298 EVT NVT = VT.getPow2VectorType(Context); 299 if (NVT == VT) { 300 // Vector length is a power of 2 - split to half the size. 301 unsigned NumElts = VT.getVectorNumElements(); 302 EVT EltVT = VT.getVectorElementType(); 303 return (NumElts == 1) ? 304 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 305 } 306 // Promote to a power of two size, avoiding multi-step promotion. 307 return getTypeAction(NVT) == Promote ? 308 getTypeToTransformTo(Context, NVT) : NVT; 309 } else if (VT.isInteger()) { 310 EVT NVT = VT.getRoundIntegerType(Context); 311 if (NVT == VT) // Size is a power of two - expand to half the size. 312 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 313 314 // Promote to a power of two size, avoiding multi-step promotion. 315 return getTypeAction(NVT) == Promote ? 316 getTypeToTransformTo(Context, NVT) : NVT; 317 } 318 assert(0 && "Unsupported extended type!"); 319 return MVT(MVT::Other); // Not reached 320 } 321 322 /// getTypeToExpandTo - For types supported by the target, this is an 323 /// identity function. For types that must be expanded (i.e. integer types 324 /// that are larger than the largest integer register or illegal floating 325 /// point types), this returns the largest legal type it will be expanded to. 326 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 327 assert(!VT.isVector()); 328 while (true) { 329 switch (getTypeAction(VT)) { 330 case Legal: 331 return VT; 332 case Expand: 333 VT = getTypeToTransformTo(Context, VT); 334 break; 335 default: 336 assert(false && "Type is not legal nor is it to be expanded!"); 337 return VT; 338 } 339 } 340 return VT; 341 } 342 343 /// getVectorTypeBreakdown - Vector types are broken down into some number of 344 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 345 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 346 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 347 /// 348 /// This method returns the number of registers needed, and the VT for each 349 /// register. It also returns the VT and quantity of the intermediate values 350 /// before they are promoted/expanded. 351 /// 352 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 353 EVT &IntermediateVT, 354 unsigned &NumIntermediates, 355 EVT &RegisterVT) const; 356 357 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 358 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 359 /// this is the case, it returns true and store the intrinsic 360 /// information into the IntrinsicInfo that was passed to the function. 361 struct IntrinsicInfo { 362 unsigned opc; // target opcode 363 EVT memVT; // memory VT 364 const Value* ptrVal; // value representing memory location 365 int offset; // offset off of ptrVal 366 unsigned align; // alignment 367 bool vol; // is volatile? 368 bool readMem; // reads memory? 369 bool writeMem; // writes memory? 370 }; 371 372 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 373 const CallInst &I, unsigned Intrinsic) const { 374 return false; 375 } 376 377 /// isFPImmLegal - Returns true if the target can instruction select the 378 /// specified FP immediate natively. If false, the legalizer will materialize 379 /// the FP immediate as a load from a constant pool. 380 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 381 return false; 382 } 383 384 /// isShuffleMaskLegal - Targets can use this to indicate that they only 385 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 386 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 387 /// are assumed to be legal. 388 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 389 EVT VT) const { 390 return true; 391 } 392 393 /// canOpTrap - Returns true if the operation can trap for the value type. 394 /// VT must be a legal type. By default, we optimistically assume most 395 /// operations don't trap except for divide and remainder. 396 virtual bool canOpTrap(unsigned Op, EVT VT) const; 397 398 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 399 /// used by Targets can use this to indicate if there is a suitable 400 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 401 /// pool entry. 402 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 403 EVT VT) const { 404 return false; 405 } 406 407 /// getOperationAction - Return how this operation should be treated: either 408 /// it is legal, needs to be promoted to a larger size, needs to be 409 /// expanded to some other code sequence, or the target has a custom expander 410 /// for it. 411 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 412 if (VT.isExtended()) return Expand; 413 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 414 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 415 return (LegalizeAction)OpActions[I][Op]; 416 } 417 418 /// isOperationLegalOrCustom - Return true if the specified operation is 419 /// legal on this target or can be made legal with custom lowering. This 420 /// is used to help guide high-level lowering decisions. 421 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 422 return (VT == MVT::Other || isTypeLegal(VT)) && 423 (getOperationAction(Op, VT) == Legal || 424 getOperationAction(Op, VT) == Custom); 425 } 426 427 /// isOperationLegal - Return true if the specified operation is legal on this 428 /// target. 429 bool isOperationLegal(unsigned Op, EVT VT) const { 430 return (VT == MVT::Other || isTypeLegal(VT)) && 431 getOperationAction(Op, VT) == Legal; 432 } 433 434 /// getLoadExtAction - Return how this load with extension should be treated: 435 /// either it is legal, needs to be promoted to a larger size, needs to be 436 /// expanded to some other code sequence, or the target has a custom expander 437 /// for it. 438 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 439 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 440 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 441 "Table isn't big enough!"); 442 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 443 } 444 445 /// isLoadExtLegal - Return true if the specified load with extension is legal 446 /// on this target. 447 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 448 return VT.isSimple() && 449 (getLoadExtAction(ExtType, VT) == Legal || 450 getLoadExtAction(ExtType, VT) == Custom); 451 } 452 453 /// getTruncStoreAction - Return how this store with truncation should be 454 /// treated: either it is legal, needs to be promoted to a larger size, needs 455 /// to be expanded to some other code sequence, or the target has a custom 456 /// expander for it. 457 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 458 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE && 459 MemVT.getSimpleVT() < MVT::LAST_VALUETYPE && 460 "Table isn't big enough!"); 461 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 462 [MemVT.getSimpleVT().SimpleTy]; 463 } 464 465 /// isTruncStoreLegal - Return true if the specified store with truncation is 466 /// legal on this target. 467 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 468 return isTypeLegal(ValVT) && MemVT.isSimple() && 469 (getTruncStoreAction(ValVT, MemVT) == Legal || 470 getTruncStoreAction(ValVT, MemVT) == Custom); 471 } 472 473 /// getIndexedLoadAction - Return how the indexed load should be treated: 474 /// either it is legal, needs to be promoted to a larger size, needs to be 475 /// expanded to some other code sequence, or the target has a custom expander 476 /// for it. 477 LegalizeAction 478 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 479 assert(IdxMode < ISD::LAST_INDEXED_MODE && 480 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 481 "Table isn't big enough!"); 482 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 483 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 484 } 485 486 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 487 /// on this target. 488 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 489 return VT.isSimple() && 490 (getIndexedLoadAction(IdxMode, VT) == Legal || 491 getIndexedLoadAction(IdxMode, VT) == Custom); 492 } 493 494 /// getIndexedStoreAction - Return how the indexed store should be treated: 495 /// either it is legal, needs to be promoted to a larger size, needs to be 496 /// expanded to some other code sequence, or the target has a custom expander 497 /// for it. 498 LegalizeAction 499 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 500 assert(IdxMode < ISD::LAST_INDEXED_MODE && 501 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 502 "Table isn't big enough!"); 503 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 504 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 505 } 506 507 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 508 /// on this target. 509 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 510 return VT.isSimple() && 511 (getIndexedStoreAction(IdxMode, VT) == Legal || 512 getIndexedStoreAction(IdxMode, VT) == Custom); 513 } 514 515 /// getCondCodeAction - Return how the condition code should be treated: 516 /// either it is legal, needs to be expanded to some other code sequence, 517 /// or the target has a custom expander for it. 518 LegalizeAction 519 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 520 assert((unsigned)CC < array_lengthof(CondCodeActions) && 521 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 522 "Table isn't big enough!"); 523 LegalizeAction Action = (LegalizeAction) 524 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 525 assert(Action != Promote && "Can't promote condition code!"); 526 return Action; 527 } 528 529 /// isCondCodeLegal - Return true if the specified condition code is legal 530 /// on this target. 531 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 532 return getCondCodeAction(CC, VT) == Legal || 533 getCondCodeAction(CC, VT) == Custom; 534 } 535 536 537 /// getTypeToPromoteTo - If the action for this operation is to promote, this 538 /// method returns the ValueType to promote to. 539 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 540 assert(getOperationAction(Op, VT) == Promote && 541 "This operation isn't promoted!"); 542 543 // See if this has an explicit type specified. 544 std::map<std::pair<unsigned, MVT::SimpleValueType>, 545 MVT::SimpleValueType>::const_iterator PTTI = 546 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 547 if (PTTI != PromoteToType.end()) return PTTI->second; 548 549 assert((VT.isInteger() || VT.isFloatingPoint()) && 550 "Cannot autopromote this type, add it with AddPromotedToType."); 551 552 EVT NVT = VT; 553 do { 554 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 555 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 556 "Didn't find type to promote to!"); 557 } while (!isTypeLegal(NVT) || 558 getOperationAction(Op, NVT) == Promote); 559 return NVT; 560 } 561 562 /// getValueType - Return the EVT corresponding to this LLVM type. 563 /// This is fixed by the LLVM operations except for the pointer size. If 564 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 565 /// counterpart (e.g. structs), otherwise it will assert. 566 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 567 EVT VT = EVT::getEVT(Ty, AllowUnknown); 568 return VT == MVT::iPTR ? PointerTy : VT; 569 } 570 571 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 572 /// function arguments in the caller parameter area. This is the actual 573 /// alignment, not its logarithm. 574 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 575 576 /// getRegisterType - Return the type of registers that this ValueType will 577 /// eventually require. 578 EVT getRegisterType(MVT VT) const { 579 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 580 return RegisterTypeForVT[VT.SimpleTy]; 581 } 582 583 /// getRegisterType - Return the type of registers that this ValueType will 584 /// eventually require. 585 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 586 if (VT.isSimple()) { 587 assert((unsigned)VT.getSimpleVT().SimpleTy < 588 array_lengthof(RegisterTypeForVT)); 589 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 590 } 591 if (VT.isVector()) { 592 EVT VT1, RegisterVT; 593 unsigned NumIntermediates; 594 (void)getVectorTypeBreakdown(Context, VT, VT1, 595 NumIntermediates, RegisterVT); 596 return RegisterVT; 597 } 598 if (VT.isInteger()) { 599 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 600 } 601 assert(0 && "Unsupported extended type!"); 602 return EVT(MVT::Other); // Not reached 603 } 604 605 /// getNumRegisters - Return the number of registers that this ValueType will 606 /// eventually require. This is one for any types promoted to live in larger 607 /// registers, but may be more than one for types (like i64) that are split 608 /// into pieces. For types like i140, which are first promoted then expanded, 609 /// it is the number of registers needed to hold all the bits of the original 610 /// type. For an i140 on a 32 bit machine this means 5 registers. 611 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 612 if (VT.isSimple()) { 613 assert((unsigned)VT.getSimpleVT().SimpleTy < 614 array_lengthof(NumRegistersForVT)); 615 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 616 } 617 if (VT.isVector()) { 618 EVT VT1, VT2; 619 unsigned NumIntermediates; 620 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 621 } 622 if (VT.isInteger()) { 623 unsigned BitWidth = VT.getSizeInBits(); 624 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 625 return (BitWidth + RegWidth - 1) / RegWidth; 626 } 627 assert(0 && "Unsupported extended type!"); 628 return 0; // Not reached 629 } 630 631 /// ShouldShrinkFPConstant - If true, then instruction selection should 632 /// seek to shrink the FP constant of the specified type to a smaller type 633 /// in order to save space and / or reduce runtime. 634 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 635 636 /// hasTargetDAGCombine - If true, the target has custom DAG combine 637 /// transformations that it can perform for the specified node. 638 bool hasTargetDAGCombine(ISD::NodeType NT) const { 639 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 640 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 641 } 642 643 /// This function returns the maximum number of store operations permitted 644 /// to replace a call to llvm.memset. The value is set by the target at the 645 /// performance threshold for such a replacement. If OptSize is true, 646 /// return the limit for functions that have OptSize attribute. 647 /// @brief Get maximum # of store operations permitted for llvm.memset 648 unsigned getMaxStoresPerMemset(bool OptSize) const { 649 return OptSize ? maxStoresPerMemsetOptSize : maxStoresPerMemset; 650 } 651 652 /// This function returns the maximum number of store operations permitted 653 /// to replace a call to llvm.memcpy. The value is set by the target at the 654 /// performance threshold for such a replacement. If OptSize is true, 655 /// return the limit for functions that have OptSize attribute. 656 /// @brief Get maximum # of store operations permitted for llvm.memcpy 657 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 658 return OptSize ? maxStoresPerMemcpyOptSize : maxStoresPerMemcpy; 659 } 660 661 /// This function returns the maximum number of store operations permitted 662 /// to replace a call to llvm.memmove. The value is set by the target at the 663 /// performance threshold for such a replacement. If OptSize is true, 664 /// return the limit for functions that have OptSize attribute. 665 /// @brief Get maximum # of store operations permitted for llvm.memmove 666 unsigned getMaxStoresPerMemmove(bool OptSize) const { 667 return OptSize ? maxStoresPerMemmoveOptSize : maxStoresPerMemmove; 668 } 669 670 /// This function returns true if the target allows unaligned memory accesses. 671 /// of the specified type. This is used, for example, in situations where an 672 /// array copy/move/set is converted to a sequence of store operations. It's 673 /// use helps to ensure that such replacements don't generate code that causes 674 /// an alignment error (trap) on the target machine. 675 /// @brief Determine if the target supports unaligned memory accesses. 676 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 677 return false; 678 } 679 680 /// This function returns true if the target would benefit from code placement 681 /// optimization. 682 /// @brief Determine if the target should perform code placement optimization. 683 bool shouldOptimizeCodePlacement() const { 684 return benefitFromCodePlacementOpt; 685 } 686 687 /// getOptimalMemOpType - Returns the target specific optimal type for load 688 /// and store operations as a result of memset, memcpy, and memmove 689 /// lowering. If DstAlign is zero that means it's safe to destination 690 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 691 /// means there isn't a need to check it against alignment requirement, 692 /// probably because the source does not need to be loaded. If 693 /// 'NonScalarIntSafe' is true, that means it's safe to return a 694 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 695 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 696 /// constant so it does not need to be loaded. 697 /// It returns EVT::Other if the type should be determined using generic 698 /// target-independent logic. 699 virtual EVT getOptimalMemOpType(uint64_t Size, 700 unsigned DstAlign, unsigned SrcAlign, 701 bool NonScalarIntSafe, bool MemcpyStrSrc, 702 MachineFunction &MF) const { 703 return MVT::Other; 704 } 705 706 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 707 /// to implement llvm.setjmp. 708 bool usesUnderscoreSetJmp() const { 709 return UseUnderscoreSetJmp; 710 } 711 712 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 713 /// to implement llvm.longjmp. 714 bool usesUnderscoreLongJmp() const { 715 return UseUnderscoreLongJmp; 716 } 717 718 /// getStackPointerRegisterToSaveRestore - If a physical register, this 719 /// specifies the register that llvm.savestack/llvm.restorestack should save 720 /// and restore. 721 unsigned getStackPointerRegisterToSaveRestore() const { 722 return StackPointerRegisterToSaveRestore; 723 } 724 725 /// getExceptionAddressRegister - If a physical register, this returns 726 /// the register that receives the exception address on entry to a landing 727 /// pad. 728 unsigned getExceptionAddressRegister() const { 729 return ExceptionPointerRegister; 730 } 731 732 /// getExceptionSelectorRegister - If a physical register, this returns 733 /// the register that receives the exception typeid on entry to a landing 734 /// pad. 735 unsigned getExceptionSelectorRegister() const { 736 return ExceptionSelectorRegister; 737 } 738 739 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 740 /// set, the default is 200) 741 unsigned getJumpBufSize() const { 742 return JumpBufSize; 743 } 744 745 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 746 /// (if never set, the default is 0) 747 unsigned getJumpBufAlignment() const { 748 return JumpBufAlignment; 749 } 750 751 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 752 /// argument. 753 unsigned getMinStackArgumentAlignment() const { 754 return MinStackArgumentAlignment; 755 } 756 757 /// getPrefLoopAlignment - return the preferred loop alignment. 758 /// 759 unsigned getPrefLoopAlignment() const { 760 return PrefLoopAlignment; 761 } 762 763 /// getShouldFoldAtomicFences - return whether the combiner should fold 764 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 765 /// 766 bool getShouldFoldAtomicFences() const { 767 return ShouldFoldAtomicFences; 768 } 769 770 /// getPreIndexedAddressParts - returns true by value, base pointer and 771 /// offset pointer and addressing mode by reference if the node's address 772 /// can be legally represented as pre-indexed load / store address. 773 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 774 SDValue &Offset, 775 ISD::MemIndexedMode &AM, 776 SelectionDAG &DAG) const { 777 return false; 778 } 779 780 /// getPostIndexedAddressParts - returns true by value, base pointer and 781 /// offset pointer and addressing mode by reference if this node can be 782 /// combined with a load / store to form a post-indexed load / store. 783 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 784 SDValue &Base, SDValue &Offset, 785 ISD::MemIndexedMode &AM, 786 SelectionDAG &DAG) const { 787 return false; 788 } 789 790 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 791 /// current function. The returned value is a member of the 792 /// MachineJumpTableInfo::JTEntryKind enum. 793 virtual unsigned getJumpTableEncoding() const; 794 795 virtual const MCExpr * 796 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 797 const MachineBasicBlock *MBB, unsigned uid, 798 MCContext &Ctx) const { 799 assert(0 && "Need to implement this hook if target has custom JTIs"); 800 return 0; 801 } 802 803 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 804 /// jumptable. 805 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 806 SelectionDAG &DAG) const; 807 808 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 809 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 810 /// MCExpr. 811 virtual const MCExpr * 812 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 813 unsigned JTI, MCContext &Ctx) const; 814 815 /// isOffsetFoldingLegal - Return true if folding a constant offset 816 /// with the given GlobalAddress is legal. It is frequently not legal in 817 /// PIC relocation models. 818 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 819 820 /// getFunctionAlignment - Return the Log2 alignment of this function. 821 virtual unsigned getFunctionAlignment(const Function *) const = 0; 822 823 /// getStackCookieLocation - Return true if the target stores stack 824 /// protector cookies at a fixed offset in some non-standard address 825 /// space, and populates the address space and offset as 826 /// appropriate. 827 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const { 828 return false; 829 } 830 831 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 832 /// used for loads / stores from the global. 833 virtual unsigned getMaximalGlobalOffset() const { 834 return 0; 835 } 836 837 //===--------------------------------------------------------------------===// 838 // TargetLowering Optimization Methods 839 // 840 841 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 842 /// SDValues for returning information from TargetLowering to its clients 843 /// that want to combine 844 struct TargetLoweringOpt { 845 SelectionDAG &DAG; 846 bool LegalTys; 847 bool LegalOps; 848 SDValue Old; 849 SDValue New; 850 851 explicit TargetLoweringOpt(SelectionDAG &InDAG, 852 bool LT, bool LO) : 853 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 854 855 bool LegalTypes() const { return LegalTys; } 856 bool LegalOperations() const { return LegalOps; } 857 858 bool CombineTo(SDValue O, SDValue N) { 859 Old = O; 860 New = N; 861 return true; 862 } 863 864 /// ShrinkDemandedConstant - Check to see if the specified operand of the 865 /// specified instruction is a constant integer. If so, check to see if 866 /// there are any bits set in the constant that are not demanded. If so, 867 /// shrink the constant and return true. 868 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 869 870 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 871 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 872 /// cast, but it could be generalized for targets with other types of 873 /// implicit widening casts. 874 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 875 DebugLoc dl); 876 }; 877 878 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 879 /// DemandedMask bits of the result of Op are ever used downstream. If we can 880 /// use this information to simplify Op, create a new simplified DAG node and 881 /// return true, returning the original and new nodes in Old and New. 882 /// Otherwise, analyze the expression and return a mask of KnownOne and 883 /// KnownZero bits for the expression (used to simplify the caller). 884 /// The KnownZero/One bits may only be accurate for those bits in the 885 /// DemandedMask. 886 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 887 APInt &KnownZero, APInt &KnownOne, 888 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 889 890 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 891 /// Mask are known to be either zero or one and return them in the 892 /// KnownZero/KnownOne bitsets. 893 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 894 const APInt &Mask, 895 APInt &KnownZero, 896 APInt &KnownOne, 897 const SelectionDAG &DAG, 898 unsigned Depth = 0) const; 899 900 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 901 /// targets that want to expose additional information about sign bits to the 902 /// DAG Combiner. 903 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 904 unsigned Depth = 0) const; 905 906 struct DAGCombinerInfo { 907 void *DC; // The DAG Combiner object. 908 bool BeforeLegalize; 909 bool BeforeLegalizeOps; 910 bool CalledByLegalizer; 911 public: 912 SelectionDAG &DAG; 913 914 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 915 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 916 CalledByLegalizer(cl), DAG(dag) {} 917 918 bool isBeforeLegalize() const { return BeforeLegalize; } 919 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 920 bool isCalledByLegalizer() const { return CalledByLegalizer; } 921 922 void AddToWorklist(SDNode *N); 923 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 924 bool AddTo = true); 925 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 926 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 927 928 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 929 }; 930 931 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 932 /// and cc. If it is unable to simplify it, return a null SDValue. 933 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 934 ISD::CondCode Cond, bool foldBooleans, 935 DAGCombinerInfo &DCI, DebugLoc dl) const; 936 937 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 938 /// node is a GlobalAddress + offset. 939 virtual bool 940 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 941 942 /// PerformDAGCombine - This method will be invoked for all target nodes and 943 /// for any target-independent nodes that the target has registered with 944 /// invoke it for. 945 /// 946 /// The semantics are as follows: 947 /// Return Value: 948 /// SDValue.Val == 0 - No change was made 949 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 950 /// otherwise - N should be replaced by the returned Operand. 951 /// 952 /// In addition, methods provided by DAGCombinerInfo may be used to perform 953 /// more complex transformations. 954 /// 955 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 956 957 /// isTypeDesirableForOp - Return true if the target has native support for 958 /// the specified value type and it is 'desirable' to use the type for the 959 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 960 /// instruction encodings are longer and some i16 instructions are slow. 961 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const { 962 // By default, assume all legal types are desirable. 963 return isTypeLegal(VT); 964 } 965 966 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner 967 /// to transform a floating point op of specified opcode to a equivalent op of 968 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM. 969 virtual bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const { 970 return false; 971 } 972 973 /// IsDesirableToPromoteOp - This method query the target whether it is 974 /// beneficial for dag combiner to promote the specified node. If true, it 975 /// should return the desired promotion type by reference. 976 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 977 return false; 978 } 979 980 //===--------------------------------------------------------------------===// 981 // TargetLowering Configuration Methods - These methods should be invoked by 982 // the derived class constructor to configure this object for the target. 983 // 984 985protected: 986 /// setShiftAmountType - Describe the type that should be used for shift 987 /// amounts. This type defaults to the pointer type. 988 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 989 990 /// setBooleanContents - Specify how the target extends the result of a 991 /// boolean value from i1 to a wider type. See getBooleanContents. 992 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 993 994 /// setSchedulingPreference - Specify the target scheduling preference. 995 void setSchedulingPreference(Sched::Preference Pref) { 996 SchedPreferenceInfo = Pref; 997 } 998 999 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 1000 /// use _setjmp to implement llvm.setjmp or the non _ version. 1001 /// Defaults to false. 1002 void setUseUnderscoreSetJmp(bool Val) { 1003 UseUnderscoreSetJmp = Val; 1004 } 1005 1006 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 1007 /// use _longjmp to implement llvm.longjmp or the non _ version. 1008 /// Defaults to false. 1009 void setUseUnderscoreLongJmp(bool Val) { 1010 UseUnderscoreLongJmp = Val; 1011 } 1012 1013 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 1014 /// specifies the register that llvm.savestack/llvm.restorestack should save 1015 /// and restore. 1016 void setStackPointerRegisterToSaveRestore(unsigned R) { 1017 StackPointerRegisterToSaveRestore = R; 1018 } 1019 1020 /// setExceptionPointerRegister - If set to a physical register, this sets 1021 /// the register that receives the exception address on entry to a landing 1022 /// pad. 1023 void setExceptionPointerRegister(unsigned R) { 1024 ExceptionPointerRegister = R; 1025 } 1026 1027 /// setExceptionSelectorRegister - If set to a physical register, this sets 1028 /// the register that receives the exception typeid on entry to a landing 1029 /// pad. 1030 void setExceptionSelectorRegister(unsigned R) { 1031 ExceptionSelectorRegister = R; 1032 } 1033 1034 /// SelectIsExpensive - Tells the code generator not to expand operations 1035 /// into sequences that use the select operations if possible. 1036 void setSelectIsExpensive(bool isExpensive = true) { 1037 SelectIsExpensive = isExpensive; 1038 } 1039 1040 /// JumpIsExpensive - Tells the code generator not to expand sequence of 1041 /// operations into a seperate sequences that increases the amount of 1042 /// flow control. 1043 void setJumpIsExpensive(bool isExpensive = true) { 1044 JumpIsExpensive = isExpensive; 1045 } 1046 1047 /// setIntDivIsCheap - Tells the code generator that integer divide is 1048 /// expensive, and if possible, should be replaced by an alternate sequence 1049 /// of instructions not containing an integer divide. 1050 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 1051 1052 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 1053 /// srl/add/sra for a signed divide by power of two, and let the target handle 1054 /// it. 1055 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 1056 1057 /// addRegisterClass - Add the specified register class as an available 1058 /// regclass for the specified value type. This indicates the selector can 1059 /// handle values of that class natively. 1060 void addRegisterClass(EVT VT, TargetRegisterClass *RC) { 1061 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 1062 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 1063 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 1064 } 1065 1066 /// findRepresentativeClass - Return the largest legal super-reg register class 1067 /// of the register class for the specified type and its associated "cost". 1068 virtual std::pair<const TargetRegisterClass*, uint8_t> 1069 findRepresentativeClass(EVT VT) const; 1070 1071 /// computeRegisterProperties - Once all of the register classes are added, 1072 /// this allows us to compute derived properties we expose. 1073 void computeRegisterProperties(); 1074 1075 /// setOperationAction - Indicate that the specified operation does not work 1076 /// with the specified type and indicate what to do about it. 1077 void setOperationAction(unsigned Op, MVT VT, 1078 LegalizeAction Action) { 1079 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 1080 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 1081 } 1082 1083 /// setLoadExtAction - Indicate that the specified load with extension does 1084 /// not work with the specified type and indicate what to do about it. 1085 void setLoadExtAction(unsigned ExtType, MVT VT, 1086 LegalizeAction Action) { 1087 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 1088 "Table isn't big enough!"); 1089 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 1090 } 1091 1092 /// setTruncStoreAction - Indicate that the specified truncating store does 1093 /// not work with the specified type and indicate what to do about it. 1094 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1095 LegalizeAction Action) { 1096 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 1097 "Table isn't big enough!"); 1098 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1099 } 1100 1101 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1102 /// does not work with the specified type and indicate what to do abort 1103 /// it. NOTE: All indexed mode loads are initialized to Expand in 1104 /// TargetLowering.cpp 1105 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1106 LegalizeAction Action) { 1107 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1108 (unsigned)Action < 0xf && "Table isn't big enough!"); 1109 // Load action are kept in the upper half. 1110 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1111 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1112 } 1113 1114 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1115 /// does not work with the specified type and indicate what to do about 1116 /// it. NOTE: All indexed mode stores are initialized to Expand in 1117 /// TargetLowering.cpp 1118 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1119 LegalizeAction Action) { 1120 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1121 (unsigned)Action < 0xf && "Table isn't big enough!"); 1122 // Store action are kept in the lower half. 1123 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1124 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1125 } 1126 1127 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1128 /// supported on the target and indicate what to do about it. 1129 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1130 LegalizeAction Action) { 1131 assert(VT < MVT::LAST_VALUETYPE && 1132 (unsigned)CC < array_lengthof(CondCodeActions) && 1133 "Table isn't big enough!"); 1134 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1135 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1136 } 1137 1138 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1139 /// promotion code defaults to trying a larger integer/fp until it can find 1140 /// one that works. If that default is insufficient, this method can be used 1141 /// by the target to override the default. 1142 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1143 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1144 } 1145 1146 /// setTargetDAGCombine - Targets should invoke this method for each target 1147 /// independent node that they want to provide a custom DAG combiner for by 1148 /// implementing the PerformDAGCombine virtual method. 1149 void setTargetDAGCombine(ISD::NodeType NT) { 1150 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1151 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1152 } 1153 1154 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1155 /// bytes); default is 200 1156 void setJumpBufSize(unsigned Size) { 1157 JumpBufSize = Size; 1158 } 1159 1160 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1161 /// alignment (in bytes); default is 0 1162 void setJumpBufAlignment(unsigned Align) { 1163 JumpBufAlignment = Align; 1164 } 1165 1166 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1167 /// alignment is zero, it means the target does not care about loop alignment. 1168 void setPrefLoopAlignment(unsigned Align) { 1169 PrefLoopAlignment = Align; 1170 } 1171 1172 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1173 /// argument. 1174 void setMinStackArgumentAlignment(unsigned Align) { 1175 MinStackArgumentAlignment = Align; 1176 } 1177 1178 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1179 /// atomic operation intrinsics includes locking. Default is false. 1180 void setShouldFoldAtomicFences(bool fold) { 1181 ShouldFoldAtomicFences = fold; 1182 } 1183 1184public: 1185 //===--------------------------------------------------------------------===// 1186 // Lowering methods - These methods must be implemented by targets so that 1187 // the SelectionDAGLowering code knows how to lower these. 1188 // 1189 1190 /// LowerFormalArguments - This hook must be implemented to lower the 1191 /// incoming (formal) arguments, described by the Ins array, into the 1192 /// specified DAG. The implementation should fill in the InVals array 1193 /// with legal-type argument values, and return the resulting token 1194 /// chain value. 1195 /// 1196 virtual SDValue 1197 LowerFormalArguments(SDValue Chain, 1198 CallingConv::ID CallConv, bool isVarArg, 1199 const SmallVectorImpl<ISD::InputArg> &Ins, 1200 DebugLoc dl, SelectionDAG &DAG, 1201 SmallVectorImpl<SDValue> &InVals) const { 1202 assert(0 && "Not Implemented"); 1203 return SDValue(); // this is here to silence compiler errors 1204 } 1205 1206 /// LowerCallTo - This function lowers an abstract call to a function into an 1207 /// actual call. This returns a pair of operands. The first element is the 1208 /// return value for the function (if RetTy is not VoidTy). The second 1209 /// element is the outgoing token chain. It calls LowerCall to do the actual 1210 /// lowering. 1211 struct ArgListEntry { 1212 SDValue Node; 1213 const Type* Ty; 1214 bool isSExt : 1; 1215 bool isZExt : 1; 1216 bool isInReg : 1; 1217 bool isSRet : 1; 1218 bool isNest : 1; 1219 bool isByVal : 1; 1220 uint16_t Alignment; 1221 1222 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1223 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1224 }; 1225 typedef std::vector<ArgListEntry> ArgListTy; 1226 std::pair<SDValue, SDValue> 1227 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1228 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1229 CallingConv::ID CallConv, bool isTailCall, 1230 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1231 SelectionDAG &DAG, DebugLoc dl) const; 1232 1233 /// LowerCall - This hook must be implemented to lower calls into the 1234 /// the specified DAG. The outgoing arguments to the call are described 1235 /// by the Outs array, and the values to be returned by the call are 1236 /// described by the Ins array. The implementation should fill in the 1237 /// InVals array with legal-type return values from the call, and return 1238 /// the resulting token chain value. 1239 virtual SDValue 1240 LowerCall(SDValue Chain, SDValue Callee, 1241 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 1242 const SmallVectorImpl<ISD::OutputArg> &Outs, 1243 const SmallVectorImpl<SDValue> &OutVals, 1244 const SmallVectorImpl<ISD::InputArg> &Ins, 1245 DebugLoc dl, SelectionDAG &DAG, 1246 SmallVectorImpl<SDValue> &InVals) const { 1247 assert(0 && "Not Implemented"); 1248 return SDValue(); // this is here to silence compiler errors 1249 } 1250 1251 /// CanLowerReturn - This hook should be implemented to check whether the 1252 /// return values described by the Outs array can fit into the return 1253 /// registers. If false is returned, an sret-demotion is performed. 1254 /// 1255 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1256 const SmallVectorImpl<ISD::OutputArg> &Outs, 1257 LLVMContext &Context) const 1258 { 1259 // Return true by default to get preexisting behavior. 1260 return true; 1261 } 1262 1263 /// LowerReturn - This hook must be implemented to lower outgoing 1264 /// return values, described by the Outs array, into the specified 1265 /// DAG. The implementation should return the resulting token chain 1266 /// value. 1267 /// 1268 virtual SDValue 1269 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1270 const SmallVectorImpl<ISD::OutputArg> &Outs, 1271 const SmallVectorImpl<SDValue> &OutVals, 1272 DebugLoc dl, SelectionDAG &DAG) const { 1273 assert(0 && "Not Implemented"); 1274 return SDValue(); // this is here to silence compiler errors 1275 } 1276 1277 /// isUsedByReturnOnly - Return true if result of the specified node is used 1278 /// by a return node only. This is used to determine whether it is possible 1279 /// to codegen a libcall as tail call at legalization time. 1280 virtual bool isUsedByReturnOnly(SDNode *N) const { 1281 return false; 1282 } 1283 1284 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1285 /// to legalize nodes with an illegal operand type but legal result types. 1286 /// It replaces the LowerOperation callback in the type Legalizer. 1287 /// The reason we can not do away with LowerOperation entirely is that 1288 /// LegalizeDAG isn't yet ready to use this callback. 1289 /// TODO: Consider merging with ReplaceNodeResults. 1290 1291 /// The target places new result values for the node in Results (their number 1292 /// and types must exactly match those of the original return values of 1293 /// the node), or leaves Results empty, which indicates that the node is not 1294 /// to be custom lowered after all. 1295 /// The default implementation calls LowerOperation. 1296 virtual void LowerOperationWrapper(SDNode *N, 1297 SmallVectorImpl<SDValue> &Results, 1298 SelectionDAG &DAG) const; 1299 1300 /// LowerOperation - This callback is invoked for operations that are 1301 /// unsupported by the target, which are registered to use 'custom' lowering, 1302 /// and whose defined values are all legal. 1303 /// If the target has no operations that require custom lowering, it need not 1304 /// implement this. The default implementation of this aborts. 1305 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1306 1307 /// ReplaceNodeResults - This callback is invoked when a node result type is 1308 /// illegal for the target, and the operation was registered to use 'custom' 1309 /// lowering for that result type. The target places new result values for 1310 /// the node in Results (their number and types must exactly match those of 1311 /// the original return values of the node), or leaves Results empty, which 1312 /// indicates that the node is not to be custom lowered after all. 1313 /// 1314 /// If the target has no operations that require custom lowering, it need not 1315 /// implement this. The default implementation aborts. 1316 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1317 SelectionDAG &DAG) const { 1318 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1319 } 1320 1321 /// getTargetNodeName() - This method returns the name of a target specific 1322 /// DAG node. 1323 virtual const char *getTargetNodeName(unsigned Opcode) const; 1324 1325 /// createFastISel - This method returns a target specific FastISel object, 1326 /// or null if the target does not support "fast" ISel. 1327 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const { 1328 return 0; 1329 } 1330 1331 //===--------------------------------------------------------------------===// 1332 // Inline Asm Support hooks 1333 // 1334 1335 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1336 /// call to be explicit llvm code if it wants to. This is useful for 1337 /// turning simple inline asms into LLVM intrinsics, which gives the 1338 /// compiler more information about the behavior of the code. 1339 virtual bool ExpandInlineAsm(CallInst *CI) const { 1340 return false; 1341 } 1342 1343 enum ConstraintType { 1344 C_Register, // Constraint represents specific register(s). 1345 C_RegisterClass, // Constraint represents any of register(s) in class. 1346 C_Memory, // Memory constraint. 1347 C_Other, // Something else. 1348 C_Unknown // Unsupported constraint. 1349 }; 1350 1351 enum ConstraintWeight { 1352 // Generic weights. 1353 CW_Invalid = -1, // No match. 1354 CW_Okay = 0, // Acceptable. 1355 CW_Good = 1, // Good weight. 1356 CW_Better = 2, // Better weight. 1357 CW_Best = 3, // Best weight. 1358 1359 // Well-known weights. 1360 CW_SpecificReg = CW_Okay, // Specific register operands. 1361 CW_Register = CW_Good, // Register operands. 1362 CW_Memory = CW_Better, // Memory operands. 1363 CW_Constant = CW_Best, // Constant operand. 1364 CW_Default = CW_Okay // Default or don't know type. 1365 }; 1366 1367 /// AsmOperandInfo - This contains information for each constraint that we are 1368 /// lowering. 1369 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1370 /// ConstraintCode - This contains the actual string for the code, like "m". 1371 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1372 /// most closely matches the operand. 1373 std::string ConstraintCode; 1374 1375 /// ConstraintType - Information about the constraint code, e.g. Register, 1376 /// RegisterClass, Memory, Other, Unknown. 1377 TargetLowering::ConstraintType ConstraintType; 1378 1379 /// CallOperandval - If this is the result output operand or a 1380 /// clobber, this is null, otherwise it is the incoming operand to the 1381 /// CallInst. This gets modified as the asm is processed. 1382 Value *CallOperandVal; 1383 1384 /// ConstraintVT - The ValueType for the operand value. 1385 EVT ConstraintVT; 1386 1387 /// isMatchingInputConstraint - Return true of this is an input operand that 1388 /// is a matching constraint like "4". 1389 bool isMatchingInputConstraint() const; 1390 1391 /// getMatchedOperand - If this is an input matching constraint, this method 1392 /// returns the output operand it matches. 1393 unsigned getMatchedOperand() const; 1394 1395 /// Copy constructor for copying from an AsmOperandInfo. 1396 AsmOperandInfo(const AsmOperandInfo &info) 1397 : InlineAsm::ConstraintInfo(info), 1398 ConstraintCode(info.ConstraintCode), 1399 ConstraintType(info.ConstraintType), 1400 CallOperandVal(info.CallOperandVal), 1401 ConstraintVT(info.ConstraintVT) { 1402 } 1403 1404 /// Copy constructor for copying from a ConstraintInfo. 1405 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1406 : InlineAsm::ConstraintInfo(info), 1407 ConstraintType(TargetLowering::C_Unknown), 1408 CallOperandVal(0), ConstraintVT(MVT::Other) { 1409 } 1410 }; 1411 1412 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 1413 1414 /// ParseConstraints - Split up the constraint string from the inline 1415 /// assembly value into the specific constraints and their prefixes, 1416 /// and also tie in the associated operand values. 1417 /// If this returns an empty vector, and if the constraint string itself 1418 /// isn't empty, there was an error parsing. 1419 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 1420 1421 /// Examine constraint type and operand type and determine a weight value. 1422 /// The operand object must already have been set up with the operand type. 1423 virtual ConstraintWeight getMultipleConstraintMatchWeight( 1424 AsmOperandInfo &info, int maIndex) const; 1425 1426 /// Examine constraint string and operand type and determine a weight value. 1427 /// The operand object must already have been set up with the operand type. 1428 virtual ConstraintWeight getSingleConstraintMatchWeight( 1429 AsmOperandInfo &info, const char *constraint) const; 1430 1431 /// ComputeConstraintToUse - Determines the constraint code and constraint 1432 /// type to use for the specific AsmOperandInfo, setting 1433 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1434 /// being passed in is available, it can be passed in as Op, otherwise an 1435 /// empty SDValue can be passed. 1436 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1437 SDValue Op, 1438 SelectionDAG *DAG = 0) const; 1439 1440 /// getConstraintType - Given a constraint, return the type of constraint it 1441 /// is for this target. 1442 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1443 1444 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1445 /// return a list of registers that can be used to satisfy the constraint. 1446 /// This should only be used for C_RegisterClass constraints. 1447 virtual std::vector<unsigned> 1448 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1449 EVT VT) const; 1450 1451 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1452 /// {edx}), return the register number and the register class for the 1453 /// register. 1454 /// 1455 /// Given a register class constraint, like 'r', if this corresponds directly 1456 /// to an LLVM register class, return a register of 0 and the register class 1457 /// pointer. 1458 /// 1459 /// This should only be used for C_Register constraints. On error, 1460 /// this returns a register number of 0 and a null register class pointer.. 1461 virtual std::pair<unsigned, const TargetRegisterClass*> 1462 getRegForInlineAsmConstraint(const std::string &Constraint, 1463 EVT VT) const; 1464 1465 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1466 /// with another that has more specific requirements based on the type of the 1467 /// corresponding operand. This returns null if there is no replacement to 1468 /// make. 1469 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1470 1471 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1472 /// vector. If it is invalid, don't add anything to Ops. 1473 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1474 std::vector<SDValue> &Ops, 1475 SelectionDAG &DAG) const; 1476 1477 //===--------------------------------------------------------------------===// 1478 // Instruction Emitting Hooks 1479 // 1480 1481 // EmitInstrWithCustomInserter - This method should be implemented by targets 1482 // that mark instructions with the 'usesCustomInserter' flag. These 1483 // instructions are special in various ways, which require special support to 1484 // insert. The specified MachineInstr is created but not inserted into any 1485 // basic blocks, and this method is called to expand it into a sequence of 1486 // instructions, potentially also creating new basic blocks and control flow. 1487 virtual MachineBasicBlock * 1488 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1489 1490 //===--------------------------------------------------------------------===// 1491 // Addressing mode description hooks (used by LSR etc). 1492 // 1493 1494 /// AddrMode - This represents an addressing mode of: 1495 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1496 /// If BaseGV is null, there is no BaseGV. 1497 /// If BaseOffs is zero, there is no base offset. 1498 /// If HasBaseReg is false, there is no base register. 1499 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1500 /// no scale. 1501 /// 1502 struct AddrMode { 1503 GlobalValue *BaseGV; 1504 int64_t BaseOffs; 1505 bool HasBaseReg; 1506 int64_t Scale; 1507 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1508 }; 1509 1510 /// isLegalAddressingMode - Return true if the addressing mode represented by 1511 /// AM is legal for this target, for a load/store of the specified type. 1512 /// The type may be VoidTy, in which case only return true if the addressing 1513 /// mode is legal for a load/store of any legal type. 1514 /// TODO: Handle pre/postinc as well. 1515 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1516 1517 /// isTruncateFree - Return true if it's free to truncate a value of 1518 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1519 /// register EAX to i16 by referencing its sub-register AX. 1520 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1521 return false; 1522 } 1523 1524 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1525 return false; 1526 } 1527 1528 /// isZExtFree - Return true if any actual instruction that defines a 1529 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1530 /// register. This does not necessarily include registers defined in 1531 /// unknown ways, such as incoming arguments, or copies from unknown 1532 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1533 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1534 /// all instructions that define 32-bit values implicit zero-extend the 1535 /// result out to 64 bits. 1536 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1537 return false; 1538 } 1539 1540 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1541 return false; 1542 } 1543 1544 /// isNarrowingProfitable - Return true if it's profitable to narrow 1545 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1546 /// from i32 to i8 but not from i32 to i16. 1547 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1548 return false; 1549 } 1550 1551 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1552 /// icmp immediate, that is the target has icmp instructions which can compare 1553 /// a register against the immediate without having to materialize the 1554 /// immediate into a register. 1555 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1556 return true; 1557 } 1558 1559 //===--------------------------------------------------------------------===// 1560 // Div utility functions 1561 // 1562 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1563 std::vector<SDNode*>* Created) const; 1564 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1565 std::vector<SDNode*>* Created) const; 1566 1567 1568 //===--------------------------------------------------------------------===// 1569 // Runtime Library hooks 1570 // 1571 1572 /// setLibcallName - Rename the default libcall routine name for the specified 1573 /// libcall. 1574 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1575 LibcallRoutineNames[Call] = Name; 1576 } 1577 1578 /// getLibcallName - Get the libcall routine name for the specified libcall. 1579 /// 1580 const char *getLibcallName(RTLIB::Libcall Call) const { 1581 return LibcallRoutineNames[Call]; 1582 } 1583 1584 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1585 /// result of the comparison libcall against zero. 1586 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1587 CmpLibcallCCs[Call] = CC; 1588 } 1589 1590 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1591 /// the comparison libcall against zero. 1592 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1593 return CmpLibcallCCs[Call]; 1594 } 1595 1596 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1597 /// specified libcall. 1598 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1599 LibcallCallingConvs[Call] = CC; 1600 } 1601 1602 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1603 /// specified libcall. 1604 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1605 return LibcallCallingConvs[Call]; 1606 } 1607 1608private: 1609 const TargetMachine &TM; 1610 const TargetData *TD; 1611 const TargetLoweringObjectFile &TLOF; 1612 1613 /// PointerTy - The type to use for pointers, usually i32 or i64. 1614 /// 1615 MVT PointerTy; 1616 1617 /// IsLittleEndian - True if this is a little endian target. 1618 /// 1619 bool IsLittleEndian; 1620 1621 /// SelectIsExpensive - Tells the code generator not to expand operations 1622 /// into sequences that use the select operations if possible. 1623 bool SelectIsExpensive; 1624 1625 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1626 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1627 /// a real cost model is in place. If we ever optimize for size, this will be 1628 /// set to true unconditionally. 1629 bool IntDivIsCheap; 1630 1631 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1632 /// srl/add/sra for a signed divide by power of two, and let the target handle 1633 /// it. 1634 bool Pow2DivIsCheap; 1635 1636 /// JumpIsExpensive - Tells the code generator that it shouldn't generate 1637 /// extra flow control instructions and should attempt to combine flow 1638 /// control instructions via predication. 1639 bool JumpIsExpensive; 1640 1641 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1642 /// llvm.setjmp. Defaults to false. 1643 bool UseUnderscoreSetJmp; 1644 1645 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1646 /// llvm.longjmp. Defaults to false. 1647 bool UseUnderscoreLongJmp; 1648 1649 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1650 /// PointerTy is. 1651 MVT ShiftAmountTy; 1652 1653 /// BooleanContents - Information about the contents of the high-bits in 1654 /// boolean values held in a type wider than i1. See getBooleanContents. 1655 BooleanContent BooleanContents; 1656 1657 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1658 /// total cycles or lowest register usage. 1659 Sched::Preference SchedPreferenceInfo; 1660 1661 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1662 unsigned JumpBufSize; 1663 1664 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1665 /// buffers 1666 unsigned JumpBufAlignment; 1667 1668 /// MinStackArgumentAlignment - The minimum alignment that any argument 1669 /// on the stack needs to have. 1670 /// 1671 unsigned MinStackArgumentAlignment; 1672 1673 /// PrefLoopAlignment - The perferred loop alignment. 1674 /// 1675 unsigned PrefLoopAlignment; 1676 1677 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1678 /// be folded into the enclosed atomic intrinsic instruction by the 1679 /// combiner. 1680 bool ShouldFoldAtomicFences; 1681 1682 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1683 /// specifies the register that llvm.savestack/llvm.restorestack should save 1684 /// and restore. 1685 unsigned StackPointerRegisterToSaveRestore; 1686 1687 /// ExceptionPointerRegister - If set to a physical register, this specifies 1688 /// the register that receives the exception address on entry to a landing 1689 /// pad. 1690 unsigned ExceptionPointerRegister; 1691 1692 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1693 /// the register that receives the exception typeid on entry to a landing 1694 /// pad. 1695 unsigned ExceptionSelectorRegister; 1696 1697 /// RegClassForVT - This indicates the default register class to use for 1698 /// each ValueType the target supports natively. 1699 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1700 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1701 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1702 1703 /// RepRegClassForVT - This indicates the "representative" register class to 1704 /// use for each ValueType the target supports natively. This information is 1705 /// used by the scheduler to track register pressure. By default, the 1706 /// representative register class is the largest legal super-reg register 1707 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1708 /// and i32's representative class would be GR32. 1709 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1710 1711 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1712 /// register class for each ValueType. The cost is used by the scheduler to 1713 /// approximate register pressure. 1714 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1715 1716 /// TransformToType - For any value types we are promoting or expanding, this 1717 /// contains the value type that we are changing to. For Expanded types, this 1718 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1719 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1720 /// by the system, this holds the same type (e.g. i32 -> i32). 1721 EVT TransformToType[MVT::LAST_VALUETYPE]; 1722 1723 /// OpActions - For each operation and each value type, keep a LegalizeAction 1724 /// that indicates how instruction selection should deal with the operation. 1725 /// Most operations are Legal (aka, supported natively by the target), but 1726 /// operations that are not should be described. Note that operations on 1727 /// non-legal value types are not described here. 1728 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1729 1730 /// LoadExtActions - For each load extension type and each value type, 1731 /// keep a LegalizeAction that indicates how instruction selection should deal 1732 /// with a load of a specific value type and extension type. 1733 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1734 1735 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1736 /// indicates whether a truncating store of a specific value type and 1737 /// truncating type is legal. 1738 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1739 1740 /// IndexedModeActions - For each indexed mode and each value type, 1741 /// keep a pair of LegalizeAction that indicates how instruction 1742 /// selection should deal with the load / store. The first dimension is the 1743 /// value_type for the reference. The second dimension represents the various 1744 /// modes for load store. 1745 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1746 1747 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1748 /// LegalizeAction that indicates how instruction selection should 1749 /// deal with the condition code. 1750 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1751 1752 ValueTypeActionImpl ValueTypeActions; 1753 1754 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1755 1756 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1757 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1758 /// which sets a bit in this array. 1759 unsigned char 1760 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1761 1762 /// PromoteToType - For operations that must be promoted to a specific type, 1763 /// this holds the destination type. This map should be sparse, so don't hold 1764 /// it as an array. 1765 /// 1766 /// Targets add entries to this map with AddPromotedToType(..), clients access 1767 /// this with getTypeToPromoteTo(..). 1768 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1769 PromoteToType; 1770 1771 /// LibcallRoutineNames - Stores the name each libcall. 1772 /// 1773 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1774 1775 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1776 /// of each of the comparison libcall against zero. 1777 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1778 1779 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1780 /// libcall. 1781 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1782 1783protected: 1784 /// When lowering \@llvm.memset this field specifies the maximum number of 1785 /// store operations that may be substituted for the call to memset. Targets 1786 /// must set this value based on the cost threshold for that target. Targets 1787 /// should assume that the memset will be done using as many of the largest 1788 /// store operations first, followed by smaller ones, if necessary, per 1789 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1790 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1791 /// store. This only applies to setting a constant array of a constant size. 1792 /// @brief Specify maximum number of store instructions per memset call. 1793 unsigned maxStoresPerMemset; 1794 1795 /// Maximum number of stores operations that may be substituted for the call 1796 /// to memset, used for functions with OptSize attribute. 1797 unsigned maxStoresPerMemsetOptSize; 1798 1799 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1800 /// store operations that may be substituted for a call to memcpy. Targets 1801 /// must set this value based on the cost threshold for that target. Targets 1802 /// should assume that the memcpy will be done using as many of the largest 1803 /// store operations first, followed by smaller ones, if necessary, per 1804 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1805 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1806 /// and one 1-byte store. This only applies to copying a constant array of 1807 /// constant size. 1808 /// @brief Specify maximum bytes of store instructions per memcpy call. 1809 unsigned maxStoresPerMemcpy; 1810 1811 /// Maximum number of store operations that may be substituted for a call 1812 /// to memcpy, used for functions with OptSize attribute. 1813 unsigned maxStoresPerMemcpyOptSize; 1814 1815 /// When lowering \@llvm.memmove this field specifies the maximum number of 1816 /// store instructions that may be substituted for a call to memmove. Targets 1817 /// must set this value based on the cost threshold for that target. Targets 1818 /// should assume that the memmove will be done using as many of the largest 1819 /// store operations first, followed by smaller ones, if necessary, per 1820 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1821 /// with 8-bit alignment would result in nine 1-byte stores. This only 1822 /// applies to copying a constant array of constant size. 1823 /// @brief Specify maximum bytes of store instructions per memmove call. 1824 unsigned maxStoresPerMemmove; 1825 1826 /// Maximum number of store instructions that may be substituted for a call 1827 /// to memmove, used for functions with OpSize attribute. 1828 unsigned maxStoresPerMemmoveOptSize; 1829 1830 /// This field specifies whether the target can benefit from code placement 1831 /// optimization. 1832 bool benefitFromCodePlacementOpt; 1833 1834private: 1835 /// isLegalRC - Return true if the value types that can be represented by the 1836 /// specified register class are all legal. 1837 bool isLegalRC(const TargetRegisterClass *RC) const; 1838 1839 /// hasLegalSuperRegRegClasses - Return true if the specified register class 1840 /// has one or more super-reg register classes that are legal. 1841 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const; 1842}; 1843 1844/// GetReturnInfo - Given an LLVM IR type and return type attributes, 1845/// compute the return value EVTs and flags, and optionally also 1846/// the offsets, if the return value is being lowered to memory. 1847void GetReturnInfo(const Type* ReturnType, Attributes attr, 1848 SmallVectorImpl<ISD::OutputArg> &Outs, 1849 const TargetLowering &TLI, 1850 SmallVectorImpl<uint64_t> *Offsets = 0); 1851 1852} // end llvm namespace 1853 1854#endif 1855