TargetLowering.h revision 58f15c482a7129c78ca809792b46befa20ea337d
1c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 24afd3d042215afe68d00b9ab8c32f063a3a1c03fLiming Gao// 3c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// The LLVM Compiler Infrastructure 4a61331e8b78ba264f0ccd011b6dc5b9e809730a5Liming Gao// 540d841f6a8f84e75409178e19e69b95e01bada0flgao// This file is distributed under the University of Illinois Open Source 6c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// License. See LICENSE.TXT for details. 7c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// 8c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang//===----------------------------------------------------------------------===// 9c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// 10c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// This file describes how to lower LLVM code to machine code. This has two 11c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// main components: 12c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// 13c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// 1. Which ValueTypes are natively supported by the target. 14c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// 2. Which operations are supported for supported ValueTypes. 15c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// 3. Cost thresholds for alternative implementations of certain operations. 16c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// 17c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// In addition it has a few other components, like information about FP 18c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// immediates. 19c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang// 20c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang//===----------------------------------------------------------------------===// 21c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang 22c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang#ifndef LLVM_TARGET_TARGETLOWERING_H 23c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang#define LLVM_TARGET_TARGETLOWERING_H 24c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang 25c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang#include "llvm/Constants.h" 26c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang#include "llvm/InlineAsm.h" 27a61331e8b78ba264f0ccd011b6dc5b9e809730a5Liming Gao#include "llvm/CodeGen/SelectionDAGNodes.h" 28c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang#include "llvm/CodeGen/RuntimeLibcalls.h" 29fa318476e442d7e77bf960af281a9bebe86ad59bLiming Gao#include "llvm/ADT/APFloat.h" 30c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang#include "llvm/ADT/DenseMap.h" 31c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang#include "llvm/ADT/SmallSet.h" 32c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang#include "llvm/ADT/STLExtras.h" 33b36d134faf4305247830522b8e2bb255e98c5699lgao#include <map> 34b36d134faf4305247830522b8e2bb255e98c5699lgao#include <vector> 35b36d134faf4305247830522b8e2bb255e98c5699lgao 36b36d134faf4305247830522b8e2bb255e98c5699lgaonamespace llvm { 37b36d134faf4305247830522b8e2bb255e98c5699lgao class AllocaInst; 38b36d134faf4305247830522b8e2bb255e98c5699lgao class Function; 39b36d134faf4305247830522b8e2bb255e98c5699lgao class FastISel; 40b36d134faf4305247830522b8e2bb255e98c5699lgao class MachineBasicBlock; 41b36d134faf4305247830522b8e2bb255e98c5699lgao class MachineFunction; 42b36d134faf4305247830522b8e2bb255e98c5699lgao class MachineFrameInfo; 43b36d134faf4305247830522b8e2bb255e98c5699lgao class MachineInstr; 44b36d134faf4305247830522b8e2bb255e98c5699lgao class MachineModuleInfo; 45b36d134faf4305247830522b8e2bb255e98c5699lgao class SDNode; 46b36d134faf4305247830522b8e2bb255e98c5699lgao class SDValue; 47b36d134faf4305247830522b8e2bb255e98c5699lgao class SelectionDAG; 48c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang class TargetData; 49c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang class TargetMachine; 50c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang class TargetRegisterClass; 51c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang class TargetSubtarget; 52c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang class Value; 53c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang class VectorType; 54c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang 55c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang//===----------------------------------------------------------------------===// 56e4ac870fe95adc7d178a79b73ad2792e0c8bfeb8Gao, Liming/// TargetLowering - This class defines information used to lower LLVM code to 57c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang/// legal SelectionDAG operators that the target instruction selector can accept 58c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang/// natively. 59e4ac870fe95adc7d178a79b73ad2792e0c8bfeb8Gao, Liming/// 60c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang/// This class also defines callbacks that targets must implement to lower 61c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang/// target-specific constructs to SelectionDAG operators. 62fa318476e442d7e77bf960af281a9bebe86ad59bLiming Gao/// 63c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuangclass TargetLowering { 64c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuangpublic: 65fa318476e442d7e77bf960af281a9bebe86ad59bLiming Gao /// LegalizeAction - This enum indicates whether operations are valid for a 66c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang /// target, and if not, what action should be used to make them valid. 67c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang enum LegalizeAction { 68fa318476e442d7e77bf960af281a9bebe86ad59bLiming Gao Legal, // The target natively supports this operation. 69c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang Promote, // This operation should be executed in a larger type. 70c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang Expand, // Try to expand this to other ops, otherwise use a libcall. 71fa318476e442d7e77bf960af281a9bebe86ad59bLiming Gao Custom // Use the LowerOperation hook to implement custom lowering. 72c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang }; 73c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang 74c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang enum OutOfRangeShiftAmount { 75c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang Undefined, // Oversized shift amounts are undefined (default). 76e4ac870fe95adc7d178a79b73ad2792e0c8bfeb8Gao, Liming Mask, // Shift amounts are auto masked (anded) to value size. 77e4ac870fe95adc7d178a79b73ad2792e0c8bfeb8Gao, Liming Extend // Oversized shift pulls in zeros or sign bits. 78c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang }; 79c69f724df0f9e53b2c29f10e1eae3c784749e8daqhuang 80 enum SetCCResultValue { 81 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 82 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 83 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 84 }; 85 86 enum SchedPreference { 87 SchedulingForLatency, // Scheduling for shortest total latency. 88 SchedulingForRegPressure // Scheduling for lowest register pressure. 89 }; 90 91 explicit TargetLowering(TargetMachine &TM); 92 virtual ~TargetLowering(); 93 94 TargetMachine &getTargetMachine() const { return TM; } 95 const TargetData *getTargetData() const { return TD; } 96 97 bool isBigEndian() const { return !IsLittleEndian; } 98 bool isLittleEndian() const { return IsLittleEndian; } 99 MVT getPointerTy() const { return PointerTy; } 100 MVT getShiftAmountTy() const { return ShiftAmountTy; } 101 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 102 103 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 104 /// codegen. 105 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 106 107 /// isSelectExpensive - Return true if the select operation is expensive for 108 /// this target. 109 bool isSelectExpensive() const { return SelectIsExpensive; } 110 111 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 112 /// a sequence of several shifts, adds, and multiplies for this target. 113 bool isIntDivCheap() const { return IntDivIsCheap; } 114 115 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 116 /// srl/add/sra. 117 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 118 119 /// getSetCCResultType - Return the ValueType of the result of setcc 120 /// operations. 121 virtual MVT getSetCCResultType(const SDValue &) const; 122 123 /// getSetCCResultContents - For targets without boolean registers, this flag 124 /// returns information about the contents of the high-bits in the setcc 125 /// result register. 126 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 127 128 /// getSchedulingPreference - Return target scheduling preference. 129 SchedPreference getSchedulingPreference() const { 130 return SchedPreferenceInfo; 131 } 132 133 /// getRegClassFor - Return the register class that should be used for the 134 /// specified value type. This may only be called on legal types. 135 TargetRegisterClass *getRegClassFor(MVT VT) const { 136 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 137 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; 138 assert(RC && "This value type is not natively supported!"); 139 return RC; 140 } 141 142 /// isTypeLegal - Return true if the target has native support for the 143 /// specified value type. This means that it has a register that directly 144 /// holds it without promotions or expansions. 145 bool isTypeLegal(MVT VT) const { 146 assert(!VT.isSimple() || 147 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 148 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; 149 } 150 151 class ValueTypeActionImpl { 152 /// ValueTypeActions - This is a bitvector that contains two bits for each 153 /// value type, where the two bits correspond to the LegalizeAction enum. 154 /// This can be queried with "getTypeAction(VT)". 155 uint32_t ValueTypeActions[2]; 156 public: 157 ValueTypeActionImpl() { 158 ValueTypeActions[0] = ValueTypeActions[1] = 0; 159 } 160 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 161 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 162 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 163 } 164 165 LegalizeAction getTypeAction(MVT VT) const { 166 if (VT.isExtended()) { 167 if (VT.isVector()) return Expand; 168 if (VT.isInteger()) 169 // First promote to a power-of-two size, then expand if necessary. 170 return VT == VT.getRoundIntegerType() ? Expand : Promote; 171 assert(0 && "Unsupported extended type!"); 172 return Legal; 173 } 174 unsigned I = VT.getSimpleVT(); 175 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 176 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 177 } 178 void setTypeAction(MVT VT, LegalizeAction Action) { 179 unsigned I = VT.getSimpleVT(); 180 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 181 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 182 } 183 }; 184 185 const ValueTypeActionImpl &getValueTypeActions() const { 186 return ValueTypeActions; 187 } 188 189 /// getTypeAction - Return how we should legalize values of this type, either 190 /// it is already legal (return 'Legal') or we need to promote it to a larger 191 /// type (return 'Promote'), or we need to expand it into multiple registers 192 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 193 LegalizeAction getTypeAction(MVT VT) const { 194 return ValueTypeActions.getTypeAction(VT); 195 } 196 197 /// getTypeToTransformTo - For types supported by the target, this is an 198 /// identity function. For types that must be promoted to larger types, this 199 /// returns the larger type to promote to. For integer types that are larger 200 /// than the largest integer register, this contains one step in the expansion 201 /// to get to the smaller register. For illegal floating point types, this 202 /// returns the integer type to transform to. 203 MVT getTypeToTransformTo(MVT VT) const { 204 if (VT.isSimple()) { 205 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); 206 MVT NVT = TransformToType[VT.getSimpleVT()]; 207 assert(getTypeAction(NVT) != Promote && 208 "Promote may not follow Expand or Promote"); 209 return NVT; 210 } 211 212 if (VT.isVector()) 213 return MVT::getVectorVT(VT.getVectorElementType(), 214 VT.getVectorNumElements() / 2); 215 if (VT.isInteger()) { 216 MVT NVT = VT.getRoundIntegerType(); 217 if (NVT == VT) 218 // Size is a power of two - expand to half the size. 219 return MVT::getIntegerVT(VT.getSizeInBits() / 2); 220 else 221 // Promote to a power of two size, avoiding multi-step promotion. 222 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 223 } 224 assert(0 && "Unsupported extended type!"); 225 return MVT(); // Not reached 226 } 227 228 /// getTypeToExpandTo - For types supported by the target, this is an 229 /// identity function. For types that must be expanded (i.e. integer types 230 /// that are larger than the largest integer register or illegal floating 231 /// point types), this returns the largest legal type it will be expanded to. 232 MVT getTypeToExpandTo(MVT VT) const { 233 assert(!VT.isVector()); 234 while (true) { 235 switch (getTypeAction(VT)) { 236 case Legal: 237 return VT; 238 case Expand: 239 VT = getTypeToTransformTo(VT); 240 break; 241 default: 242 assert(false && "Type is not legal nor is it to be expanded!"); 243 return VT; 244 } 245 } 246 return VT; 247 } 248 249 /// getVectorTypeBreakdown - Vector types are broken down into some number of 250 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 251 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 252 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 253 /// 254 /// This method returns the number of registers needed, and the VT for each 255 /// register. It also returns the VT and quantity of the intermediate values 256 /// before they are promoted/expanded. 257 /// 258 unsigned getVectorTypeBreakdown(MVT VT, 259 MVT &IntermediateVT, 260 unsigned &NumIntermediates, 261 MVT &RegisterVT) const; 262 263 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 264 legal_fpimm_iterator legal_fpimm_begin() const { 265 return LegalFPImmediates.begin(); 266 } 267 legal_fpimm_iterator legal_fpimm_end() const { 268 return LegalFPImmediates.end(); 269 } 270 271 /// isShuffleMaskLegal - Targets can use this to indicate that they only 272 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 273 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 274 /// are assumed to be legal. 275 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const { 276 return true; 277 } 278 279 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 280 /// used by Targets can use this to indicate if there is a suitable 281 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 282 /// pool entry. 283 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, 284 MVT EVT, 285 SelectionDAG &DAG) const { 286 return false; 287 } 288 289 /// getOperationAction - Return how this operation should be treated: either 290 /// it is legal, needs to be promoted to a larger size, needs to be 291 /// expanded to some other code sequence, or the target has a custom expander 292 /// for it. 293 LegalizeAction getOperationAction(unsigned Op, MVT VT) const { 294 if (VT.isExtended()) return Expand; 295 assert(Op < array_lengthof(OpActions) && 296 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 297 "Table isn't big enough!"); 298 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); 299 } 300 301 /// isOperationLegal - Return true if the specified operation is legal on this 302 /// target. 303 bool isOperationLegal(unsigned Op, MVT VT) const { 304 return (VT == MVT::Other || isTypeLegal(VT)) && 305 (getOperationAction(Op, VT) == Legal || 306 getOperationAction(Op, VT) == Custom); 307 } 308 309 /// getLoadExtAction - Return how this load with extension should be treated: 310 /// either it is legal, needs to be promoted to a larger size, needs to be 311 /// expanded to some other code sequence, or the target has a custom expander 312 /// for it. 313 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const { 314 assert(LType < array_lengthof(LoadExtActions) && 315 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 316 "Table isn't big enough!"); 317 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3); 318 } 319 320 /// isLoadExtLegal - Return true if the specified load with extension is legal 321 /// on this target. 322 bool isLoadExtLegal(unsigned LType, MVT VT) const { 323 return VT.isSimple() && 324 (getLoadExtAction(LType, VT) == Legal || 325 getLoadExtAction(LType, VT) == Custom); 326 } 327 328 /// getTruncStoreAction - Return how this store with truncation should be 329 /// treated: either it is legal, needs to be promoted to a larger size, needs 330 /// to be expanded to some other code sequence, or the target has a custom 331 /// expander for it. 332 LegalizeAction getTruncStoreAction(MVT ValVT, 333 MVT MemVT) const { 334 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 335 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 336 "Table isn't big enough!"); 337 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> 338 (2*MemVT.getSimpleVT())) & 3); 339 } 340 341 /// isTruncStoreLegal - Return true if the specified store with truncation is 342 /// legal on this target. 343 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { 344 return isTypeLegal(ValVT) && MemVT.isSimple() && 345 (getTruncStoreAction(ValVT, MemVT) == Legal || 346 getTruncStoreAction(ValVT, MemVT) == Custom); 347 } 348 349 /// getIndexedLoadAction - Return how the indexed load should be treated: 350 /// either it is legal, needs to be promoted to a larger size, needs to be 351 /// expanded to some other code sequence, or the target has a custom expander 352 /// for it. 353 LegalizeAction 354 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 355 assert(IdxMode < array_lengthof(IndexedModeActions[0]) && 356 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 && 357 "Table isn't big enough!"); 358 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> 359 (2*VT.getSimpleVT())) & 3); 360 } 361 362 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 363 /// on this target. 364 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { 365 return VT.isSimple() && 366 (getIndexedLoadAction(IdxMode, VT) == Legal || 367 getIndexedLoadAction(IdxMode, VT) == Custom); 368 } 369 370 /// getIndexedStoreAction - Return how the indexed store should be treated: 371 /// either it is legal, needs to be promoted to a larger size, needs to be 372 /// expanded to some other code sequence, or the target has a custom expander 373 /// for it. 374 LegalizeAction 375 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 376 assert(IdxMode < array_lengthof(IndexedModeActions[1]) && 377 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 378 "Table isn't big enough!"); 379 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> 380 (2*VT.getSimpleVT())) & 3); 381 } 382 383 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 384 /// on this target. 385 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { 386 return VT.isSimple() && 387 (getIndexedStoreAction(IdxMode, VT) == Legal || 388 getIndexedStoreAction(IdxMode, VT) == Custom); 389 } 390 391 /// getConvertAction - Return how the conversion should be treated: 392 /// either it is legal, needs to be promoted to a larger size, needs to be 393 /// expanded to some other code sequence, or the target has a custom expander 394 /// for it. 395 LegalizeAction 396 getConvertAction(MVT FromVT, MVT ToVT) const { 397 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 398 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 399 "Table isn't big enough!"); 400 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> 401 (2*ToVT.getSimpleVT())) & 3); 402 } 403 404 /// isConvertLegal - Return true if the specified conversion is legal 405 /// on this target. 406 bool isConvertLegal(MVT FromVT, MVT ToVT) const { 407 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 408 (getConvertAction(FromVT, ToVT) == Legal || 409 getConvertAction(FromVT, ToVT) == Custom); 410 } 411 412 /// getCondCodeAction - Return how the condition code should be treated: 413 /// either it is legal, needs to be expanded to some other code sequence, 414 /// or the target has a custom expander for it. 415 LegalizeAction 416 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 417 assert((unsigned)CC < array_lengthof(CondCodeActions) && 418 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 419 "Table isn't big enough!"); 420 LegalizeAction Action = (LegalizeAction) 421 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3); 422 assert(Action != Promote && "Can't promote condition code!"); 423 return Action; 424 } 425 426 /// isCondCodeLegal - Return true if the specified condition code is legal 427 /// on this target. 428 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 429 return getCondCodeAction(CC, VT) == Legal || 430 getCondCodeAction(CC, VT) == Custom; 431 } 432 433 434 /// getTypeToPromoteTo - If the action for this operation is to promote, this 435 /// method returns the ValueType to promote to. 436 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 437 assert(getOperationAction(Op, VT) == Promote && 438 "This operation isn't promoted!"); 439 440 // See if this has an explicit type specified. 441 std::map<std::pair<unsigned, MVT::SimpleValueType>, 442 MVT::SimpleValueType>::const_iterator PTTI = 443 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); 444 if (PTTI != PromoteToType.end()) return PTTI->second; 445 446 assert((VT.isInteger() || VT.isFloatingPoint()) && 447 "Cannot autopromote this type, add it with AddPromotedToType."); 448 449 MVT NVT = VT; 450 do { 451 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); 452 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 453 "Didn't find type to promote to!"); 454 } while (!isTypeLegal(NVT) || 455 getOperationAction(Op, NVT) == Promote); 456 return NVT; 457 } 458 459 /// getValueType - Return the MVT corresponding to this LLVM type. 460 /// This is fixed by the LLVM operations except for the pointer size. If 461 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 462 /// counterpart (e.g. structs), otherwise it will assert. 463 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 464 MVT VT = MVT::getMVT(Ty, AllowUnknown); 465 return VT == MVT::iPTR ? PointerTy : VT; 466 } 467 468 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 469 /// function arguments in the caller parameter area. This is the actual 470 /// alignment, not its logarithm. 471 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 472 473 /// getRegisterType - Return the type of registers that this ValueType will 474 /// eventually require. 475 MVT getRegisterType(MVT VT) const { 476 if (VT.isSimple()) { 477 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); 478 return RegisterTypeForVT[VT.getSimpleVT()]; 479 } 480 if (VT.isVector()) { 481 MVT VT1, RegisterVT; 482 unsigned NumIntermediates; 483 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 484 return RegisterVT; 485 } 486 if (VT.isInteger()) { 487 return getRegisterType(getTypeToTransformTo(VT)); 488 } 489 assert(0 && "Unsupported extended type!"); 490 return MVT(); // Not reached 491 } 492 493 /// getNumRegisters - Return the number of registers that this ValueType will 494 /// eventually require. This is one for any types promoted to live in larger 495 /// registers, but may be more than one for types (like i64) that are split 496 /// into pieces. For types like i140, which are first promoted then expanded, 497 /// it is the number of registers needed to hold all the bits of the original 498 /// type. For an i140 on a 32 bit machine this means 5 registers. 499 unsigned getNumRegisters(MVT VT) const { 500 if (VT.isSimple()) { 501 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); 502 return NumRegistersForVT[VT.getSimpleVT()]; 503 } 504 if (VT.isVector()) { 505 MVT VT1, VT2; 506 unsigned NumIntermediates; 507 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 508 } 509 if (VT.isInteger()) { 510 unsigned BitWidth = VT.getSizeInBits(); 511 unsigned RegWidth = getRegisterType(VT).getSizeInBits(); 512 return (BitWidth + RegWidth - 1) / RegWidth; 513 } 514 assert(0 && "Unsupported extended type!"); 515 return 0; // Not reached 516 } 517 518 /// ShouldShrinkFPConstant - If true, then instruction selection should 519 /// seek to shrink the FP constant of the specified type to a smaller type 520 /// in order to save space and / or reduce runtime. 521 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } 522 523 /// hasTargetDAGCombine - If true, the target has custom DAG combine 524 /// transformations that it can perform for the specified node. 525 bool hasTargetDAGCombine(ISD::NodeType NT) const { 526 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 527 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 528 } 529 530 /// This function returns the maximum number of store operations permitted 531 /// to replace a call to llvm.memset. The value is set by the target at the 532 /// performance threshold for such a replacement. 533 /// @brief Get maximum # of store operations permitted for llvm.memset 534 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 535 536 /// This function returns the maximum number of store operations permitted 537 /// to replace a call to llvm.memcpy. The value is set by the target at the 538 /// performance threshold for such a replacement. 539 /// @brief Get maximum # of store operations permitted for llvm.memcpy 540 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 541 542 /// This function returns the maximum number of store operations permitted 543 /// to replace a call to llvm.memmove. The value is set by the target at the 544 /// performance threshold for such a replacement. 545 /// @brief Get maximum # of store operations permitted for llvm.memmove 546 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 547 548 /// This function returns true if the target allows unaligned memory accesses. 549 /// This is used, for example, in situations where an array copy/move/set is 550 /// converted to a sequence of store operations. It's use helps to ensure that 551 /// such replacements don't generate code that causes an alignment error 552 /// (trap) on the target machine. 553 /// @brief Determine if the target supports unaligned memory accesses. 554 bool allowsUnalignedMemoryAccesses() const { 555 return allowUnalignedMemoryAccesses; 556 } 557 558 /// getOptimalMemOpType - Returns the target specific optimal type for load 559 /// and store operations as a result of memset, memcpy, and memmove lowering. 560 /// It returns MVT::iAny if SelectionDAG should be responsible for 561 /// determining it. 562 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, 563 bool isSrcConst, bool isSrcStr) const { 564 return MVT::iAny; 565 } 566 567 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 568 /// to implement llvm.setjmp. 569 bool usesUnderscoreSetJmp() const { 570 return UseUnderscoreSetJmp; 571 } 572 573 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 574 /// to implement llvm.longjmp. 575 bool usesUnderscoreLongJmp() const { 576 return UseUnderscoreLongJmp; 577 } 578 579 /// getStackPointerRegisterToSaveRestore - If a physical register, this 580 /// specifies the register that llvm.savestack/llvm.restorestack should save 581 /// and restore. 582 unsigned getStackPointerRegisterToSaveRestore() const { 583 return StackPointerRegisterToSaveRestore; 584 } 585 586 /// getExceptionAddressRegister - If a physical register, this returns 587 /// the register that receives the exception address on entry to a landing 588 /// pad. 589 unsigned getExceptionAddressRegister() const { 590 return ExceptionPointerRegister; 591 } 592 593 /// getExceptionSelectorRegister - If a physical register, this returns 594 /// the register that receives the exception typeid on entry to a landing 595 /// pad. 596 unsigned getExceptionSelectorRegister() const { 597 return ExceptionSelectorRegister; 598 } 599 600 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 601 /// set, the default is 200) 602 unsigned getJumpBufSize() const { 603 return JumpBufSize; 604 } 605 606 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 607 /// (if never set, the default is 0) 608 unsigned getJumpBufAlignment() const { 609 return JumpBufAlignment; 610 } 611 612 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 613 /// limit. Any block whose size is greater should not be predicated. 614 unsigned getIfCvtBlockSizeLimit() const { 615 return IfCvtBlockSizeLimit; 616 } 617 618 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 619 /// block to be considered for duplication. Any block whose size is greater 620 /// should not be duplicated to facilitate its predication. 621 unsigned getIfCvtDupBlockSizeLimit() const { 622 return IfCvtDupBlockSizeLimit; 623 } 624 625 /// getPrefLoopAlignment - return the preferred loop alignment. 626 /// 627 unsigned getPrefLoopAlignment() const { 628 return PrefLoopAlignment; 629 } 630 631 /// getPreIndexedAddressParts - returns true by value, base pointer and 632 /// offset pointer and addressing mode by reference if the node's address 633 /// can be legally represented as pre-indexed load / store address. 634 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 635 SDValue &Offset, 636 ISD::MemIndexedMode &AM, 637 SelectionDAG &DAG) { 638 return false; 639 } 640 641 /// getPostIndexedAddressParts - returns true by value, base pointer and 642 /// offset pointer and addressing mode by reference if this node can be 643 /// combined with a load / store to form a post-indexed load / store. 644 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 645 SDValue &Base, SDValue &Offset, 646 ISD::MemIndexedMode &AM, 647 SelectionDAG &DAG) { 648 return false; 649 } 650 651 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 652 /// jumptable. 653 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 654 SelectionDAG &DAG) const; 655 656 //===--------------------------------------------------------------------===// 657 // TargetLowering Optimization Methods 658 // 659 660 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 661 /// SDValues for returning information from TargetLowering to its clients 662 /// that want to combine 663 struct TargetLoweringOpt { 664 SelectionDAG &DAG; 665 bool AfterLegalize; 666 SDValue Old; 667 SDValue New; 668 669 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize) 670 : DAG(InDAG), AfterLegalize(afterLegalize) {} 671 672 bool CombineTo(SDValue O, SDValue N) { 673 Old = O; 674 New = N; 675 return true; 676 } 677 678 /// ShrinkDemandedConstant - Check to see if the specified operand of the 679 /// specified instruction is a constant integer. If so, check to see if 680 /// there are any bits set in the constant that are not demanded. If so, 681 /// shrink the constant and return true. 682 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 683 }; 684 685 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 686 /// DemandedMask bits of the result of Op are ever used downstream. If we can 687 /// use this information to simplify Op, create a new simplified DAG node and 688 /// return true, returning the original and new nodes in Old and New. 689 /// Otherwise, analyze the expression and return a mask of KnownOne and 690 /// KnownZero bits for the expression (used to simplify the caller). 691 /// The KnownZero/One bits may only be accurate for those bits in the 692 /// DemandedMask. 693 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 694 APInt &KnownZero, APInt &KnownOne, 695 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 696 697 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 698 /// Mask are known to be either zero or one and return them in the 699 /// KnownZero/KnownOne bitsets. 700 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 701 const APInt &Mask, 702 APInt &KnownZero, 703 APInt &KnownOne, 704 const SelectionDAG &DAG, 705 unsigned Depth = 0) const; 706 707 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 708 /// targets that want to expose additional information about sign bits to the 709 /// DAG Combiner. 710 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 711 unsigned Depth = 0) const; 712 713 struct DAGCombinerInfo { 714 void *DC; // The DAG Combiner object. 715 bool BeforeLegalize; 716 bool CalledByLegalizer; 717 public: 718 SelectionDAG &DAG; 719 720 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 721 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 722 723 bool isBeforeLegalize() const { return BeforeLegalize; } 724 bool isCalledByLegalizer() const { return CalledByLegalizer; } 725 726 void AddToWorklist(SDNode *N); 727 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To); 728 SDValue CombineTo(SDNode *N, SDValue Res); 729 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1); 730 }; 731 732 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 733 /// and cc. If it is unable to simplify it, return a null SDValue. 734 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 735 ISD::CondCode Cond, bool foldBooleans, 736 DAGCombinerInfo &DCI) const; 737 738 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 739 /// node is a GlobalAddress + offset. 740 virtual bool 741 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 742 743 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 744 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the 745 /// location that the 'Base' load is loading from. 746 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist, 747 const MachineFrameInfo *MFI) const; 748 749 /// PerformDAGCombine - This method will be invoked for all target nodes and 750 /// for any target-independent nodes that the target has registered with 751 /// invoke it for. 752 /// 753 /// The semantics are as follows: 754 /// Return Value: 755 /// SDValue.Val == 0 - No change was made 756 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 757 /// otherwise - N should be replaced by the returned Operand. 758 /// 759 /// In addition, methods provided by DAGCombinerInfo may be used to perform 760 /// more complex transformations. 761 /// 762 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 763 764 //===--------------------------------------------------------------------===// 765 // TargetLowering Configuration Methods - These methods should be invoked by 766 // the derived class constructor to configure this object for the target. 767 // 768 769protected: 770 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 771 /// GOT for PC-relative code. 772 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 773 774 /// setShiftAmountType - Describe the type that should be used for shift 775 /// amounts. This type defaults to the pointer type. 776 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 777 778 /// setSetCCResultContents - Specify how the target extends the result of a 779 /// setcc operation in a register. 780 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 781 782 /// setSchedulingPreference - Specify the target scheduling preference. 783 void setSchedulingPreference(SchedPreference Pref) { 784 SchedPreferenceInfo = Pref; 785 } 786 787 /// setShiftAmountFlavor - Describe how the target handles out of range shift 788 /// amounts. 789 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 790 ShiftAmtHandling = OORSA; 791 } 792 793 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 794 /// use _setjmp to implement llvm.setjmp or the non _ version. 795 /// Defaults to false. 796 void setUseUnderscoreSetJmp(bool Val) { 797 UseUnderscoreSetJmp = Val; 798 } 799 800 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 801 /// use _longjmp to implement llvm.longjmp or the non _ version. 802 /// Defaults to false. 803 void setUseUnderscoreLongJmp(bool Val) { 804 UseUnderscoreLongJmp = Val; 805 } 806 807 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 808 /// specifies the register that llvm.savestack/llvm.restorestack should save 809 /// and restore. 810 void setStackPointerRegisterToSaveRestore(unsigned R) { 811 StackPointerRegisterToSaveRestore = R; 812 } 813 814 /// setExceptionPointerRegister - If set to a physical register, this sets 815 /// the register that receives the exception address on entry to a landing 816 /// pad. 817 void setExceptionPointerRegister(unsigned R) { 818 ExceptionPointerRegister = R; 819 } 820 821 /// setExceptionSelectorRegister - If set to a physical register, this sets 822 /// the register that receives the exception typeid on entry to a landing 823 /// pad. 824 void setExceptionSelectorRegister(unsigned R) { 825 ExceptionSelectorRegister = R; 826 } 827 828 /// SelectIsExpensive - Tells the code generator not to expand operations 829 /// into sequences that use the select operations if possible. 830 void setSelectIsExpensive() { SelectIsExpensive = true; } 831 832 /// setIntDivIsCheap - Tells the code generator that integer divide is 833 /// expensive, and if possible, should be replaced by an alternate sequence 834 /// of instructions not containing an integer divide. 835 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 836 837 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 838 /// srl/add/sra for a signed divide by power of two, and let the target handle 839 /// it. 840 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 841 842 /// addRegisterClass - Add the specified register class as an available 843 /// regclass for the specified value type. This indicates the selector can 844 /// handle values of that class natively. 845 void addRegisterClass(MVT VT, TargetRegisterClass *RC) { 846 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 847 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 848 RegClassForVT[VT.getSimpleVT()] = RC; 849 } 850 851 /// computeRegisterProperties - Once all of the register classes are added, 852 /// this allows us to compute derived properties we expose. 853 void computeRegisterProperties(); 854 855 /// setOperationAction - Indicate that the specified operation does not work 856 /// with the specified type and indicate what to do about it. 857 void setOperationAction(unsigned Op, MVT VT, 858 LegalizeAction Action) { 859 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 860 Op < array_lengthof(OpActions) && "Table isn't big enough!"); 861 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 862 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2; 863 } 864 865 /// setLoadExtAction - Indicate that the specified load with extension does 866 /// not work with the with specified type and indicate what to do about it. 867 void setLoadExtAction(unsigned ExtType, MVT VT, 868 LegalizeAction Action) { 869 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 870 ExtType < array_lengthof(LoadExtActions) && 871 "Table isn't big enough!"); 872 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 873 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2; 874 } 875 876 /// setTruncStoreAction - Indicate that the specified truncating store does 877 /// not work with the with specified type and indicate what to do about it. 878 void setTruncStoreAction(MVT ValVT, MVT MemVT, 879 LegalizeAction Action) { 880 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 881 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 882 "Table isn't big enough!"); 883 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) << 884 MemVT.getSimpleVT()*2); 885 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action << 886 MemVT.getSimpleVT()*2; 887 } 888 889 /// setIndexedLoadAction - Indicate that the specified indexed load does or 890 /// does not work with the with specified type and indicate what to do abort 891 /// it. NOTE: All indexed mode loads are initialized to Expand in 892 /// TargetLowering.cpp 893 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 894 LegalizeAction Action) { 895 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 && 896 IdxMode < array_lengthof(IndexedModeActions[0]) && 897 "Table isn't big enough!"); 898 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 899 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 900 } 901 902 /// setIndexedStoreAction - Indicate that the specified indexed store does or 903 /// does not work with the with specified type and indicate what to do about 904 /// it. NOTE: All indexed mode stores are initialized to Expand in 905 /// TargetLowering.cpp 906 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 907 LegalizeAction Action) { 908 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 909 IdxMode < array_lengthof(IndexedModeActions[1]) && 910 "Table isn't big enough!"); 911 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 912 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 913 } 914 915 /// setConvertAction - Indicate that the specified conversion does or does 916 /// not work with the with specified type and indicate what to do about it. 917 void setConvertAction(MVT FromVT, MVT ToVT, 918 LegalizeAction Action) { 919 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 920 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 921 "Table isn't big enough!"); 922 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) << 923 ToVT.getSimpleVT()*2); 924 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action << 925 ToVT.getSimpleVT()*2; 926 } 927 928 /// setCondCodeAction - Indicate that the specified condition code is or isn't 929 /// supported on the target and indicate what to do about it. 930 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { 931 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 932 (unsigned)CC < array_lengthof(CondCodeActions) && 933 "Table isn't big enough!"); 934 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 935 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2; 936 } 937 938 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 939 /// promotion code defaults to trying a larger integer/fp until it can find 940 /// one that works. If that default is insufficient, this method can be used 941 /// by the target to override the default. 942 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 943 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] = 944 DestVT.getSimpleVT(); 945 } 946 947 /// addLegalFPImmediate - Indicate that this target can instruction select 948 /// the specified FP immediate natively. 949 void addLegalFPImmediate(const APFloat& Imm) { 950 LegalFPImmediates.push_back(Imm); 951 } 952 953 /// setTargetDAGCombine - Targets should invoke this method for each target 954 /// independent node that they want to provide a custom DAG combiner for by 955 /// implementing the PerformDAGCombine virtual method. 956 void setTargetDAGCombine(ISD::NodeType NT) { 957 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 958 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 959 } 960 961 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 962 /// bytes); default is 200 963 void setJumpBufSize(unsigned Size) { 964 JumpBufSize = Size; 965 } 966 967 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 968 /// alignment (in bytes); default is 0 969 void setJumpBufAlignment(unsigned Align) { 970 JumpBufAlignment = Align; 971 } 972 973 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 974 /// limit (in number of instructions); default is 2. 975 void setIfCvtBlockSizeLimit(unsigned Limit) { 976 IfCvtBlockSizeLimit = Limit; 977 } 978 979 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 980 /// of instructions) to be considered for code duplication during 981 /// if-conversion; default is 2. 982 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 983 IfCvtDupBlockSizeLimit = Limit; 984 } 985 986 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 987 /// alignment is zero, it means the target does not care about loop alignment. 988 void setPrefLoopAlignment(unsigned Align) { 989 PrefLoopAlignment = Align; 990 } 991 992public: 993 994 virtual const TargetSubtarget *getSubtarget() { 995 assert(0 && "Not Implemented"); 996 return NULL; // this is here to silence compiler errors 997 } 998 //===--------------------------------------------------------------------===// 999 // Lowering methods - These methods must be implemented by targets so that 1000 // the SelectionDAGLowering code knows how to lower these. 1001 // 1002 1003 /// LowerArguments - This hook must be implemented to indicate how we should 1004 /// lower the arguments for the specified function, into the specified DAG. 1005 virtual void 1006 LowerArguments(Function &F, SelectionDAG &DAG, 1007 SmallVectorImpl<SDValue>& ArgValues); 1008 1009 /// LowerCallTo - This hook lowers an abstract call to a function into an 1010 /// actual call. This returns a pair of operands. The first element is the 1011 /// return value for the function (if RetTy is not VoidTy). The second 1012 /// element is the outgoing token chain. 1013 struct ArgListEntry { 1014 SDValue Node; 1015 const Type* Ty; 1016 bool isSExt : 1; 1017 bool isZExt : 1; 1018 bool isInReg : 1; 1019 bool isSRet : 1; 1020 bool isNest : 1; 1021 bool isByVal : 1; 1022 uint16_t Alignment; 1023 1024 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1025 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1026 }; 1027 typedef std::vector<ArgListEntry> ArgListTy; 1028 virtual std::pair<SDValue, SDValue> 1029 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1030 bool isVarArg, bool isInreg, unsigned CallingConv, 1031 bool isTailCall, SDValue Callee, ArgListTy &Args, 1032 SelectionDAG &DAG); 1033 1034 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1035 /// memcpy. This can be used by targets to provide code sequences for cases 1036 /// that don't fit the target's parameters for simple loads/stores and can be 1037 /// more efficient than using a library call. This function can return a null 1038 /// SDValue if the target declines to use custom code and a different 1039 /// lowering strategy should be used. 1040 /// 1041 /// If AlwaysInline is true, the size is constant and the target should not 1042 /// emit any calls and is strongly encouraged to attempt to emit inline code 1043 /// even if it is beyond the usual threshold because this intrinsic is being 1044 /// expanded in a place where calls are not feasible (e.g. within the prologue 1045 /// for another call). If the target chooses to decline an AlwaysInline 1046 /// request here, legalize will resort to using simple loads and stores. 1047 virtual SDValue 1048 EmitTargetCodeForMemcpy(SelectionDAG &DAG, 1049 SDValue Chain, 1050 SDValue Op1, SDValue Op2, 1051 SDValue Op3, unsigned Align, 1052 bool AlwaysInline, 1053 const Value *DstSV, uint64_t DstOff, 1054 const Value *SrcSV, uint64_t SrcOff) { 1055 return SDValue(); 1056 } 1057 1058 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1059 /// memmove. This can be used by targets to provide code sequences for cases 1060 /// that don't fit the target's parameters for simple loads/stores and can be 1061 /// more efficient than using a library call. This function can return a null 1062 /// SDValue if the target declines to use custom code and a different 1063 /// lowering strategy should be used. 1064 virtual SDValue 1065 EmitTargetCodeForMemmove(SelectionDAG &DAG, 1066 SDValue Chain, 1067 SDValue Op1, SDValue Op2, 1068 SDValue Op3, unsigned Align, 1069 const Value *DstSV, uint64_t DstOff, 1070 const Value *SrcSV, uint64_t SrcOff) { 1071 return SDValue(); 1072 } 1073 1074 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1075 /// memset. This can be used by targets to provide code sequences for cases 1076 /// that don't fit the target's parameters for simple stores and can be more 1077 /// efficient than using a library call. This function can return a null 1078 /// SDValue if the target declines to use custom code and a different 1079 /// lowering strategy should be used. 1080 virtual SDValue 1081 EmitTargetCodeForMemset(SelectionDAG &DAG, 1082 SDValue Chain, 1083 SDValue Op1, SDValue Op2, 1084 SDValue Op3, unsigned Align, 1085 const Value *DstSV, uint64_t DstOff) { 1086 return SDValue(); 1087 } 1088 1089 /// LowerOperation - This callback is invoked for operations that are 1090 /// unsupported by the target, which are registered to use 'custom' lowering, 1091 /// and whose defined values are all legal. 1092 /// If the target has no operations that require custom lowering, it need not 1093 /// implement this. The default implementation of this aborts. 1094 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1095 1096 /// ReplaceNodeResults - This callback is invoked for operations that are 1097 /// unsupported by the target, which are registered to use 'custom' lowering, 1098 /// and whose result type is illegal. This must return a node whose results 1099 /// precisely match the results of the input node. This typically involves a 1100 /// MERGE_VALUES node and/or BUILD_PAIR. 1101 /// 1102 /// If the target has no operations that require custom lowering, it need not 1103 /// implement this. The default implementation aborts. 1104 virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { 1105 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1106 return 0; 1107 } 1108 1109 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1110 /// tail call optimization. Targets which want to do tail call optimization 1111 /// should override this function. 1112 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call, 1113 SDValue Ret, 1114 SelectionDAG &DAG) const { 1115 return false; 1116 } 1117 1118 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly 1119 /// preceeds the RET node and whether the return uses the result of the node 1120 /// or is a void return. This function can be used by the target to determine 1121 /// eligiblity of tail call optimization. 1122 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret) { 1123 unsigned NumOps = Ret.getNumOperands(); 1124 if ((NumOps == 1 && 1125 (Ret.getOperand(0) == SDValue(TheCall,1) || 1126 Ret.getOperand(0) == SDValue(TheCall,0))) || 1127 (NumOps > 1 && 1128 Ret.getOperand(0) == SDValue(TheCall, 1129 TheCall->getNumValues()-1) && 1130 Ret.getOperand(1) == SDValue(TheCall,0))) 1131 return true; 1132 return false; 1133 } 1134 1135 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1136 /// it exists skip possible ISD:TokenFactor. 1137 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1138 unsigned TailCallNodeOpCode) { 1139 if (Chain.getOpcode() == TailCallNodeOpCode) { 1140 return Chain; 1141 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1142 if (Chain.getNumOperands() && 1143 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1144 return Chain.getOperand(0); 1145 } 1146 return Chain; 1147 } 1148 1149 /// getTargetNodeName() - This method returns the name of a target specific 1150 /// DAG node. 1151 virtual const char *getTargetNodeName(unsigned Opcode) const; 1152 1153 /// createFastISel - This method returns a target specific FastISel object, 1154 /// or null if the target does not support "fast" ISel. 1155 virtual FastISel * 1156 createFastISel(MachineFunction &, 1157 MachineModuleInfo *, 1158 DenseMap<const Value *, unsigned> &, 1159 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1160 DenseMap<const AllocaInst *, int> & 1161#ifndef NDEBUG 1162 , SmallSet<Instruction*, 8> &CatchInfoLost 1163#endif 1164 ) { 1165 return 0; 1166 } 1167 1168 //===--------------------------------------------------------------------===// 1169 // Inline Asm Support hooks 1170 // 1171 1172 enum ConstraintType { 1173 C_Register, // Constraint represents a single register. 1174 C_RegisterClass, // Constraint represents one or more registers. 1175 C_Memory, // Memory constraint. 1176 C_Other, // Something else. 1177 C_Unknown // Unsupported constraint. 1178 }; 1179 1180 /// AsmOperandInfo - This contains information for each constraint that we are 1181 /// lowering. 1182 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1183 /// ConstraintCode - This contains the actual string for the code, like "m". 1184 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1185 /// most closely matches the operand. 1186 std::string ConstraintCode; 1187 1188 /// ConstraintType - Information about the constraint code, e.g. Register, 1189 /// RegisterClass, Memory, Other, Unknown. 1190 TargetLowering::ConstraintType ConstraintType; 1191 1192 /// CallOperandval - If this is the result output operand or a 1193 /// clobber, this is null, otherwise it is the incoming operand to the 1194 /// CallInst. This gets modified as the asm is processed. 1195 Value *CallOperandVal; 1196 1197 /// ConstraintVT - The ValueType for the operand value. 1198 MVT ConstraintVT; 1199 1200 /// isMatchingConstraint - Return true of this is an input operand that is a 1201 /// matching constraint like "4". 1202 bool isMatchingConstraint() const; 1203 1204 /// getMatchedOperand - If this is an input matching constraint, this method 1205 /// returns the output operand it matches. 1206 unsigned getMatchedOperand() const; 1207 1208 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1209 : InlineAsm::ConstraintInfo(info), 1210 ConstraintType(TargetLowering::C_Unknown), 1211 CallOperandVal(0), ConstraintVT(MVT::Other) { 1212 } 1213 }; 1214 1215 /// ComputeConstraintToUse - Determines the constraint code and constraint 1216 /// type to use for the specific AsmOperandInfo, setting 1217 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1218 /// being passed in is available, it can be passed in as Op, otherwise an 1219 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1220 /// constraint of the inline asm instruction being processed is 'm'. 1221 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1222 SDValue Op, 1223 bool hasMemory, 1224 SelectionDAG *DAG = 0) const; 1225 1226 /// getConstraintType - Given a constraint, return the type of constraint it 1227 /// is for this target. 1228 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1229 1230 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1231 /// return a list of registers that can be used to satisfy the constraint. 1232 /// This should only be used for C_RegisterClass constraints. 1233 virtual std::vector<unsigned> 1234 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1235 MVT VT) const; 1236 1237 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1238 /// {edx}), return the register number and the register class for the 1239 /// register. 1240 /// 1241 /// Given a register class constraint, like 'r', if this corresponds directly 1242 /// to an LLVM register class, return a register of 0 and the register class 1243 /// pointer. 1244 /// 1245 /// This should only be used for C_Register constraints. On error, 1246 /// this returns a register number of 0 and a null register class pointer.. 1247 virtual std::pair<unsigned, const TargetRegisterClass*> 1248 getRegForInlineAsmConstraint(const std::string &Constraint, 1249 MVT VT) const; 1250 1251 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1252 /// with another that has more specific requirements based on the type of the 1253 /// corresponding operand. This returns null if there is no replacement to 1254 /// make. 1255 virtual const char *LowerXConstraint(MVT ConstraintVT) const; 1256 1257 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1258 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1259 /// it means one of the asm constraint of the inline asm instruction being 1260 /// processed is 'm'. 1261 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1262 bool hasMemory, 1263 std::vector<SDValue> &Ops, 1264 SelectionDAG &DAG) const; 1265 1266 //===--------------------------------------------------------------------===// 1267 // Scheduler hooks 1268 // 1269 1270 // EmitInstrWithCustomInserter - This method should be implemented by targets 1271 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1272 // instructions are special in various ways, which require special support to 1273 // insert. The specified MachineInstr is created but not inserted into any 1274 // basic blocks, and the scheduler passes ownership of it to this method. 1275 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1276 MachineBasicBlock *MBB); 1277 1278 //===--------------------------------------------------------------------===// 1279 // Addressing mode description hooks (used by LSR etc). 1280 // 1281 1282 /// AddrMode - This represents an addressing mode of: 1283 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1284 /// If BaseGV is null, there is no BaseGV. 1285 /// If BaseOffs is zero, there is no base offset. 1286 /// If HasBaseReg is false, there is no base register. 1287 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1288 /// no scale. 1289 /// 1290 struct AddrMode { 1291 GlobalValue *BaseGV; 1292 int64_t BaseOffs; 1293 bool HasBaseReg; 1294 int64_t Scale; 1295 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1296 }; 1297 1298 /// isLegalAddressingMode - Return true if the addressing mode represented by 1299 /// AM is legal for this target, for a load/store of the specified type. 1300 /// TODO: Handle pre/postinc as well. 1301 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1302 1303 /// isTruncateFree - Return true if it's free to truncate a value of 1304 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1305 /// register EAX to i16 by referencing its sub-register AX. 1306 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1307 return false; 1308 } 1309 1310 virtual bool isTruncateFree(MVT VT1, MVT VT2) const { 1311 return false; 1312 } 1313 1314 //===--------------------------------------------------------------------===// 1315 // Div utility functions 1316 // 1317 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1318 std::vector<SDNode*>* Created) const; 1319 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1320 std::vector<SDNode*>* Created) const; 1321 1322 1323 //===--------------------------------------------------------------------===// 1324 // Runtime Library hooks 1325 // 1326 1327 /// setLibcallName - Rename the default libcall routine name for the specified 1328 /// libcall. 1329 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1330 LibcallRoutineNames[Call] = Name; 1331 } 1332 1333 /// getLibcallName - Get the libcall routine name for the specified libcall. 1334 /// 1335 const char *getLibcallName(RTLIB::Libcall Call) const { 1336 return LibcallRoutineNames[Call]; 1337 } 1338 1339 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1340 /// result of the comparison libcall against zero. 1341 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1342 CmpLibcallCCs[Call] = CC; 1343 } 1344 1345 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1346 /// the comparison libcall against zero. 1347 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1348 return CmpLibcallCCs[Call]; 1349 } 1350 1351private: 1352 TargetMachine &TM; 1353 const TargetData *TD; 1354 1355 /// PointerTy - The type to use for pointers, usually i32 or i64. 1356 /// 1357 MVT PointerTy; 1358 1359 /// IsLittleEndian - True if this is a little endian target. 1360 /// 1361 bool IsLittleEndian; 1362 1363 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1364 /// 1365 bool UsesGlobalOffsetTable; 1366 1367 /// SelectIsExpensive - Tells the code generator not to expand operations 1368 /// into sequences that use the select operations if possible. 1369 bool SelectIsExpensive; 1370 1371 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1372 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1373 /// a real cost model is in place. If we ever optimize for size, this will be 1374 /// set to true unconditionally. 1375 bool IntDivIsCheap; 1376 1377 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1378 /// srl/add/sra for a signed divide by power of two, and let the target handle 1379 /// it. 1380 bool Pow2DivIsCheap; 1381 1382 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1383 /// llvm.setjmp. Defaults to false. 1384 bool UseUnderscoreSetJmp; 1385 1386 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1387 /// llvm.longjmp. Defaults to false. 1388 bool UseUnderscoreLongJmp; 1389 1390 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1391 /// PointerTy is. 1392 MVT ShiftAmountTy; 1393 1394 OutOfRangeShiftAmount ShiftAmtHandling; 1395 1396 /// SetCCResultContents - Information about the contents of the high-bits in 1397 /// the result of a setcc comparison operation. 1398 SetCCResultValue SetCCResultContents; 1399 1400 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1401 /// total cycles or lowest register usage. 1402 SchedPreference SchedPreferenceInfo; 1403 1404 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1405 unsigned JumpBufSize; 1406 1407 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1408 /// buffers 1409 unsigned JumpBufAlignment; 1410 1411 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1412 /// if-converted. 1413 unsigned IfCvtBlockSizeLimit; 1414 1415 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1416 /// duplicated during if-conversion. 1417 unsigned IfCvtDupBlockSizeLimit; 1418 1419 /// PrefLoopAlignment - The perferred loop alignment. 1420 /// 1421 unsigned PrefLoopAlignment; 1422 1423 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1424 /// specifies the register that llvm.savestack/llvm.restorestack should save 1425 /// and restore. 1426 unsigned StackPointerRegisterToSaveRestore; 1427 1428 /// ExceptionPointerRegister - If set to a physical register, this specifies 1429 /// the register that receives the exception address on entry to a landing 1430 /// pad. 1431 unsigned ExceptionPointerRegister; 1432 1433 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1434 /// the register that receives the exception typeid on entry to a landing 1435 /// pad. 1436 unsigned ExceptionSelectorRegister; 1437 1438 /// RegClassForVT - This indicates the default register class to use for 1439 /// each ValueType the target supports natively. 1440 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1441 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1442 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1443 1444 /// TransformToType - For any value types we are promoting or expanding, this 1445 /// contains the value type that we are changing to. For Expanded types, this 1446 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1447 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1448 /// by the system, this holds the same type (e.g. i32 -> i32). 1449 MVT TransformToType[MVT::LAST_VALUETYPE]; 1450 1451 // Defines the capacity of the TargetLowering::OpActions table 1452 static const int OpActionsCapacity = 212; 1453 1454 /// OpActions - For each operation and each value type, keep a LegalizeAction 1455 /// that indicates how instruction selection should deal with the operation. 1456 /// Most operations are Legal (aka, supported natively by the target), but 1457 /// operations that are not should be described. Note that operations on 1458 /// non-legal value types are not described here. 1459 uint64_t OpActions[OpActionsCapacity]; 1460 1461 /// LoadExtActions - For each load of load extension type and each value type, 1462 /// keep a LegalizeAction that indicates how instruction selection should deal 1463 /// with the load. 1464 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1465 1466 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1467 /// indicates how instruction selection should deal with the store. 1468 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1469 1470 /// IndexedModeActions - For each indexed mode and each value type, keep a 1471 /// pair of LegalizeAction that indicates how instruction selection should 1472 /// deal with the load / store. 1473 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1474 1475 /// ConvertActions - For each conversion from source type to destination type, 1476 /// keep a LegalizeAction that indicates how instruction selection should 1477 /// deal with the conversion. 1478 /// Currently, this is used only for floating->floating conversions 1479 /// (FP_EXTEND and FP_ROUND). 1480 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1481 1482 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1483 /// LegalizeAction that indicates how instruction selection should 1484 /// deal with the condition code. 1485 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1486 1487 ValueTypeActionImpl ValueTypeActions; 1488 1489 std::vector<APFloat> LegalFPImmediates; 1490 1491 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses; 1492 1493 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1494 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1495 /// which sets a bit in this array. 1496 unsigned char 1497 TargetDAGCombineArray[OpActionsCapacity/(sizeof(unsigned char)*8)]; 1498 1499 /// PromoteToType - For operations that must be promoted to a specific type, 1500 /// this holds the destination type. This map should be sparse, so don't hold 1501 /// it as an array. 1502 /// 1503 /// Targets add entries to this map with AddPromotedToType(..), clients access 1504 /// this with getTypeToPromoteTo(..). 1505 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1506 PromoteToType; 1507 1508 /// LibcallRoutineNames - Stores the name each libcall. 1509 /// 1510 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1511 1512 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1513 /// of each of the comparison libcall against zero. 1514 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1515 1516protected: 1517 /// When lowering @llvm.memset this field specifies the maximum number of 1518 /// store operations that may be substituted for the call to memset. Targets 1519 /// must set this value based on the cost threshold for that target. Targets 1520 /// should assume that the memset will be done using as many of the largest 1521 /// store operations first, followed by smaller ones, if necessary, per 1522 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1523 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1524 /// store. This only applies to setting a constant array of a constant size. 1525 /// @brief Specify maximum number of store instructions per memset call. 1526 unsigned maxStoresPerMemset; 1527 1528 /// When lowering @llvm.memcpy this field specifies the maximum number of 1529 /// store operations that may be substituted for a call to memcpy. Targets 1530 /// must set this value based on the cost threshold for that target. Targets 1531 /// should assume that the memcpy will be done using as many of the largest 1532 /// store operations first, followed by smaller ones, if necessary, per 1533 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1534 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1535 /// and one 1-byte store. This only applies to copying a constant array of 1536 /// constant size. 1537 /// @brief Specify maximum bytes of store instructions per memcpy call. 1538 unsigned maxStoresPerMemcpy; 1539 1540 /// When lowering @llvm.memmove this field specifies the maximum number of 1541 /// store instructions that may be substituted for a call to memmove. Targets 1542 /// must set this value based on the cost threshold for that target. Targets 1543 /// should assume that the memmove will be done using as many of the largest 1544 /// store operations first, followed by smaller ones, if necessary, per 1545 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1546 /// with 8-bit alignment would result in nine 1-byte stores. This only 1547 /// applies to copying a constant array of constant size. 1548 /// @brief Specify maximum bytes of store instructions per memmove call. 1549 unsigned maxStoresPerMemmove; 1550 1551 /// This field specifies whether the target machine permits unaligned memory 1552 /// accesses. This is used, for example, to determine the size of store 1553 /// operations when copying small arrays and other similar tasks. 1554 /// @brief Indicate whether the target permits unaligned memory accesses. 1555 bool allowUnalignedMemoryAccesses; 1556}; 1557} // end llvm namespace 1558 1559#endif 1560