TargetLowering.h revision 71d7794856cb559696935e3ad8215cdb1ae9886b
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include <map> 28#include <vector> 29 30namespace llvm { 31 class Value; 32 class Function; 33 class TargetMachine; 34 class TargetData; 35 class TargetRegisterClass; 36 class SDNode; 37 class SDOperand; 38 class SelectionDAG; 39 class MachineBasicBlock; 40 class MachineInstr; 41 class VectorType; 42 43//===----------------------------------------------------------------------===// 44/// TargetLowering - This class defines information used to lower LLVM code to 45/// legal SelectionDAG operators that the target instruction selector can accept 46/// natively. 47/// 48/// This class also defines callbacks that targets must implement to lower 49/// target-specific constructs to SelectionDAG operators. 50/// 51class TargetLowering { 52public: 53 /// LegalizeAction - This enum indicates whether operations are valid for a 54 /// target, and if not, what action should be used to make them valid. 55 enum LegalizeAction { 56 Legal, // The target natively supports this operation. 57 Promote, // This operation should be executed in a larger type. 58 Expand, // Try to expand this to other ops, otherwise use a libcall. 59 Custom // Use the LowerOperation hook to implement custom lowering. 60 }; 61 62 enum OutOfRangeShiftAmount { 63 Undefined, // Oversized shift amounts are undefined (default). 64 Mask, // Shift amounts are auto masked (anded) to value size. 65 Extend // Oversized shift pulls in zeros or sign bits. 66 }; 67 68 enum SetCCResultValue { 69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 72 }; 73 74 enum SchedPreference { 75 SchedulingForLatency, // Scheduling for shortest total latency. 76 SchedulingForRegPressure // Scheduling for lowest register pressure. 77 }; 78 79 TargetLowering(TargetMachine &TM); 80 virtual ~TargetLowering(); 81 82 TargetMachine &getTargetMachine() const { return TM; } 83 const TargetData *getTargetData() const { return TD; } 84 85 bool isLittleEndian() const { return IsLittleEndian; } 86 MVT::ValueType getPointerTy() const { return PointerTy; } 87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 89 90 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 91 /// codegen. 92 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 93 94 /// isSelectExpensive - Return true if the select operation is expensive for 95 /// this target. 96 bool isSelectExpensive() const { return SelectIsExpensive; } 97 98 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 99 /// a sequence of several shifts, adds, and multiplies for this target. 100 bool isIntDivCheap() const { return IntDivIsCheap; } 101 102 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 103 /// srl/add/sra. 104 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 105 106 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 107 /// 108 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 109 110 /// getSetCCResultContents - For targets without boolean registers, this flag 111 /// returns information about the contents of the high-bits in the setcc 112 /// result register. 113 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 114 115 /// getSchedulingPreference - Return target scheduling preference. 116 SchedPreference getSchedulingPreference() const { 117 return SchedPreferenceInfo; 118 } 119 120 /// getRegClassFor - Return the register class that should be used for the 121 /// specified value type. This may only be called on legal types. 122 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 123 assert(!MVT::isExtendedValueType(VT)); 124 TargetRegisterClass *RC = RegClassForVT[VT]; 125 assert(RC && "This value type is not natively supported!"); 126 return RC; 127 } 128 129 /// isTypeLegal - Return true if the target has native support for the 130 /// specified value type. This means that it has a register that directly 131 /// holds it without promotions or expansions. 132 bool isTypeLegal(MVT::ValueType VT) const { 133 return !MVT::isExtendedValueType(VT) && RegClassForVT[VT] != 0; 134 } 135 136 class ValueTypeActionImpl { 137 /// ValueTypeActions - This is a bitvector that contains two bits for each 138 /// value type, where the two bits correspond to the LegalizeAction enum. 139 /// This can be queried with "getTypeAction(VT)". 140 uint32_t ValueTypeActions[2]; 141 public: 142 ValueTypeActionImpl() { 143 ValueTypeActions[0] = ValueTypeActions[1] = 0; 144 } 145 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 146 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 147 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 148 } 149 150 LegalizeAction getTypeAction(MVT::ValueType VT) const { 151 return !MVT::isExtendedValueType(VT) ? 152 (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3) : 153 Expand; 154 } 155 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 156 assert(!MVT::isExtendedValueType(VT)); 157 assert(unsigned(VT >> 4) < 158 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 159 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 160 } 161 }; 162 163 const ValueTypeActionImpl &getValueTypeActions() const { 164 return ValueTypeActions; 165 } 166 167 /// getTypeAction - Return how we should legalize values of this type, either 168 /// it is already legal (return 'Legal') or we need to promote it to a larger 169 /// type (return 'Promote'), or we need to expand it into multiple registers 170 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 171 LegalizeAction getTypeAction(MVT::ValueType VT) const { 172 return ValueTypeActions.getTypeAction(VT); 173 } 174 175 /// getTypeToTransformTo - For types supported by the target, this is an 176 /// identity function. For types that must be promoted to larger types, this 177 /// returns the larger type to promote to. For integer types that are larger 178 /// than the largest integer register, this contains one step in the expansion 179 /// to get to the smaller register. For illegal floating point types, this 180 /// returns the integer type to transform to. 181 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 182 if (MVT::isExtendedValueType(VT)) 183 return MVT::getVectorType(MVT::getVectorElementType(VT), 184 MVT::getVectorNumElements(VT) / 2); 185 186 return TransformToType[VT]; 187 } 188 189 /// getTypeToExpandTo - For types supported by the target, this is an 190 /// identity function. For types that must be expanded (i.e. integer types 191 /// that are larger than the largest integer register or illegal floating 192 /// point types), this returns the largest legal type it will be expanded to. 193 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 194 assert(!MVT::isExtendedValueType(VT)); 195 while (true) { 196 switch (getTypeAction(VT)) { 197 case Legal: 198 return VT; 199 case Expand: 200 VT = getTypeToTransformTo(VT); 201 break; 202 default: 203 assert(false && "Type is not legal nor is it to be expanded!"); 204 return VT; 205 } 206 } 207 return VT; 208 } 209 210 /// getVectorTypeBreakdown - Vector types are broken down into some number of 211 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 212 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 213 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 214 /// 215 /// This method returns the number of registers needed, and the VT for each 216 /// register. It also returns the VT of the VectorType elements before they 217 /// are promoted/expanded. 218 /// 219 unsigned getVectorTypeBreakdown(MVT::ValueType VT, 220 MVT::ValueType &ElementVT, 221 MVT::ValueType &LegalElementVT) const; 222 223 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 224 legal_fpimm_iterator legal_fpimm_begin() const { 225 return LegalFPImmediates.begin(); 226 } 227 legal_fpimm_iterator legal_fpimm_end() const { 228 return LegalFPImmediates.end(); 229 } 230 231 /// isShuffleMaskLegal - Targets can use this to indicate that they only 232 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 233 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 234 /// are assumed to be legal. 235 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 236 return true; 237 } 238 239 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 240 /// used by Targets can use this to indicate if there is a suitable 241 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 242 /// pool entry. 243 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 244 MVT::ValueType EVT, 245 SelectionDAG &DAG) const { 246 return false; 247 } 248 249 /// getOperationAction - Return how this operation should be treated: either 250 /// it is legal, needs to be promoted to a larger size, needs to be 251 /// expanded to some other code sequence, or the target has a custom expander 252 /// for it. 253 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 254 return !MVT::isExtendedValueType(VT) ? 255 (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3) : 256 Expand; 257 } 258 259 /// isOperationLegal - Return true if the specified operation is legal on this 260 /// target. 261 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 262 return getOperationAction(Op, VT) == Legal || 263 getOperationAction(Op, VT) == Custom; 264 } 265 266 /// getLoadXAction - Return how this load with extension should be treated: 267 /// either it is legal, needs to be promoted to a larger size, needs to be 268 /// expanded to some other code sequence, or the target has a custom expander 269 /// for it. 270 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 271 return !MVT::isExtendedValueType(VT) ? 272 (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3) : 273 Expand; 274 } 275 276 /// isLoadXLegal - Return true if the specified load with extension is legal 277 /// on this target. 278 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 279 return getLoadXAction(LType, VT) == Legal || 280 getLoadXAction(LType, VT) == Custom; 281 } 282 283 /// getStoreXAction - Return how this store with truncation should be treated: 284 /// either it is legal, needs to be promoted to a larger size, needs to be 285 /// expanded to some other code sequence, or the target has a custom expander 286 /// for it. 287 LegalizeAction getStoreXAction(MVT::ValueType VT) const { 288 return !MVT::isExtendedValueType(VT) ? 289 (LegalizeAction)((StoreXActions >> (2*VT)) & 3) : 290 Expand; 291 } 292 293 /// isStoreXLegal - Return true if the specified store with truncation is 294 /// legal on this target. 295 bool isStoreXLegal(MVT::ValueType VT) const { 296 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom; 297 } 298 299 /// getIndexedLoadAction - Return how the indexed load should be treated: 300 /// either it is legal, needs to be promoted to a larger size, needs to be 301 /// expanded to some other code sequence, or the target has a custom expander 302 /// for it. 303 LegalizeAction 304 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 305 return !MVT::isExtendedValueType(VT) ? 306 (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3) : 307 Expand; 308 } 309 310 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 311 /// on this target. 312 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 313 return getIndexedLoadAction(IdxMode, VT) == Legal || 314 getIndexedLoadAction(IdxMode, VT) == Custom; 315 } 316 317 /// getIndexedStoreAction - Return how the indexed store should be treated: 318 /// either it is legal, needs to be promoted to a larger size, needs to be 319 /// expanded to some other code sequence, or the target has a custom expander 320 /// for it. 321 LegalizeAction 322 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 323 return !MVT::isExtendedValueType(VT) ? 324 (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3) : 325 Expand; 326 } 327 328 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 329 /// on this target. 330 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 331 return getIndexedStoreAction(IdxMode, VT) == Legal || 332 getIndexedStoreAction(IdxMode, VT) == Custom; 333 } 334 335 /// getTypeToPromoteTo - If the action for this operation is to promote, this 336 /// method returns the ValueType to promote to. 337 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 338 assert(getOperationAction(Op, VT) == Promote && 339 "This operation isn't promoted!"); 340 341 // See if this has an explicit type specified. 342 std::map<std::pair<unsigned, MVT::ValueType>, 343 MVT::ValueType>::const_iterator PTTI = 344 PromoteToType.find(std::make_pair(Op, VT)); 345 if (PTTI != PromoteToType.end()) return PTTI->second; 346 347 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 348 "Cannot autopromote this type, add it with AddPromotedToType."); 349 350 MVT::ValueType NVT = VT; 351 do { 352 NVT = (MVT::ValueType)(NVT+1); 353 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 354 "Didn't find type to promote to!"); 355 } while (!isTypeLegal(NVT) || 356 getOperationAction(Op, NVT) == Promote); 357 return NVT; 358 } 359 360 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 361 /// This is fixed by the LLVM operations except for the pointer size. If 362 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 363 /// counterpart (e.g. structs), otherwise it will assert. 364 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { 365 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); 366 return VT == MVT::iPTR ? PointerTy : VT; 367 } 368 369 /// getNumRegisters - Return the number of registers that this ValueType will 370 /// eventually require. This is one for any types promoted to live in larger 371 /// registers, but may be more than one for types (like i64) that are split 372 /// into pieces. 373 unsigned getNumRegisters(MVT::ValueType VT) const { 374 if (!MVT::isExtendedValueType(VT)) 375 return NumRegistersForVT[VT]; 376 377 MVT::ValueType VT1, VT2; 378 return getVectorTypeBreakdown(VT, VT1, VT2); 379 } 380 381 /// hasTargetDAGCombine - If true, the target has custom DAG combine 382 /// transformations that it can perform for the specified node. 383 bool hasTargetDAGCombine(ISD::NodeType NT) const { 384 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 385 } 386 387 /// This function returns the maximum number of store operations permitted 388 /// to replace a call to llvm.memset. The value is set by the target at the 389 /// performance threshold for such a replacement. 390 /// @brief Get maximum # of store operations permitted for llvm.memset 391 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 392 393 /// This function returns the maximum number of store operations permitted 394 /// to replace a call to llvm.memcpy. The value is set by the target at the 395 /// performance threshold for such a replacement. 396 /// @brief Get maximum # of store operations permitted for llvm.memcpy 397 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 398 399 /// This function returns the maximum number of store operations permitted 400 /// to replace a call to llvm.memmove. The value is set by the target at the 401 /// performance threshold for such a replacement. 402 /// @brief Get maximum # of store operations permitted for llvm.memmove 403 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 404 405 /// This function returns true if the target allows unaligned memory accesses. 406 /// This is used, for example, in situations where an array copy/move/set is 407 /// converted to a sequence of store operations. It's use helps to ensure that 408 /// such replacements don't generate code that causes an alignment error 409 /// (trap) on the target machine. 410 /// @brief Determine if the target supports unaligned memory accesses. 411 bool allowsUnalignedMemoryAccesses() const { 412 return allowUnalignedMemoryAccesses; 413 } 414 415 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 416 /// to implement llvm.setjmp. 417 bool usesUnderscoreSetJmp() const { 418 return UseUnderscoreSetJmp; 419 } 420 421 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 422 /// to implement llvm.longjmp. 423 bool usesUnderscoreLongJmp() const { 424 return UseUnderscoreLongJmp; 425 } 426 427 /// getStackPointerRegisterToSaveRestore - If a physical register, this 428 /// specifies the register that llvm.savestack/llvm.restorestack should save 429 /// and restore. 430 unsigned getStackPointerRegisterToSaveRestore() const { 431 return StackPointerRegisterToSaveRestore; 432 } 433 434 /// getExceptionAddressRegister - If a physical register, this returns 435 /// the register that receives the exception address on entry to a landing 436 /// pad. 437 unsigned getExceptionAddressRegister() const { 438 return ExceptionPointerRegister; 439 } 440 441 /// getExceptionSelectorRegister - If a physical register, this returns 442 /// the register that receives the exception typeid on entry to a landing 443 /// pad. 444 unsigned getExceptionSelectorRegister() const { 445 return ExceptionSelectorRegister; 446 } 447 448 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 449 /// set, the default is 200) 450 unsigned getJumpBufSize() const { 451 return JumpBufSize; 452 } 453 454 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 455 /// (if never set, the default is 0) 456 unsigned getJumpBufAlignment() const { 457 return JumpBufAlignment; 458 } 459 460 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 461 /// limit. Any block whose size is greater should not be predicated. 462 virtual unsigned getIfCvtBlockSizeLimit() const { 463 return IfCvtBlockSizeLimit; 464 } 465 466 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 467 /// block to be considered for duplication. Any block whose size is greater 468 /// should not be duplicated to facilitate its predication. 469 virtual unsigned getIfCvtDupBlockSizeLimit() const { 470 return IfCvtDupBlockSizeLimit; 471 } 472 473 /// getPreIndexedAddressParts - returns true by value, base pointer and 474 /// offset pointer and addressing mode by reference if the node's address 475 /// can be legally represented as pre-indexed load / store address. 476 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 477 SDOperand &Offset, 478 ISD::MemIndexedMode &AM, 479 SelectionDAG &DAG) { 480 return false; 481 } 482 483 /// getPostIndexedAddressParts - returns true by value, base pointer and 484 /// offset pointer and addressing mode by reference if this node can be 485 /// combined with a load / store to form a post-indexed load / store. 486 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 487 SDOperand &Base, SDOperand &Offset, 488 ISD::MemIndexedMode &AM, 489 SelectionDAG &DAG) { 490 return false; 491 } 492 493 //===--------------------------------------------------------------------===// 494 // TargetLowering Optimization Methods 495 // 496 497 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 498 /// SDOperands for returning information from TargetLowering to its clients 499 /// that want to combine 500 struct TargetLoweringOpt { 501 SelectionDAG &DAG; 502 SDOperand Old; 503 SDOperand New; 504 505 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 506 507 bool CombineTo(SDOperand O, SDOperand N) { 508 Old = O; 509 New = N; 510 return true; 511 } 512 513 /// ShrinkDemandedConstant - Check to see if the specified operand of the 514 /// specified instruction is a constant integer. If so, check to see if there 515 /// are any bits set in the constant that are not demanded. If so, shrink the 516 /// constant and return true. 517 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 518 }; 519 520 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 521 /// DemandedMask bits of the result of Op are ever used downstream. If we can 522 /// use this information to simplify Op, create a new simplified DAG node and 523 /// return true, returning the original and new nodes in Old and New. 524 /// Otherwise, analyze the expression and return a mask of KnownOne and 525 /// KnownZero bits for the expression (used to simplify the caller). 526 /// The KnownZero/One bits may only be accurate for those bits in the 527 /// DemandedMask. 528 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 529 uint64_t &KnownZero, uint64_t &KnownOne, 530 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 531 532 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 533 /// Mask are known to be either zero or one and return them in the 534 /// KnownZero/KnownOne bitsets. 535 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 536 uint64_t Mask, 537 uint64_t &KnownZero, 538 uint64_t &KnownOne, 539 const SelectionDAG &DAG, 540 unsigned Depth = 0) const; 541 542 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 543 /// targets that want to expose additional information about sign bits to the 544 /// DAG Combiner. 545 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 546 unsigned Depth = 0) const; 547 548 struct DAGCombinerInfo { 549 void *DC; // The DAG Combiner object. 550 bool BeforeLegalize; 551 bool CalledByLegalizer; 552 public: 553 SelectionDAG &DAG; 554 555 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 556 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 557 558 bool isBeforeLegalize() const { return BeforeLegalize; } 559 bool isCalledByLegalizer() const { return CalledByLegalizer; } 560 561 void AddToWorklist(SDNode *N); 562 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 563 SDOperand CombineTo(SDNode *N, SDOperand Res); 564 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 565 }; 566 567 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 568 /// and cc. If it is unable to simplify it, return a null SDOperand. 569 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 570 ISD::CondCode Cond, bool foldBooleans, 571 DAGCombinerInfo &DCI) const; 572 573 /// PerformDAGCombine - This method will be invoked for all target nodes and 574 /// for any target-independent nodes that the target has registered with 575 /// invoke it for. 576 /// 577 /// The semantics are as follows: 578 /// Return Value: 579 /// SDOperand.Val == 0 - No change was made 580 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 581 /// otherwise - N should be replaced by the returned Operand. 582 /// 583 /// In addition, methods provided by DAGCombinerInfo may be used to perform 584 /// more complex transformations. 585 /// 586 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 587 588 //===--------------------------------------------------------------------===// 589 // TargetLowering Configuration Methods - These methods should be invoked by 590 // the derived class constructor to configure this object for the target. 591 // 592 593protected: 594 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 595 /// GOT for PC-relative code. 596 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 597 598 /// setShiftAmountType - Describe the type that should be used for shift 599 /// amounts. This type defaults to the pointer type. 600 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 601 602 /// setSetCCResultType - Describe the type that shoudl be used as the result 603 /// of a setcc operation. This defaults to the pointer type. 604 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 605 606 /// setSetCCResultContents - Specify how the target extends the result of a 607 /// setcc operation in a register. 608 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 609 610 /// setSchedulingPreference - Specify the target scheduling preference. 611 void setSchedulingPreference(SchedPreference Pref) { 612 SchedPreferenceInfo = Pref; 613 } 614 615 /// setShiftAmountFlavor - Describe how the target handles out of range shift 616 /// amounts. 617 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 618 ShiftAmtHandling = OORSA; 619 } 620 621 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 622 /// use _setjmp to implement llvm.setjmp or the non _ version. 623 /// Defaults to false. 624 void setUseUnderscoreSetJmp(bool Val) { 625 UseUnderscoreSetJmp = Val; 626 } 627 628 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 629 /// use _longjmp to implement llvm.longjmp or the non _ version. 630 /// Defaults to false. 631 void setUseUnderscoreLongJmp(bool Val) { 632 UseUnderscoreLongJmp = Val; 633 } 634 635 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 636 /// specifies the register that llvm.savestack/llvm.restorestack should save 637 /// and restore. 638 void setStackPointerRegisterToSaveRestore(unsigned R) { 639 StackPointerRegisterToSaveRestore = R; 640 } 641 642 /// setExceptionPointerRegister - If set to a physical register, this sets 643 /// the register that receives the exception address on entry to a landing 644 /// pad. 645 void setExceptionPointerRegister(unsigned R) { 646 ExceptionPointerRegister = R; 647 } 648 649 /// setExceptionSelectorRegister - If set to a physical register, this sets 650 /// the register that receives the exception typeid on entry to a landing 651 /// pad. 652 void setExceptionSelectorRegister(unsigned R) { 653 ExceptionSelectorRegister = R; 654 } 655 656 /// SelectIsExpensive - Tells the code generator not to expand operations 657 /// into sequences that use the select operations if possible. 658 void setSelectIsExpensive() { SelectIsExpensive = true; } 659 660 /// setIntDivIsCheap - Tells the code generator that integer divide is 661 /// expensive, and if possible, should be replaced by an alternate sequence 662 /// of instructions not containing an integer divide. 663 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 664 665 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 666 /// srl/add/sra for a signed divide by power of two, and let the target handle 667 /// it. 668 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 669 670 /// addRegisterClass - Add the specified register class as an available 671 /// regclass for the specified value type. This indicates the selector can 672 /// handle values of that class natively. 673 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 674 assert(!MVT::isExtendedValueType(VT)); 675 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 676 RegClassForVT[VT] = RC; 677 } 678 679 /// computeRegisterProperties - Once all of the register classes are added, 680 /// this allows us to compute derived properties we expose. 681 void computeRegisterProperties(); 682 683 /// setOperationAction - Indicate that the specified operation does not work 684 /// with the specified type and indicate what to do about it. 685 void setOperationAction(unsigned Op, MVT::ValueType VT, 686 LegalizeAction Action) { 687 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 688 "Table isn't big enough!"); 689 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 690 OpActions[Op] |= (uint64_t)Action << VT*2; 691 } 692 693 /// setLoadXAction - Indicate that the specified load with extension does not 694 /// work with the with specified type and indicate what to do about it. 695 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 696 LegalizeAction Action) { 697 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) && 698 "Table isn't big enough!"); 699 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 700 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 701 } 702 703 /// setStoreXAction - Indicate that the specified store with truncation does 704 /// not work with the with specified type and indicate what to do about it. 705 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) { 706 assert(VT < 32 && "Table isn't big enough!"); 707 StoreXActions &= ~(uint64_t(3UL) << VT*2); 708 StoreXActions |= (uint64_t)Action << VT*2; 709 } 710 711 /// setIndexedLoadAction - Indicate that the specified indexed load does or 712 /// does not work with the with specified type and indicate what to do abort 713 /// it. NOTE: All indexed mode loads are initialized to Expand in 714 /// TargetLowering.cpp 715 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 716 LegalizeAction Action) { 717 assert(VT < 32 && IdxMode < 718 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) && 719 "Table isn't big enough!"); 720 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 721 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 722 } 723 724 /// setIndexedStoreAction - Indicate that the specified indexed store does or 725 /// does not work with the with specified type and indicate what to do about 726 /// it. NOTE: All indexed mode stores are initialized to Expand in 727 /// TargetLowering.cpp 728 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 729 LegalizeAction Action) { 730 assert(VT < 32 && IdxMode < 731 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) && 732 "Table isn't big enough!"); 733 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 734 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 735 } 736 737 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 738 /// promotion code defaults to trying a larger integer/fp until it can find 739 /// one that works. If that default is insufficient, this method can be used 740 /// by the target to override the default. 741 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 742 MVT::ValueType DestVT) { 743 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 744 } 745 746 /// addLegalFPImmediate - Indicate that this target can instruction select 747 /// the specified FP immediate natively. 748 void addLegalFPImmediate(double Imm) { 749 LegalFPImmediates.push_back(Imm); 750 } 751 752 /// setTargetDAGCombine - Targets should invoke this method for each target 753 /// independent node that they want to provide a custom DAG combiner for by 754 /// implementing the PerformDAGCombine virtual method. 755 void setTargetDAGCombine(ISD::NodeType NT) { 756 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 757 } 758 759 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 760 /// bytes); default is 200 761 void setJumpBufSize(unsigned Size) { 762 JumpBufSize = Size; 763 } 764 765 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 766 /// alignment (in bytes); default is 0 767 void setJumpBufAlignment(unsigned Align) { 768 JumpBufAlignment = Align; 769 } 770 771 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 772 /// limit (in number of instructions); default is 2. 773 void setIfCvtBlockSizeLimit(unsigned Limit) { 774 IfCvtBlockSizeLimit = Limit; 775 } 776 777 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 778 /// of instructions) to be considered for code duplication during 779 /// if-conversion; default is 2. 780 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 781 IfCvtDupBlockSizeLimit = Limit; 782 } 783 784public: 785 786 //===--------------------------------------------------------------------===// 787 // Lowering methods - These methods must be implemented by targets so that 788 // the SelectionDAGLowering code knows how to lower these. 789 // 790 791 /// LowerArguments - This hook must be implemented to indicate how we should 792 /// lower the arguments for the specified function, into the specified DAG. 793 virtual std::vector<SDOperand> 794 LowerArguments(Function &F, SelectionDAG &DAG); 795 796 /// LowerCallTo - This hook lowers an abstract call to a function into an 797 /// actual call. This returns a pair of operands. The first element is the 798 /// return value for the function (if RetTy is not VoidTy). The second 799 /// element is the outgoing token chain. 800 struct ArgListEntry { 801 SDOperand Node; 802 const Type* Ty; 803 bool isSExt; 804 bool isZExt; 805 bool isInReg; 806 bool isSRet; 807 808 ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false) { }; 809 }; 810 typedef std::vector<ArgListEntry> ArgListTy; 811 virtual std::pair<SDOperand, SDOperand> 812 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 813 bool isVarArg, unsigned CallingConv, bool isTailCall, 814 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 815 816 /// LowerOperation - This callback is invoked for operations that are 817 /// unsupported by the target, which are registered to use 'custom' lowering, 818 /// and whose defined values are all legal. 819 /// If the target has no operations that require custom lowering, it need not 820 /// implement this. The default implementation of this aborts. 821 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 822 823 /// CustomPromoteOperation - This callback is invoked for operations that are 824 /// unsupported by the target, are registered to use 'custom' lowering, and 825 /// whose type needs to be promoted. 826 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 827 828 /// getTargetNodeName() - This method returns the name of a target specific 829 /// DAG node. 830 virtual const char *getTargetNodeName(unsigned Opcode) const; 831 832 //===--------------------------------------------------------------------===// 833 // Inline Asm Support hooks 834 // 835 836 enum ConstraintType { 837 C_Register, // Constraint represents a single register. 838 C_RegisterClass, // Constraint represents one or more registers. 839 C_Memory, // Memory constraint. 840 C_Other, // Something else. 841 C_Unknown // Unsupported constraint. 842 }; 843 844 /// getConstraintType - Given a constraint, return the type of constraint it 845 /// is for this target. 846 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 847 848 849 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 850 /// return a list of registers that can be used to satisfy the constraint. 851 /// This should only be used for C_RegisterClass constraints. 852 virtual std::vector<unsigned> 853 getRegClassForInlineAsmConstraint(const std::string &Constraint, 854 MVT::ValueType VT) const; 855 856 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 857 /// {edx}), return the register number and the register class for the 858 /// register. 859 /// 860 /// Given a register class constraint, like 'r', if this corresponds directly 861 /// to an LLVM register class, return a register of 0 and the register class 862 /// pointer. 863 /// 864 /// This should only be used for C_Register constraints. On error, 865 /// this returns a register number of 0 and a null register class pointer.. 866 virtual std::pair<unsigned, const TargetRegisterClass*> 867 getRegForInlineAsmConstraint(const std::string &Constraint, 868 MVT::ValueType VT) const; 869 870 871 /// isOperandValidForConstraint - Return the specified operand (possibly 872 /// modified) if the specified SDOperand is valid for the specified target 873 /// constraint letter, otherwise return null. 874 virtual SDOperand 875 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter, 876 SelectionDAG &DAG); 877 878 //===--------------------------------------------------------------------===// 879 // Scheduler hooks 880 // 881 882 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 883 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 884 // instructions are special in various ways, which require special support to 885 // insert. The specified MachineInstr is created but not inserted into any 886 // basic blocks, and the scheduler passes ownership of it to this method. 887 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 888 MachineBasicBlock *MBB); 889 890 //===--------------------------------------------------------------------===// 891 // Addressing mode description hooks (used by LSR etc). 892 // 893 894 /// AddrMode - This represents an addressing mode of: 895 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 896 /// If BaseGV is null, there is no BaseGV. 897 /// If BaseOffs is zero, there is no base offset. 898 /// If HasBaseReg is false, there is no base register. 899 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 900 /// no scale. 901 /// 902 struct AddrMode { 903 GlobalValue *BaseGV; 904 int64_t BaseOffs; 905 bool HasBaseReg; 906 int64_t Scale; 907 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 908 }; 909 910 /// isLegalAddressingMode - Return true if the addressing mode represented by 911 /// AM is legal for this target, for a load/store of the specified type. 912 /// TODO: Handle pre/postinc as well. 913 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 914 915 //===--------------------------------------------------------------------===// 916 // Div utility functions 917 // 918 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 919 std::vector<SDNode*>* Created) const; 920 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 921 std::vector<SDNode*>* Created) const; 922 923 924 //===--------------------------------------------------------------------===// 925 // Runtime Library hooks 926 // 927 928 /// setLibcallName - Rename the default libcall routine name for the specified 929 /// libcall. 930 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 931 LibcallRoutineNames[Call] = Name; 932 } 933 934 /// getLibcallName - Get the libcall routine name for the specified libcall. 935 /// 936 const char *getLibcallName(RTLIB::Libcall Call) const { 937 return LibcallRoutineNames[Call]; 938 } 939 940 /// setCmpLibcallCC - Override the default CondCode to be used to test the 941 /// result of the comparison libcall against zero. 942 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 943 CmpLibcallCCs[Call] = CC; 944 } 945 946 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 947 /// the comparison libcall against zero. 948 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 949 return CmpLibcallCCs[Call]; 950 } 951 952private: 953 TargetMachine &TM; 954 const TargetData *TD; 955 956 /// IsLittleEndian - True if this is a little endian target. 957 /// 958 bool IsLittleEndian; 959 960 /// PointerTy - The type to use for pointers, usually i32 or i64. 961 /// 962 MVT::ValueType PointerTy; 963 964 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 965 /// 966 bool UsesGlobalOffsetTable; 967 968 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 969 /// PointerTy is. 970 MVT::ValueType ShiftAmountTy; 971 972 OutOfRangeShiftAmount ShiftAmtHandling; 973 974 /// SelectIsExpensive - Tells the code generator not to expand operations 975 /// into sequences that use the select operations if possible. 976 bool SelectIsExpensive; 977 978 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 979 /// constants into a sequence of muls, adds, and shifts. This is a hack until 980 /// a real cost model is in place. If we ever optimize for size, this will be 981 /// set to true unconditionally. 982 bool IntDivIsCheap; 983 984 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 985 /// srl/add/sra for a signed divide by power of two, and let the target handle 986 /// it. 987 bool Pow2DivIsCheap; 988 989 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 990 /// PointerTy. 991 MVT::ValueType SetCCResultTy; 992 993 /// SetCCResultContents - Information about the contents of the high-bits in 994 /// the result of a setcc comparison operation. 995 SetCCResultValue SetCCResultContents; 996 997 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 998 /// total cycles or lowest register usage. 999 SchedPreference SchedPreferenceInfo; 1000 1001 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1002 /// llvm.setjmp. Defaults to false. 1003 bool UseUnderscoreSetJmp; 1004 1005 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1006 /// llvm.longjmp. Defaults to false. 1007 bool UseUnderscoreLongJmp; 1008 1009 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1010 unsigned JumpBufSize; 1011 1012 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1013 /// buffers 1014 unsigned JumpBufAlignment; 1015 1016 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1017 /// if-converted. 1018 unsigned IfCvtBlockSizeLimit; 1019 1020 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1021 /// duplicated during if-conversion. 1022 unsigned IfCvtDupBlockSizeLimit; 1023 1024 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1025 /// specifies the register that llvm.savestack/llvm.restorestack should save 1026 /// and restore. 1027 unsigned StackPointerRegisterToSaveRestore; 1028 1029 /// ExceptionPointerRegister - If set to a physical register, this specifies 1030 /// the register that receives the exception address on entry to a landing 1031 /// pad. 1032 unsigned ExceptionPointerRegister; 1033 1034 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1035 /// the register that receives the exception typeid on entry to a landing 1036 /// pad. 1037 unsigned ExceptionSelectorRegister; 1038 1039 /// RegClassForVT - This indicates the default register class to use for 1040 /// each ValueType the target supports natively. 1041 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1042 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1043 1044 /// TransformToType - For any value types we are promoting or expanding, this 1045 /// contains the value type that we are changing to. For Expanded types, this 1046 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1047 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1048 /// by the system, this holds the same type (e.g. i32 -> i32). 1049 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1050 1051 /// OpActions - For each operation and each value type, keep a LegalizeAction 1052 /// that indicates how instruction selection should deal with the operation. 1053 /// Most operations are Legal (aka, supported natively by the target), but 1054 /// operations that are not should be described. Note that operations on 1055 /// non-legal value types are not described here. 1056 uint64_t OpActions[156]; 1057 1058 /// LoadXActions - For each load of load extension type and each value type, 1059 /// keep a LegalizeAction that indicates how instruction selection should deal 1060 /// with the load. 1061 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1062 1063 /// StoreXActions - For each store with truncation of each value type, keep a 1064 /// LegalizeAction that indicates how instruction selection should deal with 1065 /// the store. 1066 uint64_t StoreXActions; 1067 1068 /// IndexedModeActions - For each indexed mode and each value type, keep a 1069 /// pair of LegalizeAction that indicates how instruction selection should 1070 /// deal with the load / store. 1071 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1072 1073 ValueTypeActionImpl ValueTypeActions; 1074 1075 std::vector<double> LegalFPImmediates; 1076 1077 std::vector<std::pair<MVT::ValueType, 1078 TargetRegisterClass*> > AvailableRegClasses; 1079 1080 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1081 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1082 /// which sets a bit in this array. 1083 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1084 1085 /// PromoteToType - For operations that must be promoted to a specific type, 1086 /// this holds the destination type. This map should be sparse, so don't hold 1087 /// it as an array. 1088 /// 1089 /// Targets add entries to this map with AddPromotedToType(..), clients access 1090 /// this with getTypeToPromoteTo(..). 1091 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1092 1093 /// LibcallRoutineNames - Stores the name each libcall. 1094 /// 1095 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1096 1097 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1098 /// of each of the comparison libcall against zero. 1099 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1100 1101protected: 1102 /// When lowering %llvm.memset this field specifies the maximum number of 1103 /// store operations that may be substituted for the call to memset. Targets 1104 /// must set this value based on the cost threshold for that target. Targets 1105 /// should assume that the memset will be done using as many of the largest 1106 /// store operations first, followed by smaller ones, if necessary, per 1107 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1108 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1109 /// store. This only applies to setting a constant array of a constant size. 1110 /// @brief Specify maximum number of store instructions per memset call. 1111 unsigned maxStoresPerMemset; 1112 1113 /// When lowering %llvm.memcpy this field specifies the maximum number of 1114 /// store operations that may be substituted for a call to memcpy. Targets 1115 /// must set this value based on the cost threshold for that target. Targets 1116 /// should assume that the memcpy will be done using as many of the largest 1117 /// store operations first, followed by smaller ones, if necessary, per 1118 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1119 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1120 /// and one 1-byte store. This only applies to copying a constant array of 1121 /// constant size. 1122 /// @brief Specify maximum bytes of store instructions per memcpy call. 1123 unsigned maxStoresPerMemcpy; 1124 1125 /// When lowering %llvm.memmove this field specifies the maximum number of 1126 /// store instructions that may be substituted for a call to memmove. Targets 1127 /// must set this value based on the cost threshold for that target. Targets 1128 /// should assume that the memmove will be done using as many of the largest 1129 /// store operations first, followed by smaller ones, if necessary, per 1130 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1131 /// with 8-bit alignment would result in nine 1-byte stores. This only 1132 /// applies to copying a constant array of constant size. 1133 /// @brief Specify maximum bytes of store instructions per memmove call. 1134 unsigned maxStoresPerMemmove; 1135 1136 /// This field specifies whether the target machine permits unaligned memory 1137 /// accesses. This is used, for example, to determine the size of store 1138 /// operations when copying small arrays and other similar tasks. 1139 /// @brief Indicate whether the target permits unaligned memory accesses. 1140 bool allowUnalignedMemoryAccesses; 1141}; 1142} // end llvm namespace 1143 1144#endif 1145