TargetLowering.h revision 75c2d0a351cecb222af1da8734a8c1a32f9177a3
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 16// In addition it has a few other components, like information about FP 17// immediates. 18// 19//===----------------------------------------------------------------------===// 20 21#ifndef LLVM_TARGET_TARGETLOWERING_H 22#define LLVM_TARGET_TARGETLOWERING_H 23 24#include "llvm/Type.h" 25#include "llvm/CodeGen/ValueTypes.h" 26#include <vector> 27 28namespace llvm { 29 class Function; 30 class TargetMachine; 31 class TargetData; 32 class TargetRegisterClass; 33 class SDNode; 34 class SDOperand; 35 class SelectionDAG; 36 37//===----------------------------------------------------------------------===// 38/// TargetLowering - This class defines information used to lower LLVM code to 39/// legal SelectionDAG operators that the target instruction selector can accept 40/// natively. 41/// 42/// This class also defines callbacks that targets must implement to lower 43/// target-specific constructs to SelectionDAG operators. 44/// 45class TargetLowering { 46 TargetMachine &TM; 47 const TargetData &TD; 48 49 MVT::ValueType PointerTy; 50 bool IsLittleEndian; 51 52 /// RegClassForVT - This indicates the default register class to use for 53 /// each ValueType the target supports natively. 54 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 55 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; 56 57 unsigned short UnsupportedOps[128]; 58 59 std::vector<double> LegalFPImmediates; 60 61 std::vector<std::pair<MVT::ValueType, 62 TargetRegisterClass*> > AvailableRegClasses; 63public: 64 TargetLowering(TargetMachine &TM); 65 virtual ~TargetLowering() {} 66 67 TargetMachine &getTargetMachine() const { return TM; } 68 const TargetData &getTargetData() const { return TD; } 69 70 bool isLittleEndian() const { return IsLittleEndian; } 71 MVT::ValueType getPointerTy() const { return PointerTy; } 72 73 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) { 74 TargetRegisterClass *RC = RegClassForVT[VT]; 75 assert(RC && "This value type is not natively supported!"); 76 return RC; 77 } 78 79 /// hasNativeSupportFor 80 bool hasNativeSupportFor(MVT::ValueType VT) { 81 return RegClassForVT[VT] != 0; 82 } 83 84 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 85 legal_fpimm_iterator legal_fpimm_begin() const { 86 return LegalFPImmediates.begin(); 87 } 88 legal_fpimm_iterator legal_fpimm_end() const { 89 return LegalFPImmediates.end(); 90 } 91 92 bool isOperationSupported(unsigned Op, MVT::ValueType VT) { 93 return (UnsupportedOps[Op] & (1 << VT)) == 0; 94 } 95 96 MVT::ValueType getValueType(const Type *Ty) { 97 switch (Ty->getTypeID()) { 98 default: assert(0 && "Unknown type!"); 99 case Type::VoidTyID: return MVT::isVoid; 100 case Type::BoolTyID: return MVT::i1; 101 case Type::UByteTyID: 102 case Type::SByteTyID: return MVT::i8; 103 case Type::ShortTyID: 104 case Type::UShortTyID: return MVT::i16; 105 case Type::IntTyID: 106 case Type::UIntTyID: return MVT::i32; 107 case Type::LongTyID: 108 case Type::ULongTyID: return MVT::i64; 109 case Type::FloatTyID: return MVT::f32; 110 case Type::DoubleTyID: return MVT::f64; 111 case Type::PointerTyID: return PointerTy; 112 } 113 } 114 115 /// getNumElements - Return the number of registers that this ValueType will 116 /// eventually require. This is always one for all non-integer types, is 117 /// one for any types promoted to live in larger registers, but may be more 118 /// than one for types (like i64) that are split into pieces. 119 unsigned getNumElements(MVT::ValueType VT) const { 120 return NumElementsForVT[VT]; 121 } 122 123 //===--------------------------------------------------------------------===// 124 // TargetLowering Configuration Methods - These methods should be invoked by 125 // the derived class constructor to configure this object for the target. 126 // 127 128protected: 129 130 /// addRegisterClass - Add the specified register class as an available 131 /// regclass for the specified value type. This indicates the selector can 132 /// handle values of that class natively. 133 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 134 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 135 RegClassForVT[VT] = RC; 136 } 137 138 /// computeRegisterProperties - Once all of the register classes are added, 139 /// this allows us to compute derived properties we expose. 140 void computeRegisterProperties(); 141 142 143 void setOperationUnsupported(unsigned Op, MVT::ValueType VT) { 144 assert(VT < 16 && "Too many value types!"); 145 UnsupportedOps[Op] |= 1 << VT; 146 } 147 148 /// addLegalFPImmediate - Indicate that this target can instruction select 149 /// the specified FP immediate natively. 150 void addLegalFPImmediate(double Imm) { 151 LegalFPImmediates.push_back(Imm); 152 } 153 154 155public: 156 157 //===--------------------------------------------------------------------===// 158 // Lowering methods - These methods must be implemented by targets so that 159 // the SelectionDAGLowering code knows how to lower these. 160 // 161 162 /// LowerArguments - This hook must be implemented to indicate how we should 163 /// lower the arguments for the specified function, into the specified DAG. 164 virtual std::vector<SDOperand> 165 LowerArguments(Function &F, SelectionDAG &DAG) = 0; 166 167 /// LowerCallTo - This hook lowers an abstract call to a function into an 168 /// actual call. 169 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy; 170 virtual SDNode *LowerCallTo(const Type *RetTy, SDOperand Callee, 171 ArgListTy &Args, SelectionDAG &DAG) = 0; 172}; 173} // end llvm namespace 174 175#endif 176