TargetLowering.h revision 81975f6dfd9d306d0ea7ce3ef22561c949de9af9
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include <map> 28#include <vector> 29 30namespace llvm { 31 class Value; 32 class Function; 33 class TargetMachine; 34 class TargetData; 35 class TargetRegisterClass; 36 class SDNode; 37 class SDOperand; 38 class SelectionDAG; 39 class MachineBasicBlock; 40 class MachineInstr; 41 class VectorType; 42 43//===----------------------------------------------------------------------===// 44/// TargetLowering - This class defines information used to lower LLVM code to 45/// legal SelectionDAG operators that the target instruction selector can accept 46/// natively. 47/// 48/// This class also defines callbacks that targets must implement to lower 49/// target-specific constructs to SelectionDAG operators. 50/// 51class TargetLowering { 52public: 53 /// LegalizeAction - This enum indicates whether operations are valid for a 54 /// target, and if not, what action should be used to make them valid. 55 enum LegalizeAction { 56 Legal, // The target natively supports this operation. 57 Promote, // This operation should be executed in a larger type. 58 Expand, // Try to expand this to other ops, otherwise use a libcall. 59 Custom // Use the LowerOperation hook to implement custom lowering. 60 }; 61 62 enum OutOfRangeShiftAmount { 63 Undefined, // Oversized shift amounts are undefined (default). 64 Mask, // Shift amounts are auto masked (anded) to value size. 65 Extend // Oversized shift pulls in zeros or sign bits. 66 }; 67 68 enum SetCCResultValue { 69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 72 }; 73 74 enum SchedPreference { 75 SchedulingForLatency, // Scheduling for shortest total latency. 76 SchedulingForRegPressure // Scheduling for lowest register pressure. 77 }; 78 79 explicit TargetLowering(TargetMachine &TM); 80 virtual ~TargetLowering(); 81 82 TargetMachine &getTargetMachine() const { return TM; } 83 const TargetData *getTargetData() const { return TD; } 84 85 bool isLittleEndian() const { return IsLittleEndian; } 86 MVT::ValueType getPointerTy() const { return PointerTy; } 87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 89 90 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 91 /// codegen. 92 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 93 94 /// isSelectExpensive - Return true if the select operation is expensive for 95 /// this target. 96 bool isSelectExpensive() const { return SelectIsExpensive; } 97 98 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 99 /// a sequence of several shifts, adds, and multiplies for this target. 100 bool isIntDivCheap() const { return IntDivIsCheap; } 101 102 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 103 /// srl/add/sra. 104 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 105 106 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 107 /// 108 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 109 110 /// getSetCCResultContents - For targets without boolean registers, this flag 111 /// returns information about the contents of the high-bits in the setcc 112 /// result register. 113 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 114 115 /// getSchedulingPreference - Return target scheduling preference. 116 SchedPreference getSchedulingPreference() const { 117 return SchedPreferenceInfo; 118 } 119 120 /// getRegClassFor - Return the register class that should be used for the 121 /// specified value type. This may only be called on legal types. 122 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 123 assert(!MVT::isExtendedVT(VT)); 124 TargetRegisterClass *RC = RegClassForVT[VT]; 125 assert(RC && "This value type is not natively supported!"); 126 return RC; 127 } 128 129 /// isTypeLegal - Return true if the target has native support for the 130 /// specified value type. This means that it has a register that directly 131 /// holds it without promotions or expansions. 132 bool isTypeLegal(MVT::ValueType VT) const { 133 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; 134 } 135 136 class ValueTypeActionImpl { 137 /// ValueTypeActions - This is a bitvector that contains two bits for each 138 /// value type, where the two bits correspond to the LegalizeAction enum. 139 /// This can be queried with "getTypeAction(VT)". 140 uint32_t ValueTypeActions[2]; 141 public: 142 ValueTypeActionImpl() { 143 ValueTypeActions[0] = ValueTypeActions[1] = 0; 144 } 145 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 146 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 147 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 148 } 149 150 LegalizeAction getTypeAction(MVT::ValueType VT) const { 151 if (MVT::isExtendedVT(VT)) return Expand; 152 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 153 } 154 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 155 assert(!MVT::isExtendedVT(VT)); 156 assert(unsigned(VT >> 4) < 157 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 158 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 159 } 160 }; 161 162 const ValueTypeActionImpl &getValueTypeActions() const { 163 return ValueTypeActions; 164 } 165 166 /// getTypeAction - Return how we should legalize values of this type, either 167 /// it is already legal (return 'Legal') or we need to promote it to a larger 168 /// type (return 'Promote'), or we need to expand it into multiple registers 169 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 170 LegalizeAction getTypeAction(MVT::ValueType VT) const { 171 return ValueTypeActions.getTypeAction(VT); 172 } 173 174 /// getTypeToTransformTo - For types supported by the target, this is an 175 /// identity function. For types that must be promoted to larger types, this 176 /// returns the larger type to promote to. For integer types that are larger 177 /// than the largest integer register, this contains one step in the expansion 178 /// to get to the smaller register. For illegal floating point types, this 179 /// returns the integer type to transform to. 180 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 181 if (MVT::isExtendedVT(VT)) 182 return MVT::getVectorType(MVT::getVectorElementType(VT), 183 MVT::getVectorNumElements(VT) / 2); 184 185 return TransformToType[VT]; 186 } 187 188 /// getTypeToExpandTo - For types supported by the target, this is an 189 /// identity function. For types that must be expanded (i.e. integer types 190 /// that are larger than the largest integer register or illegal floating 191 /// point types), this returns the largest legal type it will be expanded to. 192 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 193 assert(!MVT::isExtendedVT(VT)); 194 while (true) { 195 switch (getTypeAction(VT)) { 196 case Legal: 197 return VT; 198 case Expand: 199 VT = getTypeToTransformTo(VT); 200 break; 201 default: 202 assert(false && "Type is not legal nor is it to be expanded!"); 203 return VT; 204 } 205 } 206 return VT; 207 } 208 209 /// getVectorTypeBreakdown - Vector types are broken down into some number of 210 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 211 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 212 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 213 /// 214 /// This method returns the number of registers needed, and the VT for each 215 /// register. It also returns the VT and quantity of the intermediate values 216 /// before they are promoted/expanded. 217 /// 218 unsigned getVectorTypeBreakdown(MVT::ValueType VT, 219 MVT::ValueType &IntermediateVT, 220 unsigned &NumIntermediates, 221 MVT::ValueType &RegisterVT) const; 222 223 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 224 legal_fpimm_iterator legal_fpimm_begin() const { 225 return LegalFPImmediates.begin(); 226 } 227 legal_fpimm_iterator legal_fpimm_end() const { 228 return LegalFPImmediates.end(); 229 } 230 231 /// isShuffleMaskLegal - Targets can use this to indicate that they only 232 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 233 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 234 /// are assumed to be legal. 235 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 236 return true; 237 } 238 239 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 240 /// used by Targets can use this to indicate if there is a suitable 241 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 242 /// pool entry. 243 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 244 MVT::ValueType EVT, 245 SelectionDAG &DAG) const { 246 return false; 247 } 248 249 /// getOperationAction - Return how this operation should be treated: either 250 /// it is legal, needs to be promoted to a larger size, needs to be 251 /// expanded to some other code sequence, or the target has a custom expander 252 /// for it. 253 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 254 if (MVT::isExtendedVT(VT)) return Expand; 255 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 256 } 257 258 /// isOperationLegal - Return true if the specified operation is legal on this 259 /// target. 260 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 261 return getOperationAction(Op, VT) == Legal || 262 getOperationAction(Op, VT) == Custom; 263 } 264 265 /// getLoadXAction - Return how this load with extension should be treated: 266 /// either it is legal, needs to be promoted to a larger size, needs to be 267 /// expanded to some other code sequence, or the target has a custom expander 268 /// for it. 269 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 270 if (MVT::isExtendedVT(VT)) return Expand; 271 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); 272 } 273 274 /// isLoadXLegal - Return true if the specified load with extension is legal 275 /// on this target. 276 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 277 return getLoadXAction(LType, VT) == Legal || 278 getLoadXAction(LType, VT) == Custom; 279 } 280 281 /// getStoreXAction - Return how this store with truncation should be treated: 282 /// either it is legal, needs to be promoted to a larger size, needs to be 283 /// expanded to some other code sequence, or the target has a custom expander 284 /// for it. 285 LegalizeAction getStoreXAction(MVT::ValueType VT) const { 286 if (MVT::isExtendedVT(VT)) return Expand; 287 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3); 288 } 289 290 /// isStoreXLegal - Return true if the specified store with truncation is 291 /// legal on this target. 292 bool isStoreXLegal(MVT::ValueType VT) const { 293 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom; 294 } 295 296 /// getIndexedLoadAction - Return how the indexed load should be treated: 297 /// either it is legal, needs to be promoted to a larger size, needs to be 298 /// expanded to some other code sequence, or the target has a custom expander 299 /// for it. 300 LegalizeAction 301 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 302 if (MVT::isExtendedVT(VT)) return Expand; 303 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); 304 } 305 306 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 307 /// on this target. 308 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 309 return getIndexedLoadAction(IdxMode, VT) == Legal || 310 getIndexedLoadAction(IdxMode, VT) == Custom; 311 } 312 313 /// getIndexedStoreAction - Return how the indexed store should be treated: 314 /// either it is legal, needs to be promoted to a larger size, needs to be 315 /// expanded to some other code sequence, or the target has a custom expander 316 /// for it. 317 LegalizeAction 318 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 319 if (MVT::isExtendedVT(VT)) return Expand; 320 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); 321 } 322 323 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 324 /// on this target. 325 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 326 return getIndexedStoreAction(IdxMode, VT) == Legal || 327 getIndexedStoreAction(IdxMode, VT) == Custom; 328 } 329 330 /// getConvertAction - Return how the conversion should be treated: 331 /// either it is legal, needs to be promoted to a larger size, needs to be 332 /// expanded to some other code sequence, or the target has a custom expander 333 /// for it. 334 LegalizeAction 335 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 336 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 && 337 "Table isn't big enough!"); 338 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3); 339 } 340 341 /// isConvertLegal - Return true if the specified conversion is legal 342 /// on this target. 343 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 344 return getConvertAction(FromVT, ToVT) == Legal || 345 getConvertAction(FromVT, ToVT) == Custom; 346 } 347 348 /// getTypeToPromoteTo - If the action for this operation is to promote, this 349 /// method returns the ValueType to promote to. 350 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 351 assert(getOperationAction(Op, VT) == Promote && 352 "This operation isn't promoted!"); 353 354 // See if this has an explicit type specified. 355 std::map<std::pair<unsigned, MVT::ValueType>, 356 MVT::ValueType>::const_iterator PTTI = 357 PromoteToType.find(std::make_pair(Op, VT)); 358 if (PTTI != PromoteToType.end()) return PTTI->second; 359 360 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 361 "Cannot autopromote this type, add it with AddPromotedToType."); 362 363 MVT::ValueType NVT = VT; 364 do { 365 NVT = (MVT::ValueType)(NVT+1); 366 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 367 "Didn't find type to promote to!"); 368 } while (!isTypeLegal(NVT) || 369 getOperationAction(Op, NVT) == Promote); 370 return NVT; 371 } 372 373 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 374 /// This is fixed by the LLVM operations except for the pointer size. If 375 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 376 /// counterpart (e.g. structs), otherwise it will assert. 377 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { 378 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); 379 return VT == MVT::iPTR ? PointerTy : VT; 380 } 381 382 /// getRegisterType - Return the type of registers that this ValueType will 383 /// eventually require. 384 MVT::ValueType getRegisterType(MVT::ValueType VT) const { 385 if (!MVT::isExtendedVT(VT)) 386 return RegisterTypeForVT[VT]; 387 388 MVT::ValueType VT1, RegisterVT; 389 unsigned NumIntermediates; 390 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 391 return RegisterVT; 392 } 393 394 /// getNumRegisters - Return the number of registers that this ValueType will 395 /// eventually require. This is one for any types promoted to live in larger 396 /// registers, but may be more than one for types (like i64) that are split 397 /// into pieces. 398 unsigned getNumRegisters(MVT::ValueType VT) const { 399 if (!MVT::isExtendedVT(VT)) 400 return NumRegistersForVT[VT]; 401 402 MVT::ValueType VT1, VT2; 403 unsigned NumIntermediates; 404 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 405 } 406 407 /// hasTargetDAGCombine - If true, the target has custom DAG combine 408 /// transformations that it can perform for the specified node. 409 bool hasTargetDAGCombine(ISD::NodeType NT) const { 410 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 411 } 412 413 /// This function returns the maximum number of store operations permitted 414 /// to replace a call to llvm.memset. The value is set by the target at the 415 /// performance threshold for such a replacement. 416 /// @brief Get maximum # of store operations permitted for llvm.memset 417 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 418 419 /// This function returns the maximum number of store operations permitted 420 /// to replace a call to llvm.memcpy. The value is set by the target at the 421 /// performance threshold for such a replacement. 422 /// @brief Get maximum # of store operations permitted for llvm.memcpy 423 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 424 425 /// This function returns the maximum number of store operations permitted 426 /// to replace a call to llvm.memmove. The value is set by the target at the 427 /// performance threshold for such a replacement. 428 /// @brief Get maximum # of store operations permitted for llvm.memmove 429 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 430 431 /// This function returns true if the target allows unaligned memory accesses. 432 /// This is used, for example, in situations where an array copy/move/set is 433 /// converted to a sequence of store operations. It's use helps to ensure that 434 /// such replacements don't generate code that causes an alignment error 435 /// (trap) on the target machine. 436 /// @brief Determine if the target supports unaligned memory accesses. 437 bool allowsUnalignedMemoryAccesses() const { 438 return allowUnalignedMemoryAccesses; 439 } 440 441 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 442 /// to implement llvm.setjmp. 443 bool usesUnderscoreSetJmp() const { 444 return UseUnderscoreSetJmp; 445 } 446 447 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 448 /// to implement llvm.longjmp. 449 bool usesUnderscoreLongJmp() const { 450 return UseUnderscoreLongJmp; 451 } 452 453 /// getStackPointerRegisterToSaveRestore - If a physical register, this 454 /// specifies the register that llvm.savestack/llvm.restorestack should save 455 /// and restore. 456 unsigned getStackPointerRegisterToSaveRestore() const { 457 return StackPointerRegisterToSaveRestore; 458 } 459 460 /// getExceptionAddressRegister - If a physical register, this returns 461 /// the register that receives the exception address on entry to a landing 462 /// pad. 463 unsigned getExceptionAddressRegister() const { 464 return ExceptionPointerRegister; 465 } 466 467 /// getExceptionSelectorRegister - If a physical register, this returns 468 /// the register that receives the exception typeid on entry to a landing 469 /// pad. 470 unsigned getExceptionSelectorRegister() const { 471 return ExceptionSelectorRegister; 472 } 473 474 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 475 /// set, the default is 200) 476 unsigned getJumpBufSize() const { 477 return JumpBufSize; 478 } 479 480 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 481 /// (if never set, the default is 0) 482 unsigned getJumpBufAlignment() const { 483 return JumpBufAlignment; 484 } 485 486 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 487 /// limit. Any block whose size is greater should not be predicated. 488 virtual unsigned getIfCvtBlockSizeLimit() const { 489 return IfCvtBlockSizeLimit; 490 } 491 492 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 493 /// block to be considered for duplication. Any block whose size is greater 494 /// should not be duplicated to facilitate its predication. 495 virtual unsigned getIfCvtDupBlockSizeLimit() const { 496 return IfCvtDupBlockSizeLimit; 497 } 498 499 /// getPreIndexedAddressParts - returns true by value, base pointer and 500 /// offset pointer and addressing mode by reference if the node's address 501 /// can be legally represented as pre-indexed load / store address. 502 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 503 SDOperand &Offset, 504 ISD::MemIndexedMode &AM, 505 SelectionDAG &DAG) { 506 return false; 507 } 508 509 /// getPostIndexedAddressParts - returns true by value, base pointer and 510 /// offset pointer and addressing mode by reference if this node can be 511 /// combined with a load / store to form a post-indexed load / store. 512 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 513 SDOperand &Base, SDOperand &Offset, 514 ISD::MemIndexedMode &AM, 515 SelectionDAG &DAG) { 516 return false; 517 } 518 519 //===--------------------------------------------------------------------===// 520 // TargetLowering Optimization Methods 521 // 522 523 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 524 /// SDOperands for returning information from TargetLowering to its clients 525 /// that want to combine 526 struct TargetLoweringOpt { 527 SelectionDAG &DAG; 528 SDOperand Old; 529 SDOperand New; 530 531 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 532 533 bool CombineTo(SDOperand O, SDOperand N) { 534 Old = O; 535 New = N; 536 return true; 537 } 538 539 /// ShrinkDemandedConstant - Check to see if the specified operand of the 540 /// specified instruction is a constant integer. If so, check to see if there 541 /// are any bits set in the constant that are not demanded. If so, shrink the 542 /// constant and return true. 543 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 544 }; 545 546 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 547 /// DemandedMask bits of the result of Op are ever used downstream. If we can 548 /// use this information to simplify Op, create a new simplified DAG node and 549 /// return true, returning the original and new nodes in Old and New. 550 /// Otherwise, analyze the expression and return a mask of KnownOne and 551 /// KnownZero bits for the expression (used to simplify the caller). 552 /// The KnownZero/One bits may only be accurate for those bits in the 553 /// DemandedMask. 554 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 555 uint64_t &KnownZero, uint64_t &KnownOne, 556 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 557 558 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 559 /// Mask are known to be either zero or one and return them in the 560 /// KnownZero/KnownOne bitsets. 561 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 562 uint64_t Mask, 563 uint64_t &KnownZero, 564 uint64_t &KnownOne, 565 const SelectionDAG &DAG, 566 unsigned Depth = 0) const; 567 568 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 569 /// targets that want to expose additional information about sign bits to the 570 /// DAG Combiner. 571 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 572 unsigned Depth = 0) const; 573 574 struct DAGCombinerInfo { 575 void *DC; // The DAG Combiner object. 576 bool BeforeLegalize; 577 bool CalledByLegalizer; 578 public: 579 SelectionDAG &DAG; 580 581 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 582 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 583 584 bool isBeforeLegalize() const { return BeforeLegalize; } 585 bool isCalledByLegalizer() const { return CalledByLegalizer; } 586 587 void AddToWorklist(SDNode *N); 588 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 589 SDOperand CombineTo(SDNode *N, SDOperand Res); 590 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 591 }; 592 593 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 594 /// and cc. If it is unable to simplify it, return a null SDOperand. 595 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 596 ISD::CondCode Cond, bool foldBooleans, 597 DAGCombinerInfo &DCI) const; 598 599 /// PerformDAGCombine - This method will be invoked for all target nodes and 600 /// for any target-independent nodes that the target has registered with 601 /// invoke it for. 602 /// 603 /// The semantics are as follows: 604 /// Return Value: 605 /// SDOperand.Val == 0 - No change was made 606 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 607 /// otherwise - N should be replaced by the returned Operand. 608 /// 609 /// In addition, methods provided by DAGCombinerInfo may be used to perform 610 /// more complex transformations. 611 /// 612 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 613 614 //===--------------------------------------------------------------------===// 615 // TargetLowering Configuration Methods - These methods should be invoked by 616 // the derived class constructor to configure this object for the target. 617 // 618 619protected: 620 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 621 /// GOT for PC-relative code. 622 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 623 624 /// setShiftAmountType - Describe the type that should be used for shift 625 /// amounts. This type defaults to the pointer type. 626 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 627 628 /// setSetCCResultType - Describe the type that shoudl be used as the result 629 /// of a setcc operation. This defaults to the pointer type. 630 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 631 632 /// setSetCCResultContents - Specify how the target extends the result of a 633 /// setcc operation in a register. 634 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 635 636 /// setSchedulingPreference - Specify the target scheduling preference. 637 void setSchedulingPreference(SchedPreference Pref) { 638 SchedPreferenceInfo = Pref; 639 } 640 641 /// setShiftAmountFlavor - Describe how the target handles out of range shift 642 /// amounts. 643 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 644 ShiftAmtHandling = OORSA; 645 } 646 647 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 648 /// use _setjmp to implement llvm.setjmp or the non _ version. 649 /// Defaults to false. 650 void setUseUnderscoreSetJmp(bool Val) { 651 UseUnderscoreSetJmp = Val; 652 } 653 654 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 655 /// use _longjmp to implement llvm.longjmp or the non _ version. 656 /// Defaults to false. 657 void setUseUnderscoreLongJmp(bool Val) { 658 UseUnderscoreLongJmp = Val; 659 } 660 661 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 662 /// specifies the register that llvm.savestack/llvm.restorestack should save 663 /// and restore. 664 void setStackPointerRegisterToSaveRestore(unsigned R) { 665 StackPointerRegisterToSaveRestore = R; 666 } 667 668 /// setExceptionPointerRegister - If set to a physical register, this sets 669 /// the register that receives the exception address on entry to a landing 670 /// pad. 671 void setExceptionPointerRegister(unsigned R) { 672 ExceptionPointerRegister = R; 673 } 674 675 /// setExceptionSelectorRegister - If set to a physical register, this sets 676 /// the register that receives the exception typeid on entry to a landing 677 /// pad. 678 void setExceptionSelectorRegister(unsigned R) { 679 ExceptionSelectorRegister = R; 680 } 681 682 /// SelectIsExpensive - Tells the code generator not to expand operations 683 /// into sequences that use the select operations if possible. 684 void setSelectIsExpensive() { SelectIsExpensive = true; } 685 686 /// setIntDivIsCheap - Tells the code generator that integer divide is 687 /// expensive, and if possible, should be replaced by an alternate sequence 688 /// of instructions not containing an integer divide. 689 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 690 691 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 692 /// srl/add/sra for a signed divide by power of two, and let the target handle 693 /// it. 694 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 695 696 /// addRegisterClass - Add the specified register class as an available 697 /// regclass for the specified value type. This indicates the selector can 698 /// handle values of that class natively. 699 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 700 assert(!MVT::isExtendedVT(VT)); 701 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 702 RegClassForVT[VT] = RC; 703 } 704 705 /// computeRegisterProperties - Once all of the register classes are added, 706 /// this allows us to compute derived properties we expose. 707 void computeRegisterProperties(); 708 709 /// setOperationAction - Indicate that the specified operation does not work 710 /// with the specified type and indicate what to do about it. 711 void setOperationAction(unsigned Op, MVT::ValueType VT, 712 LegalizeAction Action) { 713 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 714 "Table isn't big enough!"); 715 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 716 OpActions[Op] |= (uint64_t)Action << VT*2; 717 } 718 719 /// setLoadXAction - Indicate that the specified load with extension does not 720 /// work with the with specified type and indicate what to do about it. 721 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 722 LegalizeAction Action) { 723 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) && 724 "Table isn't big enough!"); 725 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 726 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 727 } 728 729 /// setStoreXAction - Indicate that the specified store with truncation does 730 /// not work with the with specified type and indicate what to do about it. 731 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) { 732 assert(VT < 32 && "Table isn't big enough!"); 733 StoreXActions &= ~(uint64_t(3UL) << VT*2); 734 StoreXActions |= (uint64_t)Action << VT*2; 735 } 736 737 /// setIndexedLoadAction - Indicate that the specified indexed load does or 738 /// does not work with the with specified type and indicate what to do abort 739 /// it. NOTE: All indexed mode loads are initialized to Expand in 740 /// TargetLowering.cpp 741 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 742 LegalizeAction Action) { 743 assert(VT < 32 && IdxMode < 744 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) && 745 "Table isn't big enough!"); 746 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 747 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 748 } 749 750 /// setIndexedStoreAction - Indicate that the specified indexed store does or 751 /// does not work with the with specified type and indicate what to do about 752 /// it. NOTE: All indexed mode stores are initialized to Expand in 753 /// TargetLowering.cpp 754 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 755 LegalizeAction Action) { 756 assert(VT < 32 && IdxMode < 757 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) && 758 "Table isn't big enough!"); 759 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 760 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 761 } 762 763 /// setConvertAction - Indicate that the specified conversion does or does 764 /// not work with the with specified type and indicate what to do about it. 765 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT, 766 LegalizeAction Action) { 767 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 && 768 "Table isn't big enough!"); 769 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2); 770 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2; 771 } 772 773 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 774 /// promotion code defaults to trying a larger integer/fp until it can find 775 /// one that works. If that default is insufficient, this method can be used 776 /// by the target to override the default. 777 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 778 MVT::ValueType DestVT) { 779 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 780 } 781 782 /// addLegalFPImmediate - Indicate that this target can instruction select 783 /// the specified FP immediate natively. 784 void addLegalFPImmediate(double Imm) { 785 LegalFPImmediates.push_back(Imm); 786 } 787 788 /// setTargetDAGCombine - Targets should invoke this method for each target 789 /// independent node that they want to provide a custom DAG combiner for by 790 /// implementing the PerformDAGCombine virtual method. 791 void setTargetDAGCombine(ISD::NodeType NT) { 792 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 793 } 794 795 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 796 /// bytes); default is 200 797 void setJumpBufSize(unsigned Size) { 798 JumpBufSize = Size; 799 } 800 801 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 802 /// alignment (in bytes); default is 0 803 void setJumpBufAlignment(unsigned Align) { 804 JumpBufAlignment = Align; 805 } 806 807 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 808 /// limit (in number of instructions); default is 2. 809 void setIfCvtBlockSizeLimit(unsigned Limit) { 810 IfCvtBlockSizeLimit = Limit; 811 } 812 813 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 814 /// of instructions) to be considered for code duplication during 815 /// if-conversion; default is 2. 816 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 817 IfCvtDupBlockSizeLimit = Limit; 818 } 819 820public: 821 822 //===--------------------------------------------------------------------===// 823 // Lowering methods - These methods must be implemented by targets so that 824 // the SelectionDAGLowering code knows how to lower these. 825 // 826 827 /// LowerArguments - This hook must be implemented to indicate how we should 828 /// lower the arguments for the specified function, into the specified DAG. 829 virtual std::vector<SDOperand> 830 LowerArguments(Function &F, SelectionDAG &DAG); 831 832 /// LowerCallTo - This hook lowers an abstract call to a function into an 833 /// actual call. This returns a pair of operands. The first element is the 834 /// return value for the function (if RetTy is not VoidTy). The second 835 /// element is the outgoing token chain. 836 struct ArgListEntry { 837 SDOperand Node; 838 const Type* Ty; 839 bool isSExt; 840 bool isZExt; 841 bool isInReg; 842 bool isSRet; 843 bool isNest; 844 bool isByVal; 845 846 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 847 isSRet(false), isNest(false), isByVal(false) { } 848 }; 849 typedef std::vector<ArgListEntry> ArgListTy; 850 virtual std::pair<SDOperand, SDOperand> 851 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 852 bool isVarArg, unsigned CallingConv, bool isTailCall, 853 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 854 855 /// LowerOperation - This callback is invoked for operations that are 856 /// unsupported by the target, which are registered to use 'custom' lowering, 857 /// and whose defined values are all legal. 858 /// If the target has no operations that require custom lowering, it need not 859 /// implement this. The default implementation of this aborts. 860 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 861 862 /// CustomPromoteOperation - This callback is invoked for operations that are 863 /// unsupported by the target, are registered to use 'custom' lowering, and 864 /// whose type needs to be promoted. 865 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 866 867 /// getTargetNodeName() - This method returns the name of a target specific 868 /// DAG node. 869 virtual const char *getTargetNodeName(unsigned Opcode) const; 870 871 //===--------------------------------------------------------------------===// 872 // Inline Asm Support hooks 873 // 874 875 enum ConstraintType { 876 C_Register, // Constraint represents a single register. 877 C_RegisterClass, // Constraint represents one or more registers. 878 C_Memory, // Memory constraint. 879 C_Other, // Something else. 880 C_Unknown // Unsupported constraint. 881 }; 882 883 /// getConstraintType - Given a constraint, return the type of constraint it 884 /// is for this target. 885 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 886 887 888 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 889 /// return a list of registers that can be used to satisfy the constraint. 890 /// This should only be used for C_RegisterClass constraints. 891 virtual std::vector<unsigned> 892 getRegClassForInlineAsmConstraint(const std::string &Constraint, 893 MVT::ValueType VT) const; 894 895 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 896 /// {edx}), return the register number and the register class for the 897 /// register. 898 /// 899 /// Given a register class constraint, like 'r', if this corresponds directly 900 /// to an LLVM register class, return a register of 0 and the register class 901 /// pointer. 902 /// 903 /// This should only be used for C_Register constraints. On error, 904 /// this returns a register number of 0 and a null register class pointer.. 905 virtual std::pair<unsigned, const TargetRegisterClass*> 906 getRegForInlineAsmConstraint(const std::string &Constraint, 907 MVT::ValueType VT) const; 908 909 910 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 911 /// vector. If it is invalid, don't add anything to Ops. 912 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter, 913 std::vector<SDOperand> &Ops, 914 SelectionDAG &DAG); 915 916 //===--------------------------------------------------------------------===// 917 // Scheduler hooks 918 // 919 920 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 921 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 922 // instructions are special in various ways, which require special support to 923 // insert. The specified MachineInstr is created but not inserted into any 924 // basic blocks, and the scheduler passes ownership of it to this method. 925 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 926 MachineBasicBlock *MBB); 927 928 //===--------------------------------------------------------------------===// 929 // Addressing mode description hooks (used by LSR etc). 930 // 931 932 /// AddrMode - This represents an addressing mode of: 933 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 934 /// If BaseGV is null, there is no BaseGV. 935 /// If BaseOffs is zero, there is no base offset. 936 /// If HasBaseReg is false, there is no base register. 937 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 938 /// no scale. 939 /// 940 struct AddrMode { 941 GlobalValue *BaseGV; 942 int64_t BaseOffs; 943 bool HasBaseReg; 944 int64_t Scale; 945 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 946 }; 947 948 /// isLegalAddressingMode - Return true if the addressing mode represented by 949 /// AM is legal for this target, for a load/store of the specified type. 950 /// TODO: Handle pre/postinc as well. 951 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 952 953 //===--------------------------------------------------------------------===// 954 // Div utility functions 955 // 956 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 957 std::vector<SDNode*>* Created) const; 958 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 959 std::vector<SDNode*>* Created) const; 960 961 962 //===--------------------------------------------------------------------===// 963 // Runtime Library hooks 964 // 965 966 /// setLibcallName - Rename the default libcall routine name for the specified 967 /// libcall. 968 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 969 LibcallRoutineNames[Call] = Name; 970 } 971 972 /// getLibcallName - Get the libcall routine name for the specified libcall. 973 /// 974 const char *getLibcallName(RTLIB::Libcall Call) const { 975 return LibcallRoutineNames[Call]; 976 } 977 978 /// setCmpLibcallCC - Override the default CondCode to be used to test the 979 /// result of the comparison libcall against zero. 980 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 981 CmpLibcallCCs[Call] = CC; 982 } 983 984 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 985 /// the comparison libcall against zero. 986 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 987 return CmpLibcallCCs[Call]; 988 } 989 990private: 991 TargetMachine &TM; 992 const TargetData *TD; 993 994 /// IsLittleEndian - True if this is a little endian target. 995 /// 996 bool IsLittleEndian; 997 998 /// PointerTy - The type to use for pointers, usually i32 or i64. 999 /// 1000 MVT::ValueType PointerTy; 1001 1002 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1003 /// 1004 bool UsesGlobalOffsetTable; 1005 1006 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1007 /// PointerTy is. 1008 MVT::ValueType ShiftAmountTy; 1009 1010 OutOfRangeShiftAmount ShiftAmtHandling; 1011 1012 /// SelectIsExpensive - Tells the code generator not to expand operations 1013 /// into sequences that use the select operations if possible. 1014 bool SelectIsExpensive; 1015 1016 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1017 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1018 /// a real cost model is in place. If we ever optimize for size, this will be 1019 /// set to true unconditionally. 1020 bool IntDivIsCheap; 1021 1022 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1023 /// srl/add/sra for a signed divide by power of two, and let the target handle 1024 /// it. 1025 bool Pow2DivIsCheap; 1026 1027 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 1028 /// PointerTy. 1029 MVT::ValueType SetCCResultTy; 1030 1031 /// SetCCResultContents - Information about the contents of the high-bits in 1032 /// the result of a setcc comparison operation. 1033 SetCCResultValue SetCCResultContents; 1034 1035 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1036 /// total cycles or lowest register usage. 1037 SchedPreference SchedPreferenceInfo; 1038 1039 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1040 /// llvm.setjmp. Defaults to false. 1041 bool UseUnderscoreSetJmp; 1042 1043 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1044 /// llvm.longjmp. Defaults to false. 1045 bool UseUnderscoreLongJmp; 1046 1047 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1048 unsigned JumpBufSize; 1049 1050 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1051 /// buffers 1052 unsigned JumpBufAlignment; 1053 1054 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1055 /// if-converted. 1056 unsigned IfCvtBlockSizeLimit; 1057 1058 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1059 /// duplicated during if-conversion. 1060 unsigned IfCvtDupBlockSizeLimit; 1061 1062 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1063 /// specifies the register that llvm.savestack/llvm.restorestack should save 1064 /// and restore. 1065 unsigned StackPointerRegisterToSaveRestore; 1066 1067 /// ExceptionPointerRegister - If set to a physical register, this specifies 1068 /// the register that receives the exception address on entry to a landing 1069 /// pad. 1070 unsigned ExceptionPointerRegister; 1071 1072 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1073 /// the register that receives the exception typeid on entry to a landing 1074 /// pad. 1075 unsigned ExceptionSelectorRegister; 1076 1077 /// RegClassForVT - This indicates the default register class to use for 1078 /// each ValueType the target supports natively. 1079 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1080 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1081 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1082 1083 /// TransformToType - For any value types we are promoting or expanding, this 1084 /// contains the value type that we are changing to. For Expanded types, this 1085 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1086 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1087 /// by the system, this holds the same type (e.g. i32 -> i32). 1088 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1089 1090 /// OpActions - For each operation and each value type, keep a LegalizeAction 1091 /// that indicates how instruction selection should deal with the operation. 1092 /// Most operations are Legal (aka, supported natively by the target), but 1093 /// operations that are not should be described. Note that operations on 1094 /// non-legal value types are not described here. 1095 uint64_t OpActions[156]; 1096 1097 /// LoadXActions - For each load of load extension type and each value type, 1098 /// keep a LegalizeAction that indicates how instruction selection should deal 1099 /// with the load. 1100 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1101 1102 /// StoreXActions - For each store with truncation of each value type, keep a 1103 /// LegalizeAction that indicates how instruction selection should deal with 1104 /// the store. 1105 uint64_t StoreXActions; 1106 1107 /// IndexedModeActions - For each indexed mode and each value type, keep a 1108 /// pair of LegalizeAction that indicates how instruction selection should 1109 /// deal with the load / store. 1110 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1111 1112 /// ConvertActions - For each conversion from source type to destination type, 1113 /// keep a LegalizeAction that indicates how instruction selection should 1114 /// deal with the conversion. 1115 /// Currently, this is used only for floating->floating conversions 1116 /// (FP_EXTEND and FP_ROUND). 1117 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1118 1119 ValueTypeActionImpl ValueTypeActions; 1120 1121 std::vector<double> LegalFPImmediates; 1122 1123 std::vector<std::pair<MVT::ValueType, 1124 TargetRegisterClass*> > AvailableRegClasses; 1125 1126 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1127 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1128 /// which sets a bit in this array. 1129 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1130 1131 /// PromoteToType - For operations that must be promoted to a specific type, 1132 /// this holds the destination type. This map should be sparse, so don't hold 1133 /// it as an array. 1134 /// 1135 /// Targets add entries to this map with AddPromotedToType(..), clients access 1136 /// this with getTypeToPromoteTo(..). 1137 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1138 1139 /// LibcallRoutineNames - Stores the name each libcall. 1140 /// 1141 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1142 1143 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1144 /// of each of the comparison libcall against zero. 1145 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1146 1147protected: 1148 /// When lowering %llvm.memset this field specifies the maximum number of 1149 /// store operations that may be substituted for the call to memset. Targets 1150 /// must set this value based on the cost threshold for that target. Targets 1151 /// should assume that the memset will be done using as many of the largest 1152 /// store operations first, followed by smaller ones, if necessary, per 1153 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1154 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1155 /// store. This only applies to setting a constant array of a constant size. 1156 /// @brief Specify maximum number of store instructions per memset call. 1157 unsigned maxStoresPerMemset; 1158 1159 /// When lowering %llvm.memcpy this field specifies the maximum number of 1160 /// store operations that may be substituted for a call to memcpy. Targets 1161 /// must set this value based on the cost threshold for that target. Targets 1162 /// should assume that the memcpy will be done using as many of the largest 1163 /// store operations first, followed by smaller ones, if necessary, per 1164 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1165 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1166 /// and one 1-byte store. This only applies to copying a constant array of 1167 /// constant size. 1168 /// @brief Specify maximum bytes of store instructions per memcpy call. 1169 unsigned maxStoresPerMemcpy; 1170 1171 /// When lowering %llvm.memmove this field specifies the maximum number of 1172 /// store instructions that may be substituted for a call to memmove. Targets 1173 /// must set this value based on the cost threshold for that target. Targets 1174 /// should assume that the memmove will be done using as many of the largest 1175 /// store operations first, followed by smaller ones, if necessary, per 1176 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1177 /// with 8-bit alignment would result in nine 1-byte stores. This only 1178 /// applies to copying a constant array of constant size. 1179 /// @brief Specify maximum bytes of store instructions per memmove call. 1180 unsigned maxStoresPerMemmove; 1181 1182 /// This field specifies whether the target machine permits unaligned memory 1183 /// accesses. This is used, for example, to determine the size of store 1184 /// operations when copying small arrays and other similar tasks. 1185 /// @brief Indicate whether the target permits unaligned memory accesses. 1186 bool allowUnalignedMemoryAccesses; 1187}; 1188} // end llvm namespace 1189 1190#endif 1191