TargetLowering.h revision 83489bb7700c69b7a4a8da59365c42d3f5c8129b
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/InlineAsm.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/ADT/APFloat.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallSet.h" 31#include "llvm/ADT/STLExtras.h" 32#include <climits> 33#include <map> 34#include <vector> 35 36namespace llvm { 37 class AllocaInst; 38 class CallInst; 39 class Function; 40 class FastISel; 41 class MachineBasicBlock; 42 class MachineFunction; 43 class MachineFrameInfo; 44 class MachineInstr; 45 class MachineModuleInfo; 46 class DwarfWriter; 47 class SDNode; 48 class SDValue; 49 class SelectionDAG; 50 class TargetData; 51 class TargetMachine; 52 class TargetRegisterClass; 53 class TargetSubtarget; 54 class Value; 55 56//===----------------------------------------------------------------------===// 57/// TargetLowering - This class defines information used to lower LLVM code to 58/// legal SelectionDAG operators that the target instruction selector can accept 59/// natively. 60/// 61/// This class also defines callbacks that targets must implement to lower 62/// target-specific constructs to SelectionDAG operators. 63/// 64class TargetLowering { 65public: 66 /// LegalizeAction - This enum indicates whether operations are valid for a 67 /// target, and if not, what action should be used to make them valid. 68 enum LegalizeAction { 69 Legal, // The target natively supports this operation. 70 Promote, // This operation should be executed in a larger type. 71 Expand, // Try to expand this to other ops, otherwise use a libcall. 72 Custom // Use the LowerOperation hook to implement custom lowering. 73 }; 74 75 enum OutOfRangeShiftAmount { 76 Undefined, // Oversized shift amounts are undefined (default). 77 Mask, // Shift amounts are auto masked (anded) to value size. 78 Extend // Oversized shift pulls in zeros or sign bits. 79 }; 80 81 enum BooleanContent { // How the target represents true/false values. 82 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 83 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 84 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 85 }; 86 87 enum SchedPreference { 88 SchedulingForLatency, // Scheduling for shortest total latency. 89 SchedulingForRegPressure // Scheduling for lowest register pressure. 90 }; 91 92 explicit TargetLowering(TargetMachine &TM); 93 virtual ~TargetLowering(); 94 95 TargetMachine &getTargetMachine() const { return TM; } 96 const TargetData *getTargetData() const { return TD; } 97 98 bool isBigEndian() const { return !IsLittleEndian; } 99 bool isLittleEndian() const { return IsLittleEndian; } 100 MVT getPointerTy() const { return PointerTy; } 101 MVT getShiftAmountTy() const { return ShiftAmountTy; } 102 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 103 104 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 105 /// codegen. 106 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 107 108 /// isSelectExpensive - Return true if the select operation is expensive for 109 /// this target. 110 bool isSelectExpensive() const { return SelectIsExpensive; } 111 112 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 113 /// a sequence of several shifts, adds, and multiplies for this target. 114 bool isIntDivCheap() const { return IntDivIsCheap; } 115 116 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 117 /// srl/add/sra. 118 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 119 120 /// getSetCCResultType - Return the ValueType of the result of SETCC 121 /// operations. Also used to obtain the target's preferred type for 122 /// the condition operand of SELECT and BRCOND nodes. In the case of 123 /// BRCOND the argument passed is MVT::Other since there are no other 124 /// operands to get a type hint from. 125 virtual MVT getSetCCResultType(MVT VT) const; 126 127 /// getBooleanContents - For targets without i1 registers, this gives the 128 /// nature of the high-bits of boolean values held in types wider than i1. 129 /// "Boolean values" are special true/false values produced by nodes like 130 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 131 /// Not to be confused with general values promoted from i1. 132 BooleanContent getBooleanContents() const { return BooleanContents;} 133 134 /// getSchedulingPreference - Return target scheduling preference. 135 SchedPreference getSchedulingPreference() const { 136 return SchedPreferenceInfo; 137 } 138 139 /// getRegClassFor - Return the register class that should be used for the 140 /// specified value type. This may only be called on legal types. 141 TargetRegisterClass *getRegClassFor(MVT VT) const { 142 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 143 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; 144 assert(RC && "This value type is not natively supported!"); 145 return RC; 146 } 147 148 /// isTypeLegal - Return true if the target has native support for the 149 /// specified value type. This means that it has a register that directly 150 /// holds it without promotions or expansions. 151 bool isTypeLegal(MVT VT) const { 152 assert(!VT.isSimple() || 153 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 154 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; 155 } 156 157 class ValueTypeActionImpl { 158 /// ValueTypeActions - This is a bitvector that contains two bits for each 159 /// value type, where the two bits correspond to the LegalizeAction enum. 160 /// This can be queried with "getTypeAction(VT)". 161 uint32_t ValueTypeActions[2]; 162 public: 163 ValueTypeActionImpl() { 164 ValueTypeActions[0] = ValueTypeActions[1] = 0; 165 } 166 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 167 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 168 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 169 } 170 171 LegalizeAction getTypeAction(MVT VT) const { 172 if (VT.isExtended()) { 173 if (VT.isVector()) { 174 return VT.isPow2VectorType() ? Expand : Promote; 175 } 176 if (VT.isInteger()) 177 // First promote to a power-of-two size, then expand if necessary. 178 return VT == VT.getRoundIntegerType() ? Expand : Promote; 179 assert(0 && "Unsupported extended type!"); 180 return Legal; 181 } 182 unsigned I = VT.getSimpleVT(); 183 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 184 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 185 } 186 void setTypeAction(MVT VT, LegalizeAction Action) { 187 unsigned I = VT.getSimpleVT(); 188 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 189 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 190 } 191 }; 192 193 const ValueTypeActionImpl &getValueTypeActions() const { 194 return ValueTypeActions; 195 } 196 197 /// getTypeAction - Return how we should legalize values of this type, either 198 /// it is already legal (return 'Legal') or we need to promote it to a larger 199 /// type (return 'Promote'), or we need to expand it into multiple registers 200 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 201 LegalizeAction getTypeAction(MVT VT) const { 202 return ValueTypeActions.getTypeAction(VT); 203 } 204 205 /// getTypeToTransformTo - For types supported by the target, this is an 206 /// identity function. For types that must be promoted to larger types, this 207 /// returns the larger type to promote to. For integer types that are larger 208 /// than the largest integer register, this contains one step in the expansion 209 /// to get to the smaller register. For illegal floating point types, this 210 /// returns the integer type to transform to. 211 MVT getTypeToTransformTo(MVT VT) const { 212 if (VT.isSimple()) { 213 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); 214 MVT NVT = TransformToType[VT.getSimpleVT()]; 215 assert(getTypeAction(NVT) != Promote && 216 "Promote may not follow Expand or Promote"); 217 return NVT; 218 } 219 220 if (VT.isVector()) { 221 MVT NVT = VT.getPow2VectorType(); 222 if (NVT == VT) { 223 // Vector length is a power of 2 - split to half the size. 224 unsigned NumElts = VT.getVectorNumElements(); 225 MVT EltVT = VT.getVectorElementType(); 226 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2); 227 } 228 // Promote to a power of two size, avoiding multi-step promotion. 229 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 230 } else if (VT.isInteger()) { 231 MVT NVT = VT.getRoundIntegerType(); 232 if (NVT == VT) 233 // Size is a power of two - expand to half the size. 234 return MVT::getIntegerVT(VT.getSizeInBits() / 2); 235 else 236 // Promote to a power of two size, avoiding multi-step promotion. 237 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 238 } 239 assert(0 && "Unsupported extended type!"); 240 return MVT(); // Not reached 241 } 242 243 /// getTypeToExpandTo - For types supported by the target, this is an 244 /// identity function. For types that must be expanded (i.e. integer types 245 /// that are larger than the largest integer register or illegal floating 246 /// point types), this returns the largest legal type it will be expanded to. 247 MVT getTypeToExpandTo(MVT VT) const { 248 assert(!VT.isVector()); 249 while (true) { 250 switch (getTypeAction(VT)) { 251 case Legal: 252 return VT; 253 case Expand: 254 VT = getTypeToTransformTo(VT); 255 break; 256 default: 257 assert(false && "Type is not legal nor is it to be expanded!"); 258 return VT; 259 } 260 } 261 return VT; 262 } 263 264 /// getVectorTypeBreakdown - Vector types are broken down into some number of 265 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 266 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 267 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 268 /// 269 /// This method returns the number of registers needed, and the VT for each 270 /// register. It also returns the VT and quantity of the intermediate values 271 /// before they are promoted/expanded. 272 /// 273 unsigned getVectorTypeBreakdown(MVT VT, 274 MVT &IntermediateVT, 275 unsigned &NumIntermediates, 276 MVT &RegisterVT) const; 277 278 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 279 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 280 /// this is the case, it returns true and store the intrinsic 281 /// information into the IntrinsicInfo that was passed to the function. 282 typedef struct IntrinsicInfo { 283 unsigned opc; // target opcode 284 MVT memVT; // memory VT 285 const Value* ptrVal; // value representing memory location 286 int offset; // offset off of ptrVal 287 unsigned align; // alignment 288 bool vol; // is volatile? 289 bool readMem; // reads memory? 290 bool writeMem; // writes memory? 291 } IntrinisicInfo; 292 293 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 294 CallInst &I, unsigned Intrinsic) { 295 return false; 296 } 297 298 /// getWidenVectorType: given a vector type, returns the type to widen to 299 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 300 /// If there is no vector type that we want to widen to, returns MVT::Other 301 /// When and were to widen is target dependent based on the cost of 302 /// scalarizing vs using the wider vector type. 303 virtual MVT getWidenVectorType(MVT VT); 304 305 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 306 legal_fpimm_iterator legal_fpimm_begin() const { 307 return LegalFPImmediates.begin(); 308 } 309 legal_fpimm_iterator legal_fpimm_end() const { 310 return LegalFPImmediates.end(); 311 } 312 313 /// isShuffleMaskLegal - Targets can use this to indicate that they only 314 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 315 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 316 /// are assumed to be legal. 317 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const { 318 return true; 319 } 320 321 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 322 /// used by Targets can use this to indicate if there is a suitable 323 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 324 /// pool entry. 325 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, 326 MVT EVT, 327 SelectionDAG &DAG) const { 328 return false; 329 } 330 331 /// getOperationAction - Return how this operation should be treated: either 332 /// it is legal, needs to be promoted to a larger size, needs to be 333 /// expanded to some other code sequence, or the target has a custom expander 334 /// for it. 335 LegalizeAction getOperationAction(unsigned Op, MVT VT) const { 336 if (VT.isExtended()) return Expand; 337 assert(Op < array_lengthof(OpActions) && 338 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 339 "Table isn't big enough!"); 340 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); 341 } 342 343 /// isOperationLegal - Return true if the specified operation is legal on this 344 /// target. 345 bool isOperationLegal(unsigned Op, MVT VT) const { 346 return (VT == MVT::Other || isTypeLegal(VT)) && 347 (getOperationAction(Op, VT) == Legal || 348 getOperationAction(Op, VT) == Custom); 349 } 350 351 /// getLoadExtAction - Return how this load with extension should be treated: 352 /// either it is legal, needs to be promoted to a larger size, needs to be 353 /// expanded to some other code sequence, or the target has a custom expander 354 /// for it. 355 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const { 356 assert(LType < array_lengthof(LoadExtActions) && 357 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 358 "Table isn't big enough!"); 359 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3); 360 } 361 362 /// isLoadExtLegal - Return true if the specified load with extension is legal 363 /// on this target. 364 bool isLoadExtLegal(unsigned LType, MVT VT) const { 365 return VT.isSimple() && 366 (getLoadExtAction(LType, VT) == Legal || 367 getLoadExtAction(LType, VT) == Custom); 368 } 369 370 /// getTruncStoreAction - Return how this store with truncation should be 371 /// treated: either it is legal, needs to be promoted to a larger size, needs 372 /// to be expanded to some other code sequence, or the target has a custom 373 /// expander for it. 374 LegalizeAction getTruncStoreAction(MVT ValVT, 375 MVT MemVT) const { 376 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 377 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 378 "Table isn't big enough!"); 379 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> 380 (2*MemVT.getSimpleVT())) & 3); 381 } 382 383 /// isTruncStoreLegal - Return true if the specified store with truncation is 384 /// legal on this target. 385 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { 386 return isTypeLegal(ValVT) && MemVT.isSimple() && 387 (getTruncStoreAction(ValVT, MemVT) == Legal || 388 getTruncStoreAction(ValVT, MemVT) == Custom); 389 } 390 391 /// getIndexedLoadAction - Return how the indexed load should be treated: 392 /// either it is legal, needs to be promoted to a larger size, needs to be 393 /// expanded to some other code sequence, or the target has a custom expander 394 /// for it. 395 LegalizeAction 396 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 397 assert(IdxMode < array_lengthof(IndexedModeActions[0]) && 398 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 && 399 "Table isn't big enough!"); 400 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> 401 (2*VT.getSimpleVT())) & 3); 402 } 403 404 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 405 /// on this target. 406 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { 407 return VT.isSimple() && 408 (getIndexedLoadAction(IdxMode, VT) == Legal || 409 getIndexedLoadAction(IdxMode, VT) == Custom); 410 } 411 412 /// getIndexedStoreAction - Return how the indexed store should be treated: 413 /// either it is legal, needs to be promoted to a larger size, needs to be 414 /// expanded to some other code sequence, or the target has a custom expander 415 /// for it. 416 LegalizeAction 417 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 418 assert(IdxMode < array_lengthof(IndexedModeActions[1]) && 419 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 420 "Table isn't big enough!"); 421 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> 422 (2*VT.getSimpleVT())) & 3); 423 } 424 425 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 426 /// on this target. 427 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { 428 return VT.isSimple() && 429 (getIndexedStoreAction(IdxMode, VT) == Legal || 430 getIndexedStoreAction(IdxMode, VT) == Custom); 431 } 432 433 /// getConvertAction - Return how the conversion should be treated: 434 /// either it is legal, needs to be promoted to a larger size, needs to be 435 /// expanded to some other code sequence, or the target has a custom expander 436 /// for it. 437 LegalizeAction 438 getConvertAction(MVT FromVT, MVT ToVT) const { 439 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 440 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 441 "Table isn't big enough!"); 442 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> 443 (2*ToVT.getSimpleVT())) & 3); 444 } 445 446 /// isConvertLegal - Return true if the specified conversion is legal 447 /// on this target. 448 bool isConvertLegal(MVT FromVT, MVT ToVT) const { 449 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 450 (getConvertAction(FromVT, ToVT) == Legal || 451 getConvertAction(FromVT, ToVT) == Custom); 452 } 453 454 /// getCondCodeAction - Return how the condition code should be treated: 455 /// either it is legal, needs to be expanded to some other code sequence, 456 /// or the target has a custom expander for it. 457 LegalizeAction 458 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 459 assert((unsigned)CC < array_lengthof(CondCodeActions) && 460 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 461 "Table isn't big enough!"); 462 LegalizeAction Action = (LegalizeAction) 463 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3); 464 assert(Action != Promote && "Can't promote condition code!"); 465 return Action; 466 } 467 468 /// isCondCodeLegal - Return true if the specified condition code is legal 469 /// on this target. 470 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 471 return getCondCodeAction(CC, VT) == Legal || 472 getCondCodeAction(CC, VT) == Custom; 473 } 474 475 476 /// getTypeToPromoteTo - If the action for this operation is to promote, this 477 /// method returns the ValueType to promote to. 478 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 479 assert(getOperationAction(Op, VT) == Promote && 480 "This operation isn't promoted!"); 481 482 // See if this has an explicit type specified. 483 std::map<std::pair<unsigned, MVT::SimpleValueType>, 484 MVT::SimpleValueType>::const_iterator PTTI = 485 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); 486 if (PTTI != PromoteToType.end()) return PTTI->second; 487 488 assert((VT.isInteger() || VT.isFloatingPoint()) && 489 "Cannot autopromote this type, add it with AddPromotedToType."); 490 491 MVT NVT = VT; 492 do { 493 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); 494 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 495 "Didn't find type to promote to!"); 496 } while (!isTypeLegal(NVT) || 497 getOperationAction(Op, NVT) == Promote); 498 return NVT; 499 } 500 501 /// getValueType - Return the MVT corresponding to this LLVM type. 502 /// This is fixed by the LLVM operations except for the pointer size. If 503 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 504 /// counterpart (e.g. structs), otherwise it will assert. 505 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 506 MVT VT = MVT::getMVT(Ty, AllowUnknown); 507 return VT == MVT::iPTR ? PointerTy : VT; 508 } 509 510 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 511 /// function arguments in the caller parameter area. This is the actual 512 /// alignment, not its logarithm. 513 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 514 515 /// getRegisterType - Return the type of registers that this ValueType will 516 /// eventually require. 517 MVT getRegisterType(MVT VT) const { 518 if (VT.isSimple()) { 519 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); 520 return RegisterTypeForVT[VT.getSimpleVT()]; 521 } 522 if (VT.isVector()) { 523 MVT VT1, RegisterVT; 524 unsigned NumIntermediates; 525 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 526 return RegisterVT; 527 } 528 if (VT.isInteger()) { 529 return getRegisterType(getTypeToTransformTo(VT)); 530 } 531 assert(0 && "Unsupported extended type!"); 532 return MVT(); // Not reached 533 } 534 535 /// getNumRegisters - Return the number of registers that this ValueType will 536 /// eventually require. This is one for any types promoted to live in larger 537 /// registers, but may be more than one for types (like i64) that are split 538 /// into pieces. For types like i140, which are first promoted then expanded, 539 /// it is the number of registers needed to hold all the bits of the original 540 /// type. For an i140 on a 32 bit machine this means 5 registers. 541 unsigned getNumRegisters(MVT VT) const { 542 if (VT.isSimple()) { 543 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); 544 return NumRegistersForVT[VT.getSimpleVT()]; 545 } 546 if (VT.isVector()) { 547 MVT VT1, VT2; 548 unsigned NumIntermediates; 549 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 550 } 551 if (VT.isInteger()) { 552 unsigned BitWidth = VT.getSizeInBits(); 553 unsigned RegWidth = getRegisterType(VT).getSizeInBits(); 554 return (BitWidth + RegWidth - 1) / RegWidth; 555 } 556 assert(0 && "Unsupported extended type!"); 557 return 0; // Not reached 558 } 559 560 /// ShouldShrinkFPConstant - If true, then instruction selection should 561 /// seek to shrink the FP constant of the specified type to a smaller type 562 /// in order to save space and / or reduce runtime. 563 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } 564 565 /// hasTargetDAGCombine - If true, the target has custom DAG combine 566 /// transformations that it can perform for the specified node. 567 bool hasTargetDAGCombine(ISD::NodeType NT) const { 568 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 569 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 570 } 571 572 /// This function returns the maximum number of store operations permitted 573 /// to replace a call to llvm.memset. The value is set by the target at the 574 /// performance threshold for such a replacement. 575 /// @brief Get maximum # of store operations permitted for llvm.memset 576 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 577 578 /// This function returns the maximum number of store operations permitted 579 /// to replace a call to llvm.memcpy. The value is set by the target at the 580 /// performance threshold for such a replacement. 581 /// @brief Get maximum # of store operations permitted for llvm.memcpy 582 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 583 584 /// This function returns the maximum number of store operations permitted 585 /// to replace a call to llvm.memmove. The value is set by the target at the 586 /// performance threshold for such a replacement. 587 /// @brief Get maximum # of store operations permitted for llvm.memmove 588 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 589 590 /// This function returns true if the target allows unaligned memory accesses. 591 /// This is used, for example, in situations where an array copy/move/set is 592 /// converted to a sequence of store operations. It's use helps to ensure that 593 /// such replacements don't generate code that causes an alignment error 594 /// (trap) on the target machine. 595 /// @brief Determine if the target supports unaligned memory accesses. 596 bool allowsUnalignedMemoryAccesses() const { 597 return allowUnalignedMemoryAccesses; 598 } 599 600 /// getOptimalMemOpType - Returns the target specific optimal type for load 601 /// and store operations as a result of memset, memcpy, and memmove lowering. 602 /// It returns MVT::iAny if SelectionDAG should be responsible for 603 /// determining it. 604 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, 605 bool isSrcConst, bool isSrcStr) const { 606 return MVT::iAny; 607 } 608 609 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 610 /// to implement llvm.setjmp. 611 bool usesUnderscoreSetJmp() const { 612 return UseUnderscoreSetJmp; 613 } 614 615 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 616 /// to implement llvm.longjmp. 617 bool usesUnderscoreLongJmp() const { 618 return UseUnderscoreLongJmp; 619 } 620 621 /// getStackPointerRegisterToSaveRestore - If a physical register, this 622 /// specifies the register that llvm.savestack/llvm.restorestack should save 623 /// and restore. 624 unsigned getStackPointerRegisterToSaveRestore() const { 625 return StackPointerRegisterToSaveRestore; 626 } 627 628 /// getExceptionAddressRegister - If a physical register, this returns 629 /// the register that receives the exception address on entry to a landing 630 /// pad. 631 unsigned getExceptionAddressRegister() const { 632 return ExceptionPointerRegister; 633 } 634 635 /// getExceptionSelectorRegister - If a physical register, this returns 636 /// the register that receives the exception typeid on entry to a landing 637 /// pad. 638 unsigned getExceptionSelectorRegister() const { 639 return ExceptionSelectorRegister; 640 } 641 642 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 643 /// set, the default is 200) 644 unsigned getJumpBufSize() const { 645 return JumpBufSize; 646 } 647 648 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 649 /// (if never set, the default is 0) 650 unsigned getJumpBufAlignment() const { 651 return JumpBufAlignment; 652 } 653 654 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 655 /// limit. Any block whose size is greater should not be predicated. 656 unsigned getIfCvtBlockSizeLimit() const { 657 return IfCvtBlockSizeLimit; 658 } 659 660 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 661 /// block to be considered for duplication. Any block whose size is greater 662 /// should not be duplicated to facilitate its predication. 663 unsigned getIfCvtDupBlockSizeLimit() const { 664 return IfCvtDupBlockSizeLimit; 665 } 666 667 /// getPrefLoopAlignment - return the preferred loop alignment. 668 /// 669 unsigned getPrefLoopAlignment() const { 670 return PrefLoopAlignment; 671 } 672 673 /// getPreIndexedAddressParts - returns true by value, base pointer and 674 /// offset pointer and addressing mode by reference if the node's address 675 /// can be legally represented as pre-indexed load / store address. 676 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 677 SDValue &Offset, 678 ISD::MemIndexedMode &AM, 679 SelectionDAG &DAG) { 680 return false; 681 } 682 683 /// getPostIndexedAddressParts - returns true by value, base pointer and 684 /// offset pointer and addressing mode by reference if this node can be 685 /// combined with a load / store to form a post-indexed load / store. 686 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 687 SDValue &Base, SDValue &Offset, 688 ISD::MemIndexedMode &AM, 689 SelectionDAG &DAG) { 690 return false; 691 } 692 693 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 694 /// jumptable. 695 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 696 SelectionDAG &DAG) const; 697 698 /// isOffsetFoldingLegal - Return true if folding a constant offset 699 /// with the given GlobalAddress is legal. It is frequently not legal in 700 /// PIC relocation models. 701 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 702 703 //===--------------------------------------------------------------------===// 704 // TargetLowering Optimization Methods 705 // 706 707 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 708 /// SDValues for returning information from TargetLowering to its clients 709 /// that want to combine 710 struct TargetLoweringOpt { 711 SelectionDAG &DAG; 712 SDValue Old; 713 SDValue New; 714 715 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 716 717 bool CombineTo(SDValue O, SDValue N) { 718 Old = O; 719 New = N; 720 return true; 721 } 722 723 /// ShrinkDemandedConstant - Check to see if the specified operand of the 724 /// specified instruction is a constant integer. If so, check to see if 725 /// there are any bits set in the constant that are not demanded. If so, 726 /// shrink the constant and return true. 727 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 728 }; 729 730 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 731 /// DemandedMask bits of the result of Op are ever used downstream. If we can 732 /// use this information to simplify Op, create a new simplified DAG node and 733 /// return true, returning the original and new nodes in Old and New. 734 /// Otherwise, analyze the expression and return a mask of KnownOne and 735 /// KnownZero bits for the expression (used to simplify the caller). 736 /// The KnownZero/One bits may only be accurate for those bits in the 737 /// DemandedMask. 738 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 739 APInt &KnownZero, APInt &KnownOne, 740 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 741 742 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 743 /// Mask are known to be either zero or one and return them in the 744 /// KnownZero/KnownOne bitsets. 745 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 746 const APInt &Mask, 747 APInt &KnownZero, 748 APInt &KnownOne, 749 const SelectionDAG &DAG, 750 unsigned Depth = 0) const; 751 752 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 753 /// targets that want to expose additional information about sign bits to the 754 /// DAG Combiner. 755 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 756 unsigned Depth = 0) const; 757 758 struct DAGCombinerInfo { 759 void *DC; // The DAG Combiner object. 760 bool BeforeLegalize; 761 bool CalledByLegalizer; 762 public: 763 SelectionDAG &DAG; 764 765 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 766 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 767 768 bool isBeforeLegalize() const { return BeforeLegalize; } 769 bool isCalledByLegalizer() const { return CalledByLegalizer; } 770 771 void AddToWorklist(SDNode *N); 772 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To); 773 SDValue CombineTo(SDNode *N, SDValue Res); 774 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1); 775 }; 776 777 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 778 /// and cc. If it is unable to simplify it, return a null SDValue. 779 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 780 ISD::CondCode Cond, bool foldBooleans, 781 DAGCombinerInfo &DCI) const; 782 783 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 784 /// node is a GlobalAddress + offset. 785 virtual bool 786 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 787 788 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 789 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the 790 /// location that the 'Base' load is loading from. 791 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist, 792 const MachineFrameInfo *MFI) const; 793 794 /// PerformDAGCombine - This method will be invoked for all target nodes and 795 /// for any target-independent nodes that the target has registered with 796 /// invoke it for. 797 /// 798 /// The semantics are as follows: 799 /// Return Value: 800 /// SDValue.Val == 0 - No change was made 801 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 802 /// otherwise - N should be replaced by the returned Operand. 803 /// 804 /// In addition, methods provided by DAGCombinerInfo may be used to perform 805 /// more complex transformations. 806 /// 807 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 808 809 //===--------------------------------------------------------------------===// 810 // TargetLowering Configuration Methods - These methods should be invoked by 811 // the derived class constructor to configure this object for the target. 812 // 813 814protected: 815 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 816 /// GOT for PC-relative code. 817 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 818 819 /// setShiftAmountType - Describe the type that should be used for shift 820 /// amounts. This type defaults to the pointer type. 821 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 822 823 /// setBooleanContents - Specify how the target extends the result of a 824 /// boolean value from i1 to a wider type. See getBooleanContents. 825 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 826 827 /// setSchedulingPreference - Specify the target scheduling preference. 828 void setSchedulingPreference(SchedPreference Pref) { 829 SchedPreferenceInfo = Pref; 830 } 831 832 /// setShiftAmountFlavor - Describe how the target handles out of range shift 833 /// amounts. 834 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 835 ShiftAmtHandling = OORSA; 836 } 837 838 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 839 /// use _setjmp to implement llvm.setjmp or the non _ version. 840 /// Defaults to false. 841 void setUseUnderscoreSetJmp(bool Val) { 842 UseUnderscoreSetJmp = Val; 843 } 844 845 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 846 /// use _longjmp to implement llvm.longjmp or the non _ version. 847 /// Defaults to false. 848 void setUseUnderscoreLongJmp(bool Val) { 849 UseUnderscoreLongJmp = Val; 850 } 851 852 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 853 /// specifies the register that llvm.savestack/llvm.restorestack should save 854 /// and restore. 855 void setStackPointerRegisterToSaveRestore(unsigned R) { 856 StackPointerRegisterToSaveRestore = R; 857 } 858 859 /// setExceptionPointerRegister - If set to a physical register, this sets 860 /// the register that receives the exception address on entry to a landing 861 /// pad. 862 void setExceptionPointerRegister(unsigned R) { 863 ExceptionPointerRegister = R; 864 } 865 866 /// setExceptionSelectorRegister - If set to a physical register, this sets 867 /// the register that receives the exception typeid on entry to a landing 868 /// pad. 869 void setExceptionSelectorRegister(unsigned R) { 870 ExceptionSelectorRegister = R; 871 } 872 873 /// SelectIsExpensive - Tells the code generator not to expand operations 874 /// into sequences that use the select operations if possible. 875 void setSelectIsExpensive() { SelectIsExpensive = true; } 876 877 /// setIntDivIsCheap - Tells the code generator that integer divide is 878 /// expensive, and if possible, should be replaced by an alternate sequence 879 /// of instructions not containing an integer divide. 880 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 881 882 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 883 /// srl/add/sra for a signed divide by power of two, and let the target handle 884 /// it. 885 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 886 887 /// addRegisterClass - Add the specified register class as an available 888 /// regclass for the specified value type. This indicates the selector can 889 /// handle values of that class natively. 890 void addRegisterClass(MVT VT, TargetRegisterClass *RC) { 891 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 892 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 893 RegClassForVT[VT.getSimpleVT()] = RC; 894 } 895 896 /// computeRegisterProperties - Once all of the register classes are added, 897 /// this allows us to compute derived properties we expose. 898 void computeRegisterProperties(); 899 900 /// setOperationAction - Indicate that the specified operation does not work 901 /// with the specified type and indicate what to do about it. 902 void setOperationAction(unsigned Op, MVT VT, 903 LegalizeAction Action) { 904 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 905 Op < array_lengthof(OpActions) && "Table isn't big enough!"); 906 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 907 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2; 908 } 909 910 /// setLoadExtAction - Indicate that the specified load with extension does 911 /// not work with the with specified type and indicate what to do about it. 912 void setLoadExtAction(unsigned ExtType, MVT VT, 913 LegalizeAction Action) { 914 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 915 ExtType < array_lengthof(LoadExtActions) && 916 "Table isn't big enough!"); 917 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 918 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2; 919 } 920 921 /// setTruncStoreAction - Indicate that the specified truncating store does 922 /// not work with the with specified type and indicate what to do about it. 923 void setTruncStoreAction(MVT ValVT, MVT MemVT, 924 LegalizeAction Action) { 925 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 926 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 927 "Table isn't big enough!"); 928 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) << 929 MemVT.getSimpleVT()*2); 930 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action << 931 MemVT.getSimpleVT()*2; 932 } 933 934 /// setIndexedLoadAction - Indicate that the specified indexed load does or 935 /// does not work with the with specified type and indicate what to do abort 936 /// it. NOTE: All indexed mode loads are initialized to Expand in 937 /// TargetLowering.cpp 938 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 939 LegalizeAction Action) { 940 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 && 941 IdxMode < array_lengthof(IndexedModeActions[0]) && 942 "Table isn't big enough!"); 943 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 944 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 945 } 946 947 /// setIndexedStoreAction - Indicate that the specified indexed store does or 948 /// does not work with the with specified type and indicate what to do about 949 /// it. NOTE: All indexed mode stores are initialized to Expand in 950 /// TargetLowering.cpp 951 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 952 LegalizeAction Action) { 953 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 954 IdxMode < array_lengthof(IndexedModeActions[1]) && 955 "Table isn't big enough!"); 956 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 957 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 958 } 959 960 /// setConvertAction - Indicate that the specified conversion does or does 961 /// not work with the with specified type and indicate what to do about it. 962 void setConvertAction(MVT FromVT, MVT ToVT, 963 LegalizeAction Action) { 964 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 965 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 966 "Table isn't big enough!"); 967 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) << 968 ToVT.getSimpleVT()*2); 969 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action << 970 ToVT.getSimpleVT()*2; 971 } 972 973 /// setCondCodeAction - Indicate that the specified condition code is or isn't 974 /// supported on the target and indicate what to do about it. 975 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { 976 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 977 (unsigned)CC < array_lengthof(CondCodeActions) && 978 "Table isn't big enough!"); 979 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 980 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2; 981 } 982 983 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 984 /// promotion code defaults to trying a larger integer/fp until it can find 985 /// one that works. If that default is insufficient, this method can be used 986 /// by the target to override the default. 987 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 988 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] = 989 DestVT.getSimpleVT(); 990 } 991 992 /// addLegalFPImmediate - Indicate that this target can instruction select 993 /// the specified FP immediate natively. 994 void addLegalFPImmediate(const APFloat& Imm) { 995 LegalFPImmediates.push_back(Imm); 996 } 997 998 /// setTargetDAGCombine - Targets should invoke this method for each target 999 /// independent node that they want to provide a custom DAG combiner for by 1000 /// implementing the PerformDAGCombine virtual method. 1001 void setTargetDAGCombine(ISD::NodeType NT) { 1002 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1003 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1004 } 1005 1006 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1007 /// bytes); default is 200 1008 void setJumpBufSize(unsigned Size) { 1009 JumpBufSize = Size; 1010 } 1011 1012 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1013 /// alignment (in bytes); default is 0 1014 void setJumpBufAlignment(unsigned Align) { 1015 JumpBufAlignment = Align; 1016 } 1017 1018 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1019 /// limit (in number of instructions); default is 2. 1020 void setIfCvtBlockSizeLimit(unsigned Limit) { 1021 IfCvtBlockSizeLimit = Limit; 1022 } 1023 1024 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1025 /// of instructions) to be considered for code duplication during 1026 /// if-conversion; default is 2. 1027 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1028 IfCvtDupBlockSizeLimit = Limit; 1029 } 1030 1031 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1032 /// alignment is zero, it means the target does not care about loop alignment. 1033 void setPrefLoopAlignment(unsigned Align) { 1034 PrefLoopAlignment = Align; 1035 } 1036 1037public: 1038 1039 virtual const TargetSubtarget *getSubtarget() { 1040 assert(0 && "Not Implemented"); 1041 return NULL; // this is here to silence compiler errors 1042 } 1043 //===--------------------------------------------------------------------===// 1044 // Lowering methods - These methods must be implemented by targets so that 1045 // the SelectionDAGLowering code knows how to lower these. 1046 // 1047 1048 /// LowerArguments - This hook must be implemented to indicate how we should 1049 /// lower the arguments for the specified function, into the specified DAG. 1050 virtual void 1051 LowerArguments(Function &F, SelectionDAG &DAG, 1052 SmallVectorImpl<SDValue>& ArgValues); 1053 1054 /// LowerCallTo - This hook lowers an abstract call to a function into an 1055 /// actual call. This returns a pair of operands. The first element is the 1056 /// return value for the function (if RetTy is not VoidTy). The second 1057 /// element is the outgoing token chain. 1058 struct ArgListEntry { 1059 SDValue Node; 1060 const Type* Ty; 1061 bool isSExt : 1; 1062 bool isZExt : 1; 1063 bool isInReg : 1; 1064 bool isSRet : 1; 1065 bool isNest : 1; 1066 bool isByVal : 1; 1067 uint16_t Alignment; 1068 1069 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1070 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1071 }; 1072 typedef std::vector<ArgListEntry> ArgListTy; 1073 virtual std::pair<SDValue, SDValue> 1074 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1075 bool isVarArg, bool isInreg, unsigned CallingConv, 1076 bool isTailCall, SDValue Callee, ArgListTy &Args, 1077 SelectionDAG &DAG); 1078 1079 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1080 /// memcpy. This can be used by targets to provide code sequences for cases 1081 /// that don't fit the target's parameters for simple loads/stores and can be 1082 /// more efficient than using a library call. This function can return a null 1083 /// SDValue if the target declines to use custom code and a different 1084 /// lowering strategy should be used. 1085 /// 1086 /// If AlwaysInline is true, the size is constant and the target should not 1087 /// emit any calls and is strongly encouraged to attempt to emit inline code 1088 /// even if it is beyond the usual threshold because this intrinsic is being 1089 /// expanded in a place where calls are not feasible (e.g. within the prologue 1090 /// for another call). If the target chooses to decline an AlwaysInline 1091 /// request here, legalize will resort to using simple loads and stores. 1092 virtual SDValue 1093 EmitTargetCodeForMemcpy(SelectionDAG &DAG, 1094 SDValue Chain, 1095 SDValue Op1, SDValue Op2, 1096 SDValue Op3, unsigned Align, 1097 bool AlwaysInline, 1098 const Value *DstSV, uint64_t DstOff, 1099 const Value *SrcSV, uint64_t SrcOff) { 1100 return SDValue(); 1101 } 1102 1103 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1104 /// memmove. This can be used by targets to provide code sequences for cases 1105 /// that don't fit the target's parameters for simple loads/stores and can be 1106 /// more efficient than using a library call. This function can return a null 1107 /// SDValue if the target declines to use custom code and a different 1108 /// lowering strategy should be used. 1109 virtual SDValue 1110 EmitTargetCodeForMemmove(SelectionDAG &DAG, 1111 SDValue Chain, 1112 SDValue Op1, SDValue Op2, 1113 SDValue Op3, unsigned Align, 1114 const Value *DstSV, uint64_t DstOff, 1115 const Value *SrcSV, uint64_t SrcOff) { 1116 return SDValue(); 1117 } 1118 1119 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1120 /// memset. This can be used by targets to provide code sequences for cases 1121 /// that don't fit the target's parameters for simple stores and can be more 1122 /// efficient than using a library call. This function can return a null 1123 /// SDValue if the target declines to use custom code and a different 1124 /// lowering strategy should be used. 1125 virtual SDValue 1126 EmitTargetCodeForMemset(SelectionDAG &DAG, 1127 SDValue Chain, 1128 SDValue Op1, SDValue Op2, 1129 SDValue Op3, unsigned Align, 1130 const Value *DstSV, uint64_t DstOff) { 1131 return SDValue(); 1132 } 1133 1134 /// LowerOperation - This callback is invoked for operations that are 1135 /// unsupported by the target, which are registered to use 'custom' lowering, 1136 /// and whose defined values are all legal. 1137 /// If the target has no operations that require custom lowering, it need not 1138 /// implement this. The default implementation of this aborts. 1139 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1140 1141 /// ReplaceNodeResults - This callback is invoked when a node result type is 1142 /// illegal for the target, and the operation was registered to use 'custom' 1143 /// lowering for that result type. The target places new result values for 1144 /// the node in Results (their number and types must exactly match those of 1145 /// the original return values of the node), or leaves Results empty, which 1146 /// indicates that the node is not to be custom lowered after all. 1147 /// 1148 /// If the target has no operations that require custom lowering, it need not 1149 /// implement this. The default implementation aborts. 1150 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1151 SelectionDAG &DAG) { 1152 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1153 } 1154 1155 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1156 /// tail call optimization. Targets which want to do tail call optimization 1157 /// should override this function. 1158 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call, 1159 SDValue Ret, 1160 SelectionDAG &DAG) const { 1161 return false; 1162 } 1163 1164 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly 1165 /// preceeds the RET node and whether the return uses the result of the node 1166 /// or is a void return. This function can be used by the target to determine 1167 /// eligiblity of tail call optimization. 1168 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret) { 1169 unsigned NumOps = Ret.getNumOperands(); 1170 if ((NumOps == 1 && 1171 (Ret.getOperand(0) == SDValue(TheCall,1) || 1172 Ret.getOperand(0) == SDValue(TheCall,0))) || 1173 (NumOps > 1 && 1174 Ret.getOperand(0) == SDValue(TheCall, 1175 TheCall->getNumValues()-1) && 1176 Ret.getOperand(1) == SDValue(TheCall,0))) 1177 return true; 1178 return false; 1179 } 1180 1181 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1182 /// it exists. Skip a possible ISD::TokenFactor. 1183 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1184 unsigned TailCallNodeOpCode) { 1185 if (Chain.getOpcode() == TailCallNodeOpCode) { 1186 return Chain; 1187 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1188 if (Chain.getNumOperands() && 1189 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1190 return Chain.getOperand(0); 1191 } 1192 return Chain; 1193 } 1194 1195 /// getTargetNodeName() - This method returns the name of a target specific 1196 /// DAG node. 1197 virtual const char *getTargetNodeName(unsigned Opcode) const; 1198 1199 /// createFastISel - This method returns a target specific FastISel object, 1200 /// or null if the target does not support "fast" ISel. 1201 virtual FastISel * 1202 createFastISel(MachineFunction &, 1203 MachineModuleInfo *, DwarfWriter *, 1204 DenseMap<const Value *, unsigned> &, 1205 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1206 DenseMap<const AllocaInst *, int> & 1207#ifndef NDEBUG 1208 , SmallSet<Instruction*, 8> &CatchInfoLost 1209#endif 1210 ) { 1211 return 0; 1212 } 1213 1214 //===--------------------------------------------------------------------===// 1215 // Inline Asm Support hooks 1216 // 1217 1218 enum ConstraintType { 1219 C_Register, // Constraint represents specific register(s). 1220 C_RegisterClass, // Constraint represents any of register(s) in class. 1221 C_Memory, // Memory constraint. 1222 C_Other, // Something else. 1223 C_Unknown // Unsupported constraint. 1224 }; 1225 1226 /// AsmOperandInfo - This contains information for each constraint that we are 1227 /// lowering. 1228 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1229 /// ConstraintCode - This contains the actual string for the code, like "m". 1230 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1231 /// most closely matches the operand. 1232 std::string ConstraintCode; 1233 1234 /// ConstraintType - Information about the constraint code, e.g. Register, 1235 /// RegisterClass, Memory, Other, Unknown. 1236 TargetLowering::ConstraintType ConstraintType; 1237 1238 /// CallOperandval - If this is the result output operand or a 1239 /// clobber, this is null, otherwise it is the incoming operand to the 1240 /// CallInst. This gets modified as the asm is processed. 1241 Value *CallOperandVal; 1242 1243 /// ConstraintVT - The ValueType for the operand value. 1244 MVT ConstraintVT; 1245 1246 /// isMatchingInputConstraint - Return true of this is an input operand that 1247 /// is a matching constraint like "4". 1248 bool isMatchingInputConstraint() const; 1249 1250 /// getMatchedOperand - If this is an input matching constraint, this method 1251 /// returns the output operand it matches. 1252 unsigned getMatchedOperand() const; 1253 1254 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1255 : InlineAsm::ConstraintInfo(info), 1256 ConstraintType(TargetLowering::C_Unknown), 1257 CallOperandVal(0), ConstraintVT(MVT::Other) { 1258 } 1259 }; 1260 1261 /// ComputeConstraintToUse - Determines the constraint code and constraint 1262 /// type to use for the specific AsmOperandInfo, setting 1263 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1264 /// being passed in is available, it can be passed in as Op, otherwise an 1265 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1266 /// constraint of the inline asm instruction being processed is 'm'. 1267 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1268 SDValue Op, 1269 bool hasMemory, 1270 SelectionDAG *DAG = 0) const; 1271 1272 /// getConstraintType - Given a constraint, return the type of constraint it 1273 /// is for this target. 1274 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1275 1276 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1277 /// return a list of registers that can be used to satisfy the constraint. 1278 /// This should only be used for C_RegisterClass constraints. 1279 virtual std::vector<unsigned> 1280 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1281 MVT VT) const; 1282 1283 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1284 /// {edx}), return the register number and the register class for the 1285 /// register. 1286 /// 1287 /// Given a register class constraint, like 'r', if this corresponds directly 1288 /// to an LLVM register class, return a register of 0 and the register class 1289 /// pointer. 1290 /// 1291 /// This should only be used for C_Register constraints. On error, 1292 /// this returns a register number of 0 and a null register class pointer.. 1293 virtual std::pair<unsigned, const TargetRegisterClass*> 1294 getRegForInlineAsmConstraint(const std::string &Constraint, 1295 MVT VT) const; 1296 1297 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1298 /// with another that has more specific requirements based on the type of the 1299 /// corresponding operand. This returns null if there is no replacement to 1300 /// make. 1301 virtual const char *LowerXConstraint(MVT ConstraintVT) const; 1302 1303 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1304 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1305 /// it means one of the asm constraint of the inline asm instruction being 1306 /// processed is 'm'. 1307 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1308 bool hasMemory, 1309 std::vector<SDValue> &Ops, 1310 SelectionDAG &DAG) const; 1311 1312 //===--------------------------------------------------------------------===// 1313 // Scheduler hooks 1314 // 1315 1316 // EmitInstrWithCustomInserter - This method should be implemented by targets 1317 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1318 // instructions are special in various ways, which require special support to 1319 // insert. The specified MachineInstr is created but not inserted into any 1320 // basic blocks, and the scheduler passes ownership of it to this method. 1321 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1322 MachineBasicBlock *MBB); 1323 1324 //===--------------------------------------------------------------------===// 1325 // Addressing mode description hooks (used by LSR etc). 1326 // 1327 1328 /// AddrMode - This represents an addressing mode of: 1329 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1330 /// If BaseGV is null, there is no BaseGV. 1331 /// If BaseOffs is zero, there is no base offset. 1332 /// If HasBaseReg is false, there is no base register. 1333 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1334 /// no scale. 1335 /// 1336 struct AddrMode { 1337 GlobalValue *BaseGV; 1338 int64_t BaseOffs; 1339 bool HasBaseReg; 1340 int64_t Scale; 1341 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1342 }; 1343 1344 /// isLegalAddressingMode - Return true if the addressing mode represented by 1345 /// AM is legal for this target, for a load/store of the specified type. 1346 /// TODO: Handle pre/postinc as well. 1347 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1348 1349 /// isTruncateFree - Return true if it's free to truncate a value of 1350 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1351 /// register EAX to i16 by referencing its sub-register AX. 1352 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1353 return false; 1354 } 1355 1356 virtual bool isTruncateFree(MVT VT1, MVT VT2) const { 1357 return false; 1358 } 1359 1360 //===--------------------------------------------------------------------===// 1361 // Div utility functions 1362 // 1363 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1364 std::vector<SDNode*>* Created) const; 1365 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1366 std::vector<SDNode*>* Created) const; 1367 1368 1369 //===--------------------------------------------------------------------===// 1370 // Runtime Library hooks 1371 // 1372 1373 /// setLibcallName - Rename the default libcall routine name for the specified 1374 /// libcall. 1375 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1376 LibcallRoutineNames[Call] = Name; 1377 } 1378 1379 /// getLibcallName - Get the libcall routine name for the specified libcall. 1380 /// 1381 const char *getLibcallName(RTLIB::Libcall Call) const { 1382 return LibcallRoutineNames[Call]; 1383 } 1384 1385 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1386 /// result of the comparison libcall against zero. 1387 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1388 CmpLibcallCCs[Call] = CC; 1389 } 1390 1391 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1392 /// the comparison libcall against zero. 1393 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1394 return CmpLibcallCCs[Call]; 1395 } 1396 1397private: 1398 TargetMachine &TM; 1399 const TargetData *TD; 1400 1401 /// PointerTy - The type to use for pointers, usually i32 or i64. 1402 /// 1403 MVT PointerTy; 1404 1405 /// IsLittleEndian - True if this is a little endian target. 1406 /// 1407 bool IsLittleEndian; 1408 1409 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1410 /// 1411 bool UsesGlobalOffsetTable; 1412 1413 /// SelectIsExpensive - Tells the code generator not to expand operations 1414 /// into sequences that use the select operations if possible. 1415 bool SelectIsExpensive; 1416 1417 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1418 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1419 /// a real cost model is in place. If we ever optimize for size, this will be 1420 /// set to true unconditionally. 1421 bool IntDivIsCheap; 1422 1423 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1424 /// srl/add/sra for a signed divide by power of two, and let the target handle 1425 /// it. 1426 bool Pow2DivIsCheap; 1427 1428 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1429 /// llvm.setjmp. Defaults to false. 1430 bool UseUnderscoreSetJmp; 1431 1432 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1433 /// llvm.longjmp. Defaults to false. 1434 bool UseUnderscoreLongJmp; 1435 1436 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1437 /// PointerTy is. 1438 MVT ShiftAmountTy; 1439 1440 OutOfRangeShiftAmount ShiftAmtHandling; 1441 1442 /// BooleanContents - Information about the contents of the high-bits in 1443 /// boolean values held in a type wider than i1. See getBooleanContents. 1444 BooleanContent BooleanContents; 1445 1446 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1447 /// total cycles or lowest register usage. 1448 SchedPreference SchedPreferenceInfo; 1449 1450 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1451 unsigned JumpBufSize; 1452 1453 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1454 /// buffers 1455 unsigned JumpBufAlignment; 1456 1457 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1458 /// if-converted. 1459 unsigned IfCvtBlockSizeLimit; 1460 1461 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1462 /// duplicated during if-conversion. 1463 unsigned IfCvtDupBlockSizeLimit; 1464 1465 /// PrefLoopAlignment - The perferred loop alignment. 1466 /// 1467 unsigned PrefLoopAlignment; 1468 1469 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1470 /// specifies the register that llvm.savestack/llvm.restorestack should save 1471 /// and restore. 1472 unsigned StackPointerRegisterToSaveRestore; 1473 1474 /// ExceptionPointerRegister - If set to a physical register, this specifies 1475 /// the register that receives the exception address on entry to a landing 1476 /// pad. 1477 unsigned ExceptionPointerRegister; 1478 1479 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1480 /// the register that receives the exception typeid on entry to a landing 1481 /// pad. 1482 unsigned ExceptionSelectorRegister; 1483 1484 /// RegClassForVT - This indicates the default register class to use for 1485 /// each ValueType the target supports natively. 1486 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1487 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1488 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1489 1490 /// TransformToType - For any value types we are promoting or expanding, this 1491 /// contains the value type that we are changing to. For Expanded types, this 1492 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1493 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1494 /// by the system, this holds the same type (e.g. i32 -> i32). 1495 MVT TransformToType[MVT::LAST_VALUETYPE]; 1496 1497 /// OpActions - For each operation and each value type, keep a LegalizeAction 1498 /// that indicates how instruction selection should deal with the operation. 1499 /// Most operations are Legal (aka, supported natively by the target), but 1500 /// operations that are not should be described. Note that operations on 1501 /// non-legal value types are not described here. 1502 uint64_t OpActions[ISD::BUILTIN_OP_END]; 1503 1504 /// LoadExtActions - For each load of load extension type and each value type, 1505 /// keep a LegalizeAction that indicates how instruction selection should deal 1506 /// with the load. 1507 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1508 1509 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1510 /// indicates how instruction selection should deal with the store. 1511 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1512 1513 /// IndexedModeActions - For each indexed mode and each value type, keep a 1514 /// pair of LegalizeAction that indicates how instruction selection should 1515 /// deal with the load / store. 1516 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1517 1518 /// ConvertActions - For each conversion from source type to destination type, 1519 /// keep a LegalizeAction that indicates how instruction selection should 1520 /// deal with the conversion. 1521 /// Currently, this is used only for floating->floating conversions 1522 /// (FP_EXTEND and FP_ROUND). 1523 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1524 1525 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1526 /// LegalizeAction that indicates how instruction selection should 1527 /// deal with the condition code. 1528 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1529 1530 ValueTypeActionImpl ValueTypeActions; 1531 1532 std::vector<APFloat> LegalFPImmediates; 1533 1534 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses; 1535 1536 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1537 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1538 /// which sets a bit in this array. 1539 unsigned char 1540 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1541 1542 /// PromoteToType - For operations that must be promoted to a specific type, 1543 /// this holds the destination type. This map should be sparse, so don't hold 1544 /// it as an array. 1545 /// 1546 /// Targets add entries to this map with AddPromotedToType(..), clients access 1547 /// this with getTypeToPromoteTo(..). 1548 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1549 PromoteToType; 1550 1551 /// LibcallRoutineNames - Stores the name each libcall. 1552 /// 1553 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1554 1555 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1556 /// of each of the comparison libcall against zero. 1557 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1558 1559protected: 1560 /// When lowering @llvm.memset this field specifies the maximum number of 1561 /// store operations that may be substituted for the call to memset. Targets 1562 /// must set this value based on the cost threshold for that target. Targets 1563 /// should assume that the memset will be done using as many of the largest 1564 /// store operations first, followed by smaller ones, if necessary, per 1565 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1566 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1567 /// store. This only applies to setting a constant array of a constant size. 1568 /// @brief Specify maximum number of store instructions per memset call. 1569 unsigned maxStoresPerMemset; 1570 1571 /// When lowering @llvm.memcpy this field specifies the maximum number of 1572 /// store operations that may be substituted for a call to memcpy. Targets 1573 /// must set this value based on the cost threshold for that target. Targets 1574 /// should assume that the memcpy will be done using as many of the largest 1575 /// store operations first, followed by smaller ones, if necessary, per 1576 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1577 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1578 /// and one 1-byte store. This only applies to copying a constant array of 1579 /// constant size. 1580 /// @brief Specify maximum bytes of store instructions per memcpy call. 1581 unsigned maxStoresPerMemcpy; 1582 1583 /// When lowering @llvm.memmove this field specifies the maximum number of 1584 /// store instructions that may be substituted for a call to memmove. Targets 1585 /// must set this value based on the cost threshold for that target. Targets 1586 /// should assume that the memmove will be done using as many of the largest 1587 /// store operations first, followed by smaller ones, if necessary, per 1588 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1589 /// with 8-bit alignment would result in nine 1-byte stores. This only 1590 /// applies to copying a constant array of constant size. 1591 /// @brief Specify maximum bytes of store instructions per memmove call. 1592 unsigned maxStoresPerMemmove; 1593 1594 /// This field specifies whether the target machine permits unaligned memory 1595 /// accesses. This is used, for example, to determine the size of store 1596 /// operations when copying small arrays and other similar tasks. 1597 /// @brief Indicate whether the target permits unaligned memory accesses. 1598 bool allowUnalignedMemoryAccesses; 1599}; 1600} // end llvm namespace 1601 1602#endif 1603