TargetLowering.h revision 8b944d39b356135676459152385f05c496951f6c
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/InlineAsm.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/ADT/APFloat.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallSet.h" 31#include "llvm/ADT/SmallVector.h" 32#include "llvm/ADT/STLExtras.h" 33#include "llvm/CodeGen/DebugLoc.h" 34#include "llvm/Target/TargetMachine.h" 35#include <climits> 36#include <map> 37#include <vector> 38 39namespace llvm { 40 class AllocaInst; 41 class CallInst; 42 class Function; 43 class FastISel; 44 class MachineBasicBlock; 45 class MachineFunction; 46 class MachineFrameInfo; 47 class MachineInstr; 48 class MachineModuleInfo; 49 class DwarfWriter; 50 class SDNode; 51 class SDValue; 52 class SelectionDAG; 53 class TargetData; 54 class TargetMachine; 55 class TargetRegisterClass; 56 class TargetSubtarget; 57 class Value; 58 59 // FIXME: should this be here? 60 namespace TLSModel { 61 enum Model { 62 GeneralDynamic, 63 LocalDynamic, 64 InitialExec, 65 LocalExec 66 }; 67 } 68 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 69 70 71//===----------------------------------------------------------------------===// 72/// TargetLowering - This class defines information used to lower LLVM code to 73/// legal SelectionDAG operators that the target instruction selector can accept 74/// natively. 75/// 76/// This class also defines callbacks that targets must implement to lower 77/// target-specific constructs to SelectionDAG operators. 78/// 79class TargetLowering { 80public: 81 /// LegalizeAction - This enum indicates whether operations are valid for a 82 /// target, and if not, what action should be used to make them valid. 83 enum LegalizeAction { 84 Legal, // The target natively supports this operation. 85 Promote, // This operation should be executed in a larger type. 86 Expand, // Try to expand this to other ops, otherwise use a libcall. 87 Custom // Use the LowerOperation hook to implement custom lowering. 88 }; 89 90 enum OutOfRangeShiftAmount { 91 Undefined, // Oversized shift amounts are undefined (default). 92 Mask, // Shift amounts are auto masked (anded) to value size. 93 Extend // Oversized shift pulls in zeros or sign bits. 94 }; 95 96 enum BooleanContent { // How the target represents true/false values. 97 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 98 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 99 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 100 }; 101 102 enum SchedPreference { 103 SchedulingForLatency, // Scheduling for shortest total latency. 104 SchedulingForRegPressure // Scheduling for lowest register pressure. 105 }; 106 107 explicit TargetLowering(TargetMachine &TM); 108 virtual ~TargetLowering(); 109 110 TargetMachine &getTargetMachine() const { return TM; } 111 const TargetData *getTargetData() const { return TD; } 112 113 bool isBigEndian() const { return !IsLittleEndian; } 114 bool isLittleEndian() const { return IsLittleEndian; } 115 MVT getPointerTy() const { return PointerTy; } 116 MVT getShiftAmountTy() const { return ShiftAmountTy; } 117 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 118 119 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 120 /// codegen. 121 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 122 123 /// isSelectExpensive - Return true if the select operation is expensive for 124 /// this target. 125 bool isSelectExpensive() const { return SelectIsExpensive; } 126 127 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 128 /// a sequence of several shifts, adds, and multiplies for this target. 129 bool isIntDivCheap() const { return IntDivIsCheap; } 130 131 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 132 /// srl/add/sra. 133 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 134 135 /// getSetCCResultType - Return the ValueType of the result of SETCC 136 /// operations. Also used to obtain the target's preferred type for 137 /// the condition operand of SELECT and BRCOND nodes. In the case of 138 /// BRCOND the argument passed is MVT::Other since there are no other 139 /// operands to get a type hint from. 140 virtual MVT getSetCCResultType(MVT VT) const; 141 142 /// getBooleanContents - For targets without i1 registers, this gives the 143 /// nature of the high-bits of boolean values held in types wider than i1. 144 /// "Boolean values" are special true/false values produced by nodes like 145 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 146 /// Not to be confused with general values promoted from i1. 147 BooleanContent getBooleanContents() const { return BooleanContents;} 148 149 /// getSchedulingPreference - Return target scheduling preference. 150 SchedPreference getSchedulingPreference() const { 151 return SchedPreferenceInfo; 152 } 153 154 /// getRegClassFor - Return the register class that should be used for the 155 /// specified value type. This may only be called on legal types. 156 TargetRegisterClass *getRegClassFor(MVT VT) const { 157 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 158 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; 159 assert(RC && "This value type is not natively supported!"); 160 return RC; 161 } 162 163 /// isTypeLegal - Return true if the target has native support for the 164 /// specified value type. This means that it has a register that directly 165 /// holds it without promotions or expansions. 166 bool isTypeLegal(MVT VT) const { 167 assert(!VT.isSimple() || 168 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 169 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; 170 } 171 172 class ValueTypeActionImpl { 173 /// ValueTypeActions - This is a bitvector that contains two bits for each 174 /// value type, where the two bits correspond to the LegalizeAction enum. 175 /// This can be queried with "getTypeAction(VT)". 176 uint32_t ValueTypeActions[2]; 177 public: 178 ValueTypeActionImpl() { 179 ValueTypeActions[0] = ValueTypeActions[1] = 0; 180 } 181 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 182 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 183 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 184 } 185 186 LegalizeAction getTypeAction(MVT VT) const { 187 if (VT.isExtended()) { 188 if (VT.isVector()) { 189 return VT.isPow2VectorType() ? Expand : Promote; 190 } 191 if (VT.isInteger()) 192 // First promote to a power-of-two size, then expand if necessary. 193 return VT == VT.getRoundIntegerType() ? Expand : Promote; 194 assert(0 && "Unsupported extended type!"); 195 return Legal; 196 } 197 unsigned I = VT.getSimpleVT(); 198 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 199 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 200 } 201 void setTypeAction(MVT VT, LegalizeAction Action) { 202 unsigned I = VT.getSimpleVT(); 203 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 204 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 205 } 206 }; 207 208 const ValueTypeActionImpl &getValueTypeActions() const { 209 return ValueTypeActions; 210 } 211 212 /// getTypeAction - Return how we should legalize values of this type, either 213 /// it is already legal (return 'Legal') or we need to promote it to a larger 214 /// type (return 'Promote'), or we need to expand it into multiple registers 215 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 216 LegalizeAction getTypeAction(MVT VT) const { 217 return ValueTypeActions.getTypeAction(VT); 218 } 219 220 /// getTypeToTransformTo - For types supported by the target, this is an 221 /// identity function. For types that must be promoted to larger types, this 222 /// returns the larger type to promote to. For integer types that are larger 223 /// than the largest integer register, this contains one step in the expansion 224 /// to get to the smaller register. For illegal floating point types, this 225 /// returns the integer type to transform to. 226 MVT getTypeToTransformTo(MVT VT) const { 227 if (VT.isSimple()) { 228 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); 229 MVT NVT = TransformToType[VT.getSimpleVT()]; 230 assert(getTypeAction(NVT) != Promote && 231 "Promote may not follow Expand or Promote"); 232 return NVT; 233 } 234 235 if (VT.isVector()) { 236 MVT NVT = VT.getPow2VectorType(); 237 if (NVT == VT) { 238 // Vector length is a power of 2 - split to half the size. 239 unsigned NumElts = VT.getVectorNumElements(); 240 MVT EltVT = VT.getVectorElementType(); 241 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2); 242 } 243 // Promote to a power of two size, avoiding multi-step promotion. 244 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 245 } else if (VT.isInteger()) { 246 MVT NVT = VT.getRoundIntegerType(); 247 if (NVT == VT) 248 // Size is a power of two - expand to half the size. 249 return MVT::getIntegerVT(VT.getSizeInBits() / 2); 250 else 251 // Promote to a power of two size, avoiding multi-step promotion. 252 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 253 } 254 assert(0 && "Unsupported extended type!"); 255 return MVT(); // Not reached 256 } 257 258 /// getTypeToExpandTo - For types supported by the target, this is an 259 /// identity function. For types that must be expanded (i.e. integer types 260 /// that are larger than the largest integer register or illegal floating 261 /// point types), this returns the largest legal type it will be expanded to. 262 MVT getTypeToExpandTo(MVT VT) const { 263 assert(!VT.isVector()); 264 while (true) { 265 switch (getTypeAction(VT)) { 266 case Legal: 267 return VT; 268 case Expand: 269 VT = getTypeToTransformTo(VT); 270 break; 271 default: 272 assert(false && "Type is not legal nor is it to be expanded!"); 273 return VT; 274 } 275 } 276 return VT; 277 } 278 279 /// getVectorTypeBreakdown - Vector types are broken down into some number of 280 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 281 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 282 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 283 /// 284 /// This method returns the number of registers needed, and the VT for each 285 /// register. It also returns the VT and quantity of the intermediate values 286 /// before they are promoted/expanded. 287 /// 288 unsigned getVectorTypeBreakdown(MVT VT, 289 MVT &IntermediateVT, 290 unsigned &NumIntermediates, 291 MVT &RegisterVT) const; 292 293 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 294 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 295 /// this is the case, it returns true and store the intrinsic 296 /// information into the IntrinsicInfo that was passed to the function. 297 typedef struct IntrinsicInfo { 298 unsigned opc; // target opcode 299 MVT memVT; // memory VT 300 const Value* ptrVal; // value representing memory location 301 int offset; // offset off of ptrVal 302 unsigned align; // alignment 303 bool vol; // is volatile? 304 bool readMem; // reads memory? 305 bool writeMem; // writes memory? 306 } IntrinisicInfo; 307 308 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 309 CallInst &I, unsigned Intrinsic) { 310 return false; 311 } 312 313 /// getWidenVectorType: given a vector type, returns the type to widen to 314 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 315 /// If there is no vector type that we want to widen to, returns MVT::Other 316 /// When and were to widen is target dependent based on the cost of 317 /// scalarizing vs using the wider vector type. 318 virtual MVT getWidenVectorType(MVT VT) const; 319 320 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 321 legal_fpimm_iterator legal_fpimm_begin() const { 322 return LegalFPImmediates.begin(); 323 } 324 legal_fpimm_iterator legal_fpimm_end() const { 325 return LegalFPImmediates.end(); 326 } 327 328 /// isShuffleMaskLegal - Targets can use this to indicate that they only 329 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 330 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 331 /// are assumed to be legal. 332 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 333 MVT VT) const { 334 return true; 335 } 336 337 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 338 /// used by Targets can use this to indicate if there is a suitable 339 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 340 /// pool entry. 341 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 342 MVT VT) const { 343 return false; 344 } 345 346 /// getOperationAction - Return how this operation should be treated: either 347 /// it is legal, needs to be promoted to a larger size, needs to be 348 /// expanded to some other code sequence, or the target has a custom expander 349 /// for it. 350 LegalizeAction getOperationAction(unsigned Op, MVT VT) const { 351 if (VT.isExtended()) return Expand; 352 assert(Op < array_lengthof(OpActions) && 353 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 354 "Table isn't big enough!"); 355 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); 356 } 357 358 /// isOperationLegalOrCustom - Return true if the specified operation is 359 /// legal on this target or can be made legal with custom lowering. This 360 /// is used to help guide high-level lowering decisions. 361 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const { 362 return (VT == MVT::Other || isTypeLegal(VT)) && 363 (getOperationAction(Op, VT) == Legal || 364 getOperationAction(Op, VT) == Custom); 365 } 366 367 /// isOperationLegal - Return true if the specified operation is legal on this 368 /// target. 369 bool isOperationLegal(unsigned Op, MVT VT) const { 370 return (VT == MVT::Other || isTypeLegal(VT)) && 371 getOperationAction(Op, VT) == Legal; 372 } 373 374 /// getLoadExtAction - Return how this load with extension should be treated: 375 /// either it is legal, needs to be promoted to a larger size, needs to be 376 /// expanded to some other code sequence, or the target has a custom expander 377 /// for it. 378 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const { 379 assert(LType < array_lengthof(LoadExtActions) && 380 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 381 "Table isn't big enough!"); 382 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3); 383 } 384 385 /// isLoadExtLegal - Return true if the specified load with extension is legal 386 /// on this target. 387 bool isLoadExtLegal(unsigned LType, MVT VT) const { 388 return VT.isSimple() && 389 (getLoadExtAction(LType, VT) == Legal || 390 getLoadExtAction(LType, VT) == Custom); 391 } 392 393 /// getTruncStoreAction - Return how this store with truncation should be 394 /// treated: either it is legal, needs to be promoted to a larger size, needs 395 /// to be expanded to some other code sequence, or the target has a custom 396 /// expander for it. 397 LegalizeAction getTruncStoreAction(MVT ValVT, 398 MVT MemVT) const { 399 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 400 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 401 "Table isn't big enough!"); 402 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> 403 (2*MemVT.getSimpleVT())) & 3); 404 } 405 406 /// isTruncStoreLegal - Return true if the specified store with truncation is 407 /// legal on this target. 408 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { 409 return isTypeLegal(ValVT) && MemVT.isSimple() && 410 (getTruncStoreAction(ValVT, MemVT) == Legal || 411 getTruncStoreAction(ValVT, MemVT) == Custom); 412 } 413 414 /// getIndexedLoadAction - Return how the indexed load should be treated: 415 /// either it is legal, needs to be promoted to a larger size, needs to be 416 /// expanded to some other code sequence, or the target has a custom expander 417 /// for it. 418 LegalizeAction 419 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 420 assert(IdxMode < array_lengthof(IndexedModeActions[0]) && 421 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 && 422 "Table isn't big enough!"); 423 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> 424 (2*VT.getSimpleVT())) & 3); 425 } 426 427 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 428 /// on this target. 429 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { 430 return VT.isSimple() && 431 (getIndexedLoadAction(IdxMode, VT) == Legal || 432 getIndexedLoadAction(IdxMode, VT) == Custom); 433 } 434 435 /// getIndexedStoreAction - Return how the indexed store should be treated: 436 /// either it is legal, needs to be promoted to a larger size, needs to be 437 /// expanded to some other code sequence, or the target has a custom expander 438 /// for it. 439 LegalizeAction 440 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 441 assert(IdxMode < array_lengthof(IndexedModeActions[1]) && 442 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 443 "Table isn't big enough!"); 444 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> 445 (2*VT.getSimpleVT())) & 3); 446 } 447 448 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 449 /// on this target. 450 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { 451 return VT.isSimple() && 452 (getIndexedStoreAction(IdxMode, VT) == Legal || 453 getIndexedStoreAction(IdxMode, VT) == Custom); 454 } 455 456 /// getConvertAction - Return how the conversion should be treated: 457 /// either it is legal, needs to be promoted to a larger size, needs to be 458 /// expanded to some other code sequence, or the target has a custom expander 459 /// for it. 460 LegalizeAction 461 getConvertAction(MVT FromVT, MVT ToVT) const { 462 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 463 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 464 "Table isn't big enough!"); 465 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> 466 (2*ToVT.getSimpleVT())) & 3); 467 } 468 469 /// isConvertLegal - Return true if the specified conversion is legal 470 /// on this target. 471 bool isConvertLegal(MVT FromVT, MVT ToVT) const { 472 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 473 (getConvertAction(FromVT, ToVT) == Legal || 474 getConvertAction(FromVT, ToVT) == Custom); 475 } 476 477 /// getCondCodeAction - Return how the condition code should be treated: 478 /// either it is legal, needs to be expanded to some other code sequence, 479 /// or the target has a custom expander for it. 480 LegalizeAction 481 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 482 assert((unsigned)CC < array_lengthof(CondCodeActions) && 483 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 484 "Table isn't big enough!"); 485 LegalizeAction Action = (LegalizeAction) 486 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3); 487 assert(Action != Promote && "Can't promote condition code!"); 488 return Action; 489 } 490 491 /// isCondCodeLegal - Return true if the specified condition code is legal 492 /// on this target. 493 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 494 return getCondCodeAction(CC, VT) == Legal || 495 getCondCodeAction(CC, VT) == Custom; 496 } 497 498 499 /// getTypeToPromoteTo - If the action for this operation is to promote, this 500 /// method returns the ValueType to promote to. 501 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 502 assert(getOperationAction(Op, VT) == Promote && 503 "This operation isn't promoted!"); 504 505 // See if this has an explicit type specified. 506 std::map<std::pair<unsigned, MVT::SimpleValueType>, 507 MVT::SimpleValueType>::const_iterator PTTI = 508 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); 509 if (PTTI != PromoteToType.end()) return PTTI->second; 510 511 assert((VT.isInteger() || VT.isFloatingPoint()) && 512 "Cannot autopromote this type, add it with AddPromotedToType."); 513 514 MVT NVT = VT; 515 do { 516 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); 517 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 518 "Didn't find type to promote to!"); 519 } while (!isTypeLegal(NVT) || 520 getOperationAction(Op, NVT) == Promote); 521 return NVT; 522 } 523 524 /// getValueType - Return the MVT corresponding to this LLVM type. 525 /// This is fixed by the LLVM operations except for the pointer size. If 526 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 527 /// counterpart (e.g. structs), otherwise it will assert. 528 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 529 MVT VT = MVT::getMVT(Ty, AllowUnknown); 530 return VT == MVT::iPTR ? PointerTy : VT; 531 } 532 533 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 534 /// function arguments in the caller parameter area. This is the actual 535 /// alignment, not its logarithm. 536 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 537 538 /// getRegisterType - Return the type of registers that this ValueType will 539 /// eventually require. 540 MVT getRegisterType(MVT VT) const { 541 if (VT.isSimple()) { 542 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); 543 return RegisterTypeForVT[VT.getSimpleVT()]; 544 } 545 if (VT.isVector()) { 546 MVT VT1, RegisterVT; 547 unsigned NumIntermediates; 548 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 549 return RegisterVT; 550 } 551 if (VT.isInteger()) { 552 return getRegisterType(getTypeToTransformTo(VT)); 553 } 554 assert(0 && "Unsupported extended type!"); 555 return MVT(); // Not reached 556 } 557 558 /// getNumRegisters - Return the number of registers that this ValueType will 559 /// eventually require. This is one for any types promoted to live in larger 560 /// registers, but may be more than one for types (like i64) that are split 561 /// into pieces. For types like i140, which are first promoted then expanded, 562 /// it is the number of registers needed to hold all the bits of the original 563 /// type. For an i140 on a 32 bit machine this means 5 registers. 564 unsigned getNumRegisters(MVT VT) const { 565 if (VT.isSimple()) { 566 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); 567 return NumRegistersForVT[VT.getSimpleVT()]; 568 } 569 if (VT.isVector()) { 570 MVT VT1, VT2; 571 unsigned NumIntermediates; 572 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 573 } 574 if (VT.isInteger()) { 575 unsigned BitWidth = VT.getSizeInBits(); 576 unsigned RegWidth = getRegisterType(VT).getSizeInBits(); 577 return (BitWidth + RegWidth - 1) / RegWidth; 578 } 579 assert(0 && "Unsupported extended type!"); 580 return 0; // Not reached 581 } 582 583 /// ShouldShrinkFPConstant - If true, then instruction selection should 584 /// seek to shrink the FP constant of the specified type to a smaller type 585 /// in order to save space and / or reduce runtime. 586 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } 587 588 /// hasTargetDAGCombine - If true, the target has custom DAG combine 589 /// transformations that it can perform for the specified node. 590 bool hasTargetDAGCombine(ISD::NodeType NT) const { 591 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 592 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 593 } 594 595 /// This function returns the maximum number of store operations permitted 596 /// to replace a call to llvm.memset. The value is set by the target at the 597 /// performance threshold for such a replacement. 598 /// @brief Get maximum # of store operations permitted for llvm.memset 599 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 600 601 /// This function returns the maximum number of store operations permitted 602 /// to replace a call to llvm.memcpy. The value is set by the target at the 603 /// performance threshold for such a replacement. 604 /// @brief Get maximum # of store operations permitted for llvm.memcpy 605 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 606 607 /// This function returns the maximum number of store operations permitted 608 /// to replace a call to llvm.memmove. The value is set by the target at the 609 /// performance threshold for such a replacement. 610 /// @brief Get maximum # of store operations permitted for llvm.memmove 611 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 612 613 /// This function returns true if the target allows unaligned memory accesses. 614 /// This is used, for example, in situations where an array copy/move/set is 615 /// converted to a sequence of store operations. It's use helps to ensure that 616 /// such replacements don't generate code that causes an alignment error 617 /// (trap) on the target machine. 618 /// @brief Determine if the target supports unaligned memory accesses. 619 bool allowsUnalignedMemoryAccesses() const { 620 return allowUnalignedMemoryAccesses; 621 } 622 623 /// This function returns true if the target would benefit from code placement 624 /// optimization. 625 /// @brief Determine if the target should perform code placement optimization. 626 bool shouldOptimizeCodePlacement() const { 627 return benefitFromCodePlacementOpt; 628 } 629 630 /// getOptimalMemOpType - Returns the target specific optimal type for load 631 /// and store operations as a result of memset, memcpy, and memmove lowering. 632 /// It returns MVT::iAny if SelectionDAG should be responsible for 633 /// determining it. 634 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, 635 bool isSrcConst, bool isSrcStr) const { 636 return MVT::iAny; 637 } 638 639 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 640 /// to implement llvm.setjmp. 641 bool usesUnderscoreSetJmp() const { 642 return UseUnderscoreSetJmp; 643 } 644 645 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 646 /// to implement llvm.longjmp. 647 bool usesUnderscoreLongJmp() const { 648 return UseUnderscoreLongJmp; 649 } 650 651 /// getStackPointerRegisterToSaveRestore - If a physical register, this 652 /// specifies the register that llvm.savestack/llvm.restorestack should save 653 /// and restore. 654 unsigned getStackPointerRegisterToSaveRestore() const { 655 return StackPointerRegisterToSaveRestore; 656 } 657 658 /// getExceptionAddressRegister - If a physical register, this returns 659 /// the register that receives the exception address on entry to a landing 660 /// pad. 661 unsigned getExceptionAddressRegister() const { 662 return ExceptionPointerRegister; 663 } 664 665 /// getExceptionSelectorRegister - If a physical register, this returns 666 /// the register that receives the exception typeid on entry to a landing 667 /// pad. 668 unsigned getExceptionSelectorRegister() const { 669 return ExceptionSelectorRegister; 670 } 671 672 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 673 /// set, the default is 200) 674 unsigned getJumpBufSize() const { 675 return JumpBufSize; 676 } 677 678 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 679 /// (if never set, the default is 0) 680 unsigned getJumpBufAlignment() const { 681 return JumpBufAlignment; 682 } 683 684 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 685 /// limit. Any block whose size is greater should not be predicated. 686 unsigned getIfCvtBlockSizeLimit() const { 687 return IfCvtBlockSizeLimit; 688 } 689 690 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 691 /// block to be considered for duplication. Any block whose size is greater 692 /// should not be duplicated to facilitate its predication. 693 unsigned getIfCvtDupBlockSizeLimit() const { 694 return IfCvtDupBlockSizeLimit; 695 } 696 697 /// getPrefLoopAlignment - return the preferred loop alignment. 698 /// 699 unsigned getPrefLoopAlignment() const { 700 return PrefLoopAlignment; 701 } 702 703 /// getPreIndexedAddressParts - returns true by value, base pointer and 704 /// offset pointer and addressing mode by reference if the node's address 705 /// can be legally represented as pre-indexed load / store address. 706 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 707 SDValue &Offset, 708 ISD::MemIndexedMode &AM, 709 SelectionDAG &DAG) const { 710 return false; 711 } 712 713 /// getPostIndexedAddressParts - returns true by value, base pointer and 714 /// offset pointer and addressing mode by reference if this node can be 715 /// combined with a load / store to form a post-indexed load / store. 716 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 717 SDValue &Base, SDValue &Offset, 718 ISD::MemIndexedMode &AM, 719 SelectionDAG &DAG) const { 720 return false; 721 } 722 723 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 724 /// jumptable. 725 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 726 SelectionDAG &DAG) const; 727 728 /// isOffsetFoldingLegal - Return true if folding a constant offset 729 /// with the given GlobalAddress is legal. It is frequently not legal in 730 /// PIC relocation models. 731 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 732 733 //===--------------------------------------------------------------------===// 734 // TargetLowering Optimization Methods 735 // 736 737 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 738 /// SDValues for returning information from TargetLowering to its clients 739 /// that want to combine 740 struct TargetLoweringOpt { 741 SelectionDAG &DAG; 742 SDValue Old; 743 SDValue New; 744 745 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 746 747 bool CombineTo(SDValue O, SDValue N) { 748 Old = O; 749 New = N; 750 return true; 751 } 752 753 /// ShrinkDemandedConstant - Check to see if the specified operand of the 754 /// specified instruction is a constant integer. If so, check to see if 755 /// there are any bits set in the constant that are not demanded. If so, 756 /// shrink the constant and return true. 757 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 758 759 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 760 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 761 /// cast, but it could be generalized for targets with other types of 762 /// implicit widening casts. 763 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 764 DebugLoc dl); 765 }; 766 767 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 768 /// DemandedMask bits of the result of Op are ever used downstream. If we can 769 /// use this information to simplify Op, create a new simplified DAG node and 770 /// return true, returning the original and new nodes in Old and New. 771 /// Otherwise, analyze the expression and return a mask of KnownOne and 772 /// KnownZero bits for the expression (used to simplify the caller). 773 /// The KnownZero/One bits may only be accurate for those bits in the 774 /// DemandedMask. 775 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 776 APInt &KnownZero, APInt &KnownOne, 777 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 778 779 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 780 /// Mask are known to be either zero or one and return them in the 781 /// KnownZero/KnownOne bitsets. 782 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 783 const APInt &Mask, 784 APInt &KnownZero, 785 APInt &KnownOne, 786 const SelectionDAG &DAG, 787 unsigned Depth = 0) const; 788 789 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 790 /// targets that want to expose additional information about sign bits to the 791 /// DAG Combiner. 792 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 793 unsigned Depth = 0) const; 794 795 struct DAGCombinerInfo { 796 void *DC; // The DAG Combiner object. 797 bool BeforeLegalize; 798 bool CalledByLegalizer; 799 public: 800 SelectionDAG &DAG; 801 802 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 803 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 804 805 bool isBeforeLegalize() const { return BeforeLegalize; } 806 bool isCalledByLegalizer() const { return CalledByLegalizer; } 807 808 void AddToWorklist(SDNode *N); 809 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 810 bool AddTo = true); 811 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 812 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 813 814 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 815 }; 816 817 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 818 /// and cc. If it is unable to simplify it, return a null SDValue. 819 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 820 ISD::CondCode Cond, bool foldBooleans, 821 DAGCombinerInfo &DCI, DebugLoc dl) const; 822 823 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 824 /// node is a GlobalAddress + offset. 825 virtual bool 826 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 827 828 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 829 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the 830 /// location that the 'Base' load is loading from. 831 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist, 832 const MachineFrameInfo *MFI) const; 833 834 /// PerformDAGCombine - This method will be invoked for all target nodes and 835 /// for any target-independent nodes that the target has registered with 836 /// invoke it for. 837 /// 838 /// The semantics are as follows: 839 /// Return Value: 840 /// SDValue.Val == 0 - No change was made 841 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 842 /// otherwise - N should be replaced by the returned Operand. 843 /// 844 /// In addition, methods provided by DAGCombinerInfo may be used to perform 845 /// more complex transformations. 846 /// 847 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 848 849 //===--------------------------------------------------------------------===// 850 // TargetLowering Configuration Methods - These methods should be invoked by 851 // the derived class constructor to configure this object for the target. 852 // 853 854protected: 855 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 856 /// GOT for PC-relative code. 857 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 858 859 /// setShiftAmountType - Describe the type that should be used for shift 860 /// amounts. This type defaults to the pointer type. 861 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 862 863 /// setBooleanContents - Specify how the target extends the result of a 864 /// boolean value from i1 to a wider type. See getBooleanContents. 865 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 866 867 /// setSchedulingPreference - Specify the target scheduling preference. 868 void setSchedulingPreference(SchedPreference Pref) { 869 SchedPreferenceInfo = Pref; 870 } 871 872 /// setShiftAmountFlavor - Describe how the target handles out of range shift 873 /// amounts. 874 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 875 ShiftAmtHandling = OORSA; 876 } 877 878 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 879 /// use _setjmp to implement llvm.setjmp or the non _ version. 880 /// Defaults to false. 881 void setUseUnderscoreSetJmp(bool Val) { 882 UseUnderscoreSetJmp = Val; 883 } 884 885 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 886 /// use _longjmp to implement llvm.longjmp or the non _ version. 887 /// Defaults to false. 888 void setUseUnderscoreLongJmp(bool Val) { 889 UseUnderscoreLongJmp = Val; 890 } 891 892 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 893 /// specifies the register that llvm.savestack/llvm.restorestack should save 894 /// and restore. 895 void setStackPointerRegisterToSaveRestore(unsigned R) { 896 StackPointerRegisterToSaveRestore = R; 897 } 898 899 /// setExceptionPointerRegister - If set to a physical register, this sets 900 /// the register that receives the exception address on entry to a landing 901 /// pad. 902 void setExceptionPointerRegister(unsigned R) { 903 ExceptionPointerRegister = R; 904 } 905 906 /// setExceptionSelectorRegister - If set to a physical register, this sets 907 /// the register that receives the exception typeid on entry to a landing 908 /// pad. 909 void setExceptionSelectorRegister(unsigned R) { 910 ExceptionSelectorRegister = R; 911 } 912 913 /// SelectIsExpensive - Tells the code generator not to expand operations 914 /// into sequences that use the select operations if possible. 915 void setSelectIsExpensive() { SelectIsExpensive = true; } 916 917 /// setIntDivIsCheap - Tells the code generator that integer divide is 918 /// expensive, and if possible, should be replaced by an alternate sequence 919 /// of instructions not containing an integer divide. 920 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 921 922 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 923 /// srl/add/sra for a signed divide by power of two, and let the target handle 924 /// it. 925 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 926 927 /// addRegisterClass - Add the specified register class as an available 928 /// regclass for the specified value type. This indicates the selector can 929 /// handle values of that class natively. 930 void addRegisterClass(MVT VT, TargetRegisterClass *RC) { 931 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 932 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 933 RegClassForVT[VT.getSimpleVT()] = RC; 934 } 935 936 /// computeRegisterProperties - Once all of the register classes are added, 937 /// this allows us to compute derived properties we expose. 938 void computeRegisterProperties(); 939 940 /// setOperationAction - Indicate that the specified operation does not work 941 /// with the specified type and indicate what to do about it. 942 void setOperationAction(unsigned Op, MVT VT, 943 LegalizeAction Action) { 944 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 945 Op < array_lengthof(OpActions) && "Table isn't big enough!"); 946 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 947 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2; 948 } 949 950 /// setLoadExtAction - Indicate that the specified load with extension does 951 /// not work with the with specified type and indicate what to do about it. 952 void setLoadExtAction(unsigned ExtType, MVT VT, 953 LegalizeAction Action) { 954 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 955 ExtType < array_lengthof(LoadExtActions) && 956 "Table isn't big enough!"); 957 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 958 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2; 959 } 960 961 /// setTruncStoreAction - Indicate that the specified truncating store does 962 /// not work with the with specified type and indicate what to do about it. 963 void setTruncStoreAction(MVT ValVT, MVT MemVT, 964 LegalizeAction Action) { 965 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 966 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 967 "Table isn't big enough!"); 968 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) << 969 MemVT.getSimpleVT()*2); 970 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action << 971 MemVT.getSimpleVT()*2; 972 } 973 974 /// setIndexedLoadAction - Indicate that the specified indexed load does or 975 /// does not work with the with specified type and indicate what to do abort 976 /// it. NOTE: All indexed mode loads are initialized to Expand in 977 /// TargetLowering.cpp 978 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 979 LegalizeAction Action) { 980 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 && 981 IdxMode < array_lengthof(IndexedModeActions[0]) && 982 "Table isn't big enough!"); 983 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 984 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 985 } 986 987 /// setIndexedStoreAction - Indicate that the specified indexed store does or 988 /// does not work with the with specified type and indicate what to do about 989 /// it. NOTE: All indexed mode stores are initialized to Expand in 990 /// TargetLowering.cpp 991 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 992 LegalizeAction Action) { 993 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 994 IdxMode < array_lengthof(IndexedModeActions[1]) && 995 "Table isn't big enough!"); 996 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 997 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 998 } 999 1000 /// setConvertAction - Indicate that the specified conversion does or does 1001 /// not work with the with specified type and indicate what to do about it. 1002 void setConvertAction(MVT FromVT, MVT ToVT, 1003 LegalizeAction Action) { 1004 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 1005 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 1006 "Table isn't big enough!"); 1007 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) << 1008 ToVT.getSimpleVT()*2); 1009 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action << 1010 ToVT.getSimpleVT()*2; 1011 } 1012 1013 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1014 /// supported on the target and indicate what to do about it. 1015 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { 1016 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 1017 (unsigned)CC < array_lengthof(CondCodeActions) && 1018 "Table isn't big enough!"); 1019 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 1020 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2; 1021 } 1022 1023 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1024 /// promotion code defaults to trying a larger integer/fp until it can find 1025 /// one that works. If that default is insufficient, this method can be used 1026 /// by the target to override the default. 1027 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1028 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] = 1029 DestVT.getSimpleVT(); 1030 } 1031 1032 /// addLegalFPImmediate - Indicate that this target can instruction select 1033 /// the specified FP immediate natively. 1034 void addLegalFPImmediate(const APFloat& Imm) { 1035 LegalFPImmediates.push_back(Imm); 1036 } 1037 1038 /// setTargetDAGCombine - Targets should invoke this method for each target 1039 /// independent node that they want to provide a custom DAG combiner for by 1040 /// implementing the PerformDAGCombine virtual method. 1041 void setTargetDAGCombine(ISD::NodeType NT) { 1042 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1043 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1044 } 1045 1046 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1047 /// bytes); default is 200 1048 void setJumpBufSize(unsigned Size) { 1049 JumpBufSize = Size; 1050 } 1051 1052 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1053 /// alignment (in bytes); default is 0 1054 void setJumpBufAlignment(unsigned Align) { 1055 JumpBufAlignment = Align; 1056 } 1057 1058 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1059 /// limit (in number of instructions); default is 2. 1060 void setIfCvtBlockSizeLimit(unsigned Limit) { 1061 IfCvtBlockSizeLimit = Limit; 1062 } 1063 1064 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1065 /// of instructions) to be considered for code duplication during 1066 /// if-conversion; default is 2. 1067 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1068 IfCvtDupBlockSizeLimit = Limit; 1069 } 1070 1071 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1072 /// alignment is zero, it means the target does not care about loop alignment. 1073 void setPrefLoopAlignment(unsigned Align) { 1074 PrefLoopAlignment = Align; 1075 } 1076 1077public: 1078 1079 virtual const TargetSubtarget *getSubtarget() { 1080 assert(0 && "Not Implemented"); 1081 return NULL; // this is here to silence compiler errors 1082 } 1083 //===--------------------------------------------------------------------===// 1084 // Lowering methods - These methods must be implemented by targets so that 1085 // the SelectionDAGLowering code knows how to lower these. 1086 // 1087 1088 /// LowerArguments - This hook must be implemented to indicate how we should 1089 /// lower the arguments for the specified function, into the specified DAG. 1090 virtual void 1091 LowerArguments(Function &F, SelectionDAG &DAG, 1092 SmallVectorImpl<SDValue>& ArgValues, DebugLoc dl); 1093 1094 /// LowerCallTo - This hook lowers an abstract call to a function into an 1095 /// actual call. This returns a pair of operands. The first element is the 1096 /// return value for the function (if RetTy is not VoidTy). The second 1097 /// element is the outgoing token chain. 1098 struct ArgListEntry { 1099 SDValue Node; 1100 const Type* Ty; 1101 bool isSExt : 1; 1102 bool isZExt : 1; 1103 bool isInReg : 1; 1104 bool isSRet : 1; 1105 bool isNest : 1; 1106 bool isByVal : 1; 1107 uint16_t Alignment; 1108 1109 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1110 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1111 }; 1112 typedef std::vector<ArgListEntry> ArgListTy; 1113 virtual std::pair<SDValue, SDValue> 1114 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1115 bool isVarArg, bool isInreg, unsigned CallingConv, 1116 bool isTailCall, SDValue Callee, ArgListTy &Args, 1117 SelectionDAG &DAG, DebugLoc dl); 1118 1119 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1120 /// memcpy. This can be used by targets to provide code sequences for cases 1121 /// that don't fit the target's parameters for simple loads/stores and can be 1122 /// more efficient than using a library call. This function can return a null 1123 /// SDValue if the target declines to use custom code and a different 1124 /// lowering strategy should be used. 1125 /// 1126 /// If AlwaysInline is true, the size is constant and the target should not 1127 /// emit any calls and is strongly encouraged to attempt to emit inline code 1128 /// even if it is beyond the usual threshold because this intrinsic is being 1129 /// expanded in a place where calls are not feasible (e.g. within the prologue 1130 /// for another call). If the target chooses to decline an AlwaysInline 1131 /// request here, legalize will resort to using simple loads and stores. 1132 virtual SDValue 1133 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1134 SDValue Chain, 1135 SDValue Op1, SDValue Op2, 1136 SDValue Op3, unsigned Align, 1137 bool AlwaysInline, 1138 const Value *DstSV, uint64_t DstOff, 1139 const Value *SrcSV, uint64_t SrcOff) { 1140 return SDValue(); 1141 } 1142 1143 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1144 /// memmove. This can be used by targets to provide code sequences for cases 1145 /// that don't fit the target's parameters for simple loads/stores and can be 1146 /// more efficient than using a library call. This function can return a null 1147 /// SDValue if the target declines to use custom code and a different 1148 /// lowering strategy should be used. 1149 virtual SDValue 1150 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1151 SDValue Chain, 1152 SDValue Op1, SDValue Op2, 1153 SDValue Op3, unsigned Align, 1154 const Value *DstSV, uint64_t DstOff, 1155 const Value *SrcSV, uint64_t SrcOff) { 1156 return SDValue(); 1157 } 1158 1159 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1160 /// memset. This can be used by targets to provide code sequences for cases 1161 /// that don't fit the target's parameters for simple stores and can be more 1162 /// efficient than using a library call. This function can return a null 1163 /// SDValue if the target declines to use custom code and a different 1164 /// lowering strategy should be used. 1165 virtual SDValue 1166 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1167 SDValue Chain, 1168 SDValue Op1, SDValue Op2, 1169 SDValue Op3, unsigned Align, 1170 const Value *DstSV, uint64_t DstOff) { 1171 return SDValue(); 1172 } 1173 1174 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1175 /// to legalize nodes with an illegal operand type but legal result types. 1176 /// It replaces the LowerOperation callback in the type Legalizer. 1177 /// The reason we can not do away with LowerOperation entirely is that 1178 /// LegalizeDAG isn't yet ready to use this callback. 1179 /// TODO: Consider merging with ReplaceNodeResults. 1180 1181 /// The target places new result values for the node in Results (their number 1182 /// and types must exactly match those of the original return values of 1183 /// the node), or leaves Results empty, which indicates that the node is not 1184 /// to be custom lowered after all. 1185 /// The default implementation calls LowerOperation. 1186 virtual void LowerOperationWrapper(SDNode *N, 1187 SmallVectorImpl<SDValue> &Results, 1188 SelectionDAG &DAG); 1189 1190 /// LowerOperation - This callback is invoked for operations that are 1191 /// unsupported by the target, which are registered to use 'custom' lowering, 1192 /// and whose defined values are all legal. 1193 /// If the target has no operations that require custom lowering, it need not 1194 /// implement this. The default implementation of this aborts. 1195 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1196 1197 /// ReplaceNodeResults - This callback is invoked when a node result type is 1198 /// illegal for the target, and the operation was registered to use 'custom' 1199 /// lowering for that result type. The target places new result values for 1200 /// the node in Results (their number and types must exactly match those of 1201 /// the original return values of the node), or leaves Results empty, which 1202 /// indicates that the node is not to be custom lowered after all. 1203 /// 1204 /// If the target has no operations that require custom lowering, it need not 1205 /// implement this. The default implementation aborts. 1206 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1207 SelectionDAG &DAG) { 1208 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1209 } 1210 1211 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1212 /// tail call optimization. Targets which want to do tail call optimization 1213 /// should override this function. 1214 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call, 1215 SDValue Ret, 1216 SelectionDAG &DAG) const { 1217 return false; 1218 } 1219 1220 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly 1221 /// preceeds the RET node and whether the return uses the result of the node 1222 /// or is a void return. This function can be used by the target to determine 1223 /// eligiblity of tail call optimization. 1224 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret); 1225 1226 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1227 /// it exists. Skip a possible ISD::TokenFactor. 1228 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1229 unsigned TailCallNodeOpCode) { 1230 if (Chain.getOpcode() == TailCallNodeOpCode) { 1231 return Chain; 1232 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1233 if (Chain.getNumOperands() && 1234 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1235 return Chain.getOperand(0); 1236 } 1237 return Chain; 1238 } 1239 1240 /// getTargetNodeName() - This method returns the name of a target specific 1241 /// DAG node. 1242 virtual const char *getTargetNodeName(unsigned Opcode) const; 1243 1244 /// createFastISel - This method returns a target specific FastISel object, 1245 /// or null if the target does not support "fast" ISel. 1246 virtual FastISel * 1247 createFastISel(MachineFunction &, 1248 MachineModuleInfo *, DwarfWriter *, 1249 DenseMap<const Value *, unsigned> &, 1250 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1251 DenseMap<const AllocaInst *, int> & 1252#ifndef NDEBUG 1253 , SmallSet<Instruction*, 8> &CatchInfoLost 1254#endif 1255 ) { 1256 return 0; 1257 } 1258 1259 //===--------------------------------------------------------------------===// 1260 // Inline Asm Support hooks 1261 // 1262 1263 enum ConstraintType { 1264 C_Register, // Constraint represents specific register(s). 1265 C_RegisterClass, // Constraint represents any of register(s) in class. 1266 C_Memory, // Memory constraint. 1267 C_Other, // Something else. 1268 C_Unknown // Unsupported constraint. 1269 }; 1270 1271 /// AsmOperandInfo - This contains information for each constraint that we are 1272 /// lowering. 1273 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1274 /// ConstraintCode - This contains the actual string for the code, like "m". 1275 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1276 /// most closely matches the operand. 1277 std::string ConstraintCode; 1278 1279 /// ConstraintType - Information about the constraint code, e.g. Register, 1280 /// RegisterClass, Memory, Other, Unknown. 1281 TargetLowering::ConstraintType ConstraintType; 1282 1283 /// CallOperandval - If this is the result output operand or a 1284 /// clobber, this is null, otherwise it is the incoming operand to the 1285 /// CallInst. This gets modified as the asm is processed. 1286 Value *CallOperandVal; 1287 1288 /// ConstraintVT - The ValueType for the operand value. 1289 MVT ConstraintVT; 1290 1291 /// isMatchingInputConstraint - Return true of this is an input operand that 1292 /// is a matching constraint like "4". 1293 bool isMatchingInputConstraint() const; 1294 1295 /// getMatchedOperand - If this is an input matching constraint, this method 1296 /// returns the output operand it matches. 1297 unsigned getMatchedOperand() const; 1298 1299 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1300 : InlineAsm::ConstraintInfo(info), 1301 ConstraintType(TargetLowering::C_Unknown), 1302 CallOperandVal(0), ConstraintVT(MVT::Other) { 1303 } 1304 }; 1305 1306 /// ComputeConstraintToUse - Determines the constraint code and constraint 1307 /// type to use for the specific AsmOperandInfo, setting 1308 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1309 /// being passed in is available, it can be passed in as Op, otherwise an 1310 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1311 /// constraint of the inline asm instruction being processed is 'm'. 1312 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1313 SDValue Op, 1314 bool hasMemory, 1315 SelectionDAG *DAG = 0) const; 1316 1317 /// getConstraintType - Given a constraint, return the type of constraint it 1318 /// is for this target. 1319 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1320 1321 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1322 /// return a list of registers that can be used to satisfy the constraint. 1323 /// This should only be used for C_RegisterClass constraints. 1324 virtual std::vector<unsigned> 1325 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1326 MVT VT) const; 1327 1328 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1329 /// {edx}), return the register number and the register class for the 1330 /// register. 1331 /// 1332 /// Given a register class constraint, like 'r', if this corresponds directly 1333 /// to an LLVM register class, return a register of 0 and the register class 1334 /// pointer. 1335 /// 1336 /// This should only be used for C_Register constraints. On error, 1337 /// this returns a register number of 0 and a null register class pointer.. 1338 virtual std::pair<unsigned, const TargetRegisterClass*> 1339 getRegForInlineAsmConstraint(const std::string &Constraint, 1340 MVT VT) const; 1341 1342 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1343 /// with another that has more specific requirements based on the type of the 1344 /// corresponding operand. This returns null if there is no replacement to 1345 /// make. 1346 virtual const char *LowerXConstraint(MVT ConstraintVT) const; 1347 1348 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1349 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1350 /// it means one of the asm constraint of the inline asm instruction being 1351 /// processed is 'm'. 1352 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1353 bool hasMemory, 1354 std::vector<SDValue> &Ops, 1355 SelectionDAG &DAG) const; 1356 1357 //===--------------------------------------------------------------------===// 1358 // Scheduler hooks 1359 // 1360 1361 // EmitInstrWithCustomInserter - This method should be implemented by targets 1362 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1363 // instructions are special in various ways, which require special support to 1364 // insert. The specified MachineInstr is created but not inserted into any 1365 // basic blocks, and the scheduler passes ownership of it to this method. 1366 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1367 MachineBasicBlock *MBB) const; 1368 1369 //===--------------------------------------------------------------------===// 1370 // Addressing mode description hooks (used by LSR etc). 1371 // 1372 1373 /// AddrMode - This represents an addressing mode of: 1374 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1375 /// If BaseGV is null, there is no BaseGV. 1376 /// If BaseOffs is zero, there is no base offset. 1377 /// If HasBaseReg is false, there is no base register. 1378 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1379 /// no scale. 1380 /// 1381 struct AddrMode { 1382 GlobalValue *BaseGV; 1383 int64_t BaseOffs; 1384 bool HasBaseReg; 1385 int64_t Scale; 1386 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1387 }; 1388 1389 /// isLegalAddressingMode - Return true if the addressing mode represented by 1390 /// AM is legal for this target, for a load/store of the specified type. 1391 /// The type may be VoidTy, in which case only return true if the addressing 1392 /// mode is legal for a load/store of any legal type. 1393 /// TODO: Handle pre/postinc as well. 1394 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1395 1396 /// isTruncateFree - Return true if it's free to truncate a value of 1397 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1398 /// register EAX to i16 by referencing its sub-register AX. 1399 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1400 return false; 1401 } 1402 1403 virtual bool isTruncateFree(MVT VT1, MVT VT2) const { 1404 return false; 1405 } 1406 1407 /// isZExtFree - Return true if any actual instruction that defines a 1408 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 1409 /// register. This does not necessarily include registers defined in 1410 /// unknown ways, such as incoming arguments, or copies from unknown 1411 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1412 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1413 /// all instructions that define 32-bit values implicit zero-extend the 1414 /// result out to 64 bits. 1415 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1416 return false; 1417 } 1418 1419 virtual bool isZExtFree(MVT VT1, MVT VT2) const { 1420 return false; 1421 } 1422 1423 /// isNarrowingProfitable - Return true if it's profitable to narrow 1424 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1425 /// from i32 to i8 but not from i32 to i16. 1426 virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const { 1427 return true; 1428 } 1429 1430 //===--------------------------------------------------------------------===// 1431 // Div utility functions 1432 // 1433 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1434 std::vector<SDNode*>* Created) const; 1435 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1436 std::vector<SDNode*>* Created) const; 1437 1438 1439 //===--------------------------------------------------------------------===// 1440 // Runtime Library hooks 1441 // 1442 1443 /// setLibcallName - Rename the default libcall routine name for the specified 1444 /// libcall. 1445 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1446 LibcallRoutineNames[Call] = Name; 1447 } 1448 1449 /// getLibcallName - Get the libcall routine name for the specified libcall. 1450 /// 1451 const char *getLibcallName(RTLIB::Libcall Call) const { 1452 return LibcallRoutineNames[Call]; 1453 } 1454 1455 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1456 /// result of the comparison libcall against zero. 1457 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1458 CmpLibcallCCs[Call] = CC; 1459 } 1460 1461 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1462 /// the comparison libcall against zero. 1463 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1464 return CmpLibcallCCs[Call]; 1465 } 1466 1467private: 1468 TargetMachine &TM; 1469 const TargetData *TD; 1470 1471 /// PointerTy - The type to use for pointers, usually i32 or i64. 1472 /// 1473 MVT PointerTy; 1474 1475 /// IsLittleEndian - True if this is a little endian target. 1476 /// 1477 bool IsLittleEndian; 1478 1479 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1480 /// 1481 bool UsesGlobalOffsetTable; 1482 1483 /// SelectIsExpensive - Tells the code generator not to expand operations 1484 /// into sequences that use the select operations if possible. 1485 bool SelectIsExpensive; 1486 1487 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1488 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1489 /// a real cost model is in place. If we ever optimize for size, this will be 1490 /// set to true unconditionally. 1491 bool IntDivIsCheap; 1492 1493 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1494 /// srl/add/sra for a signed divide by power of two, and let the target handle 1495 /// it. 1496 bool Pow2DivIsCheap; 1497 1498 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1499 /// llvm.setjmp. Defaults to false. 1500 bool UseUnderscoreSetJmp; 1501 1502 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1503 /// llvm.longjmp. Defaults to false. 1504 bool UseUnderscoreLongJmp; 1505 1506 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1507 /// PointerTy is. 1508 MVT ShiftAmountTy; 1509 1510 OutOfRangeShiftAmount ShiftAmtHandling; 1511 1512 /// BooleanContents - Information about the contents of the high-bits in 1513 /// boolean values held in a type wider than i1. See getBooleanContents. 1514 BooleanContent BooleanContents; 1515 1516 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1517 /// total cycles or lowest register usage. 1518 SchedPreference SchedPreferenceInfo; 1519 1520 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1521 unsigned JumpBufSize; 1522 1523 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1524 /// buffers 1525 unsigned JumpBufAlignment; 1526 1527 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1528 /// if-converted. 1529 unsigned IfCvtBlockSizeLimit; 1530 1531 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1532 /// duplicated during if-conversion. 1533 unsigned IfCvtDupBlockSizeLimit; 1534 1535 /// PrefLoopAlignment - The perferred loop alignment. 1536 /// 1537 unsigned PrefLoopAlignment; 1538 1539 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1540 /// specifies the register that llvm.savestack/llvm.restorestack should save 1541 /// and restore. 1542 unsigned StackPointerRegisterToSaveRestore; 1543 1544 /// ExceptionPointerRegister - If set to a physical register, this specifies 1545 /// the register that receives the exception address on entry to a landing 1546 /// pad. 1547 unsigned ExceptionPointerRegister; 1548 1549 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1550 /// the register that receives the exception typeid on entry to a landing 1551 /// pad. 1552 unsigned ExceptionSelectorRegister; 1553 1554 /// RegClassForVT - This indicates the default register class to use for 1555 /// each ValueType the target supports natively. 1556 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1557 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1558 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1559 1560 /// TransformToType - For any value types we are promoting or expanding, this 1561 /// contains the value type that we are changing to. For Expanded types, this 1562 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1563 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1564 /// by the system, this holds the same type (e.g. i32 -> i32). 1565 MVT TransformToType[MVT::LAST_VALUETYPE]; 1566 1567 /// OpActions - For each operation and each value type, keep a LegalizeAction 1568 /// that indicates how instruction selection should deal with the operation. 1569 /// Most operations are Legal (aka, supported natively by the target), but 1570 /// operations that are not should be described. Note that operations on 1571 /// non-legal value types are not described here. 1572 uint64_t OpActions[ISD::BUILTIN_OP_END]; 1573 1574 /// LoadExtActions - For each load of load extension type and each value type, 1575 /// keep a LegalizeAction that indicates how instruction selection should deal 1576 /// with the load. 1577 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1578 1579 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1580 /// indicates how instruction selection should deal with the store. 1581 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1582 1583 /// IndexedModeActions - For each indexed mode and each value type, keep a 1584 /// pair of LegalizeAction that indicates how instruction selection should 1585 /// deal with the load / store. 1586 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1587 1588 /// ConvertActions - For each conversion from source type to destination type, 1589 /// keep a LegalizeAction that indicates how instruction selection should 1590 /// deal with the conversion. 1591 /// Currently, this is used only for floating->floating conversions 1592 /// (FP_EXTEND and FP_ROUND). 1593 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1594 1595 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1596 /// LegalizeAction that indicates how instruction selection should 1597 /// deal with the condition code. 1598 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1599 1600 ValueTypeActionImpl ValueTypeActions; 1601 1602 std::vector<APFloat> LegalFPImmediates; 1603 1604 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses; 1605 1606 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1607 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1608 /// which sets a bit in this array. 1609 unsigned char 1610 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1611 1612 /// PromoteToType - For operations that must be promoted to a specific type, 1613 /// this holds the destination type. This map should be sparse, so don't hold 1614 /// it as an array. 1615 /// 1616 /// Targets add entries to this map with AddPromotedToType(..), clients access 1617 /// this with getTypeToPromoteTo(..). 1618 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1619 PromoteToType; 1620 1621 /// LibcallRoutineNames - Stores the name each libcall. 1622 /// 1623 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1624 1625 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1626 /// of each of the comparison libcall against zero. 1627 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1628 1629protected: 1630 /// When lowering \@llvm.memset this field specifies the maximum number of 1631 /// store operations that may be substituted for the call to memset. Targets 1632 /// must set this value based on the cost threshold for that target. Targets 1633 /// should assume that the memset will be done using as many of the largest 1634 /// store operations first, followed by smaller ones, if necessary, per 1635 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1636 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1637 /// store. This only applies to setting a constant array of a constant size. 1638 /// @brief Specify maximum number of store instructions per memset call. 1639 unsigned maxStoresPerMemset; 1640 1641 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1642 /// store operations that may be substituted for a call to memcpy. Targets 1643 /// must set this value based on the cost threshold for that target. Targets 1644 /// should assume that the memcpy will be done using as many of the largest 1645 /// store operations first, followed by smaller ones, if necessary, per 1646 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1647 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1648 /// and one 1-byte store. This only applies to copying a constant array of 1649 /// constant size. 1650 /// @brief Specify maximum bytes of store instructions per memcpy call. 1651 unsigned maxStoresPerMemcpy; 1652 1653 /// When lowering \@llvm.memmove this field specifies the maximum number of 1654 /// store instructions that may be substituted for a call to memmove. Targets 1655 /// must set this value based on the cost threshold for that target. Targets 1656 /// should assume that the memmove will be done using as many of the largest 1657 /// store operations first, followed by smaller ones, if necessary, per 1658 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1659 /// with 8-bit alignment would result in nine 1-byte stores. This only 1660 /// applies to copying a constant array of constant size. 1661 /// @brief Specify maximum bytes of store instructions per memmove call. 1662 unsigned maxStoresPerMemmove; 1663 1664 /// This field specifies whether the target machine permits unaligned memory 1665 /// accesses. This is used, for example, to determine the size of store 1666 /// operations when copying small arrays and other similar tasks. 1667 /// @brief Indicate whether the target permits unaligned memory accesses. 1668 bool allowUnalignedMemoryAccesses; 1669 1670 /// This field specifies whether the target can benefit from code placement 1671 /// optimization. 1672 bool benefitFromCodePlacementOpt; 1673}; 1674} // end llvm namespace 1675 1676#endif 1677