TargetLowering.h revision 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include "llvm/ADT/APFloat.h" 28#include "llvm/ADT/STLExtras.h" 29#include <map> 30#include <vector> 31 32namespace llvm { 33 class Value; 34 class Function; 35 class TargetMachine; 36 class TargetData; 37 class TargetRegisterClass; 38 class SDNode; 39 class SDOperand; 40 class SelectionDAG; 41 class MachineBasicBlock; 42 class MachineInstr; 43 class VectorType; 44 class TargetSubtarget; 45 46//===----------------------------------------------------------------------===// 47/// TargetLowering - This class defines information used to lower LLVM code to 48/// legal SelectionDAG operators that the target instruction selector can accept 49/// natively. 50/// 51/// This class also defines callbacks that targets must implement to lower 52/// target-specific constructs to SelectionDAG operators. 53/// 54class TargetLowering { 55public: 56 /// LegalizeAction - This enum indicates whether operations are valid for a 57 /// target, and if not, what action should be used to make them valid. 58 enum LegalizeAction { 59 Legal, // The target natively supports this operation. 60 Promote, // This operation should be executed in a larger type. 61 Expand, // Try to expand this to other ops, otherwise use a libcall. 62 Custom // Use the LowerOperation hook to implement custom lowering. 63 }; 64 65 enum OutOfRangeShiftAmount { 66 Undefined, // Oversized shift amounts are undefined (default). 67 Mask, // Shift amounts are auto masked (anded) to value size. 68 Extend // Oversized shift pulls in zeros or sign bits. 69 }; 70 71 enum SetCCResultValue { 72 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 73 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 74 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 75 }; 76 77 enum SchedPreference { 78 SchedulingForLatency, // Scheduling for shortest total latency. 79 SchedulingForRegPressure // Scheduling for lowest register pressure. 80 }; 81 82 explicit TargetLowering(TargetMachine &TM); 83 virtual ~TargetLowering(); 84 85 TargetMachine &getTargetMachine() const { return TM; } 86 const TargetData *getTargetData() const { return TD; } 87 88 bool isBigEndian() const { return !IsLittleEndian; } 89 bool isLittleEndian() const { return IsLittleEndian; } 90 MVT::ValueType getPointerTy() const { return PointerTy; } 91 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 92 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 93 94 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 95 /// codegen. 96 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 97 98 /// isSelectExpensive - Return true if the select operation is expensive for 99 /// this target. 100 bool isSelectExpensive() const { return SelectIsExpensive; } 101 102 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 103 /// a sequence of several shifts, adds, and multiplies for this target. 104 bool isIntDivCheap() const { return IntDivIsCheap; } 105 106 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 107 /// srl/add/sra. 108 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 109 110 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 111 /// 112 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 113 114 /// getSetCCResultContents - For targets without boolean registers, this flag 115 /// returns information about the contents of the high-bits in the setcc 116 /// result register. 117 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 118 119 /// getSchedulingPreference - Return target scheduling preference. 120 SchedPreference getSchedulingPreference() const { 121 return SchedPreferenceInfo; 122 } 123 124 /// getRegClassFor - Return the register class that should be used for the 125 /// specified value type. This may only be called on legal types. 126 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 127 assert(VT < array_lengthof(RegClassForVT)); 128 TargetRegisterClass *RC = RegClassForVT[VT]; 129 assert(RC && "This value type is not natively supported!"); 130 return RC; 131 } 132 133 /// isTypeLegal - Return true if the target has native support for the 134 /// specified value type. This means that it has a register that directly 135 /// holds it without promotions or expansions. 136 bool isTypeLegal(MVT::ValueType VT) const { 137 assert(MVT::isExtendedVT(VT) || VT < array_lengthof(RegClassForVT)); 138 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; 139 } 140 141 class ValueTypeActionImpl { 142 /// ValueTypeActions - This is a bitvector that contains two bits for each 143 /// value type, where the two bits correspond to the LegalizeAction enum. 144 /// This can be queried with "getTypeAction(VT)". 145 uint32_t ValueTypeActions[2]; 146 public: 147 ValueTypeActionImpl() { 148 ValueTypeActions[0] = ValueTypeActions[1] = 0; 149 } 150 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 151 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 152 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 153 } 154 155 LegalizeAction getTypeAction(MVT::ValueType VT) const { 156 if (MVT::isExtendedVT(VT)) { 157 if (MVT::isVector(VT)) return Expand; 158 if (MVT::isInteger(VT)) 159 // First promote to a power-of-two size, then expand if necessary. 160 return VT == MVT::RoundIntegerType(VT) ? Expand : Promote; 161 assert(0 && "Unsupported extended type!"); 162 } 163 assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 164 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 165 } 166 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 167 assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 168 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 169 } 170 }; 171 172 const ValueTypeActionImpl &getValueTypeActions() const { 173 return ValueTypeActions; 174 } 175 176 /// getTypeAction - Return how we should legalize values of this type, either 177 /// it is already legal (return 'Legal') or we need to promote it to a larger 178 /// type (return 'Promote'), or we need to expand it into multiple registers 179 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 180 LegalizeAction getTypeAction(MVT::ValueType VT) const { 181 return ValueTypeActions.getTypeAction(VT); 182 } 183 184 /// getTypeToTransformTo - For types supported by the target, this is an 185 /// identity function. For types that must be promoted to larger types, this 186 /// returns the larger type to promote to. For integer types that are larger 187 /// than the largest integer register, this contains one step in the expansion 188 /// to get to the smaller register. For illegal floating point types, this 189 /// returns the integer type to transform to. 190 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 191 if (!MVT::isExtendedVT(VT)) { 192 assert(VT < array_lengthof(TransformToType)); 193 MVT::ValueType NVT = TransformToType[VT]; 194 assert(getTypeAction(NVT) != Promote && 195 "Promote may not follow Expand or Promote"); 196 return NVT; 197 } 198 199 if (MVT::isVector(VT)) 200 return MVT::getVectorType(MVT::getVectorElementType(VT), 201 MVT::getVectorNumElements(VT) / 2); 202 if (MVT::isInteger(VT)) { 203 MVT::ValueType NVT = MVT::RoundIntegerType(VT); 204 if (NVT == VT) 205 // Size is a power of two - expand to half the size. 206 return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2); 207 else 208 // Promote to a power of two size, avoiding multi-step promotion. 209 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 210 } 211 assert(0 && "Unsupported extended type!"); 212 } 213 214 /// getTypeToExpandTo - For types supported by the target, this is an 215 /// identity function. For types that must be expanded (i.e. integer types 216 /// that are larger than the largest integer register or illegal floating 217 /// point types), this returns the largest legal type it will be expanded to. 218 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 219 assert(!MVT::isVector(VT)); 220 while (true) { 221 switch (getTypeAction(VT)) { 222 case Legal: 223 return VT; 224 case Expand: 225 VT = getTypeToTransformTo(VT); 226 break; 227 default: 228 assert(false && "Type is not legal nor is it to be expanded!"); 229 return VT; 230 } 231 } 232 return VT; 233 } 234 235 /// getVectorTypeBreakdown - Vector types are broken down into some number of 236 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 237 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 238 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 239 /// 240 /// This method returns the number of registers needed, and the VT for each 241 /// register. It also returns the VT and quantity of the intermediate values 242 /// before they are promoted/expanded. 243 /// 244 unsigned getVectorTypeBreakdown(MVT::ValueType VT, 245 MVT::ValueType &IntermediateVT, 246 unsigned &NumIntermediates, 247 MVT::ValueType &RegisterVT) const; 248 249 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 250 legal_fpimm_iterator legal_fpimm_begin() const { 251 return LegalFPImmediates.begin(); 252 } 253 legal_fpimm_iterator legal_fpimm_end() const { 254 return LegalFPImmediates.end(); 255 } 256 257 /// isShuffleMaskLegal - Targets can use this to indicate that they only 258 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 259 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 260 /// are assumed to be legal. 261 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 262 return true; 263 } 264 265 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 266 /// used by Targets can use this to indicate if there is a suitable 267 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 268 /// pool entry. 269 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 270 MVT::ValueType EVT, 271 SelectionDAG &DAG) const { 272 return false; 273 } 274 275 /// getOperationAction - Return how this operation should be treated: either 276 /// it is legal, needs to be promoted to a larger size, needs to be 277 /// expanded to some other code sequence, or the target has a custom expander 278 /// for it. 279 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 280 if (MVT::isExtendedVT(VT)) return Expand; 281 assert(Op < array_lengthof(OpActions) && 282 VT < sizeof(OpActions[0])*4 && "Table isn't big enough!"); 283 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 284 } 285 286 /// isOperationLegal - Return true if the specified operation is legal on this 287 /// target. 288 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 289 return getOperationAction(Op, VT) == Legal || 290 getOperationAction(Op, VT) == Custom; 291 } 292 293 /// getLoadXAction - Return how this load with extension should be treated: 294 /// either it is legal, needs to be promoted to a larger size, needs to be 295 /// expanded to some other code sequence, or the target has a custom expander 296 /// for it. 297 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 298 assert(LType < array_lengthof(LoadXActions) && 299 VT < sizeof(LoadXActions[0])*4 && "Table isn't big enough!"); 300 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); 301 } 302 303 /// isLoadXLegal - Return true if the specified load with extension is legal 304 /// on this target. 305 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 306 return !MVT::isExtendedVT(VT) && 307 (getLoadXAction(LType, VT) == Legal || 308 getLoadXAction(LType, VT) == Custom); 309 } 310 311 /// getTruncStoreAction - Return how this store with truncation should be 312 /// treated: either it is legal, needs to be promoted to a larger size, needs 313 /// to be expanded to some other code sequence, or the target has a custom 314 /// expander for it. 315 LegalizeAction getTruncStoreAction(MVT::ValueType ValVT, 316 MVT::ValueType MemVT) const { 317 assert(ValVT < array_lengthof(TruncStoreActions) && 318 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!"); 319 return (LegalizeAction)((TruncStoreActions[ValVT] >> (2*MemVT)) & 3); 320 } 321 322 /// isTruncStoreLegal - Return true if the specified store with truncation is 323 /// legal on this target. 324 bool isTruncStoreLegal(MVT::ValueType ValVT, MVT::ValueType MemVT) const { 325 return !MVT::isExtendedVT(MemVT) && 326 (getTruncStoreAction(ValVT, MemVT) == Legal || 327 getTruncStoreAction(ValVT, MemVT) == Custom); 328 } 329 330 /// getIndexedLoadAction - Return how the indexed load should be treated: 331 /// either it is legal, needs to be promoted to a larger size, needs to be 332 /// expanded to some other code sequence, or the target has a custom expander 333 /// for it. 334 LegalizeAction 335 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 336 assert(IdxMode < array_lengthof(IndexedModeActions[0]) && 337 VT < sizeof(IndexedModeActions[0][0])*4 && 338 "Table isn't big enough!"); 339 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); 340 } 341 342 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 343 /// on this target. 344 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 345 return getIndexedLoadAction(IdxMode, VT) == Legal || 346 getIndexedLoadAction(IdxMode, VT) == Custom; 347 } 348 349 /// getIndexedStoreAction - Return how the indexed store should be treated: 350 /// either it is legal, needs to be promoted to a larger size, needs to be 351 /// expanded to some other code sequence, or the target has a custom expander 352 /// for it. 353 LegalizeAction 354 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 355 assert(IdxMode < array_lengthof(IndexedModeActions[1]) && 356 VT < sizeof(IndexedModeActions[1][0])*4 && 357 "Table isn't big enough!"); 358 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); 359 } 360 361 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 362 /// on this target. 363 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 364 return getIndexedStoreAction(IdxMode, VT) == Legal || 365 getIndexedStoreAction(IdxMode, VT) == Custom; 366 } 367 368 /// getConvertAction - Return how the conversion should be treated: 369 /// either it is legal, needs to be promoted to a larger size, needs to be 370 /// expanded to some other code sequence, or the target has a custom expander 371 /// for it. 372 LegalizeAction 373 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 374 assert(FromVT < array_lengthof(ConvertActions) && 375 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!"); 376 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3); 377 } 378 379 /// isConvertLegal - Return true if the specified conversion is legal 380 /// on this target. 381 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 382 return getConvertAction(FromVT, ToVT) == Legal || 383 getConvertAction(FromVT, ToVT) == Custom; 384 } 385 386 /// getTypeToPromoteTo - If the action for this operation is to promote, this 387 /// method returns the ValueType to promote to. 388 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 389 assert(getOperationAction(Op, VT) == Promote && 390 "This operation isn't promoted!"); 391 392 // See if this has an explicit type specified. 393 std::map<std::pair<unsigned, MVT::ValueType>, 394 MVT::ValueType>::const_iterator PTTI = 395 PromoteToType.find(std::make_pair(Op, VT)); 396 if (PTTI != PromoteToType.end()) return PTTI->second; 397 398 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 399 "Cannot autopromote this type, add it with AddPromotedToType."); 400 401 MVT::ValueType NVT = VT; 402 do { 403 NVT = (MVT::ValueType)(NVT+1); 404 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 405 "Didn't find type to promote to!"); 406 } while (!isTypeLegal(NVT) || 407 getOperationAction(Op, NVT) == Promote); 408 return NVT; 409 } 410 411 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 412 /// This is fixed by the LLVM operations except for the pointer size. If 413 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 414 /// counterpart (e.g. structs), otherwise it will assert. 415 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { 416 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); 417 return VT == MVT::iPTR ? PointerTy : VT; 418 } 419 420 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 421 /// function arguments in the caller parameter area. 422 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 423 424 /// getRegisterType - Return the type of registers that this ValueType will 425 /// eventually require. 426 MVT::ValueType getRegisterType(MVT::ValueType VT) const { 427 if (!MVT::isExtendedVT(VT)) { 428 assert(VT < array_lengthof(RegisterTypeForVT)); 429 return RegisterTypeForVT[VT]; 430 } 431 if (MVT::isVector(VT)) { 432 MVT::ValueType VT1, RegisterVT; 433 unsigned NumIntermediates; 434 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 435 return RegisterVT; 436 } 437 if (MVT::isInteger(VT)) { 438 return getRegisterType(getTypeToTransformTo(VT)); 439 } 440 assert(0 && "Unsupported extended type!"); 441 } 442 443 /// getNumRegisters - Return the number of registers that this ValueType will 444 /// eventually require. This is one for any types promoted to live in larger 445 /// registers, but may be more than one for types (like i64) that are split 446 /// into pieces. For types like i140, which are first promoted then expanded, 447 /// it is the number of registers needed to hold all the bits of the original 448 /// type. For an i140 on a 32 bit machine this means 5 registers. 449 unsigned getNumRegisters(MVT::ValueType VT) const { 450 if (!MVT::isExtendedVT(VT)) { 451 assert(VT < array_lengthof(NumRegistersForVT)); 452 return NumRegistersForVT[VT]; 453 } 454 if (MVT::isVector(VT)) { 455 MVT::ValueType VT1, VT2; 456 unsigned NumIntermediates; 457 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 458 } 459 if (MVT::isInteger(VT)) { 460 unsigned BitWidth = MVT::getSizeInBits(VT); 461 unsigned RegWidth = MVT::getSizeInBits(getRegisterType(VT)); 462 return (BitWidth + RegWidth - 1) / RegWidth; 463 } 464 assert(0 && "Unsupported extended type!"); 465 } 466 467 /// hasTargetDAGCombine - If true, the target has custom DAG combine 468 /// transformations that it can perform for the specified node. 469 bool hasTargetDAGCombine(ISD::NodeType NT) const { 470 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 471 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 472 } 473 474 /// This function returns the maximum number of store operations permitted 475 /// to replace a call to llvm.memset. The value is set by the target at the 476 /// performance threshold for such a replacement. 477 /// @brief Get maximum # of store operations permitted for llvm.memset 478 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 479 480 /// This function returns the maximum number of store operations permitted 481 /// to replace a call to llvm.memcpy. The value is set by the target at the 482 /// performance threshold for such a replacement. 483 /// @brief Get maximum # of store operations permitted for llvm.memcpy 484 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 485 486 /// This function returns the maximum number of store operations permitted 487 /// to replace a call to llvm.memmove. The value is set by the target at the 488 /// performance threshold for such a replacement. 489 /// @brief Get maximum # of store operations permitted for llvm.memmove 490 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 491 492 /// This function returns true if the target allows unaligned memory accesses. 493 /// This is used, for example, in situations where an array copy/move/set is 494 /// converted to a sequence of store operations. It's use helps to ensure that 495 /// such replacements don't generate code that causes an alignment error 496 /// (trap) on the target machine. 497 /// @brief Determine if the target supports unaligned memory accesses. 498 bool allowsUnalignedMemoryAccesses() const { 499 return allowUnalignedMemoryAccesses; 500 } 501 502 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 503 /// to implement llvm.setjmp. 504 bool usesUnderscoreSetJmp() const { 505 return UseUnderscoreSetJmp; 506 } 507 508 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 509 /// to implement llvm.longjmp. 510 bool usesUnderscoreLongJmp() const { 511 return UseUnderscoreLongJmp; 512 } 513 514 /// getStackPointerRegisterToSaveRestore - If a physical register, this 515 /// specifies the register that llvm.savestack/llvm.restorestack should save 516 /// and restore. 517 unsigned getStackPointerRegisterToSaveRestore() const { 518 return StackPointerRegisterToSaveRestore; 519 } 520 521 /// getExceptionAddressRegister - If a physical register, this returns 522 /// the register that receives the exception address on entry to a landing 523 /// pad. 524 unsigned getExceptionAddressRegister() const { 525 return ExceptionPointerRegister; 526 } 527 528 /// getExceptionSelectorRegister - If a physical register, this returns 529 /// the register that receives the exception typeid on entry to a landing 530 /// pad. 531 unsigned getExceptionSelectorRegister() const { 532 return ExceptionSelectorRegister; 533 } 534 535 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 536 /// set, the default is 200) 537 unsigned getJumpBufSize() const { 538 return JumpBufSize; 539 } 540 541 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 542 /// (if never set, the default is 0) 543 unsigned getJumpBufAlignment() const { 544 return JumpBufAlignment; 545 } 546 547 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 548 /// limit. Any block whose size is greater should not be predicated. 549 virtual unsigned getIfCvtBlockSizeLimit() const { 550 return IfCvtBlockSizeLimit; 551 } 552 553 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 554 /// block to be considered for duplication. Any block whose size is greater 555 /// should not be duplicated to facilitate its predication. 556 virtual unsigned getIfCvtDupBlockSizeLimit() const { 557 return IfCvtDupBlockSizeLimit; 558 } 559 560 /// getPreIndexedAddressParts - returns true by value, base pointer and 561 /// offset pointer and addressing mode by reference if the node's address 562 /// can be legally represented as pre-indexed load / store address. 563 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 564 SDOperand &Offset, 565 ISD::MemIndexedMode &AM, 566 SelectionDAG &DAG) { 567 return false; 568 } 569 570 /// getPostIndexedAddressParts - returns true by value, base pointer and 571 /// offset pointer and addressing mode by reference if this node can be 572 /// combined with a load / store to form a post-indexed load / store. 573 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 574 SDOperand &Base, SDOperand &Offset, 575 ISD::MemIndexedMode &AM, 576 SelectionDAG &DAG) { 577 return false; 578 } 579 580 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 581 /// jumptable. 582 virtual SDOperand getPICJumpTableRelocBase(SDOperand Table, 583 SelectionDAG &DAG) const; 584 585 //===--------------------------------------------------------------------===// 586 // TargetLowering Optimization Methods 587 // 588 589 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 590 /// SDOperands for returning information from TargetLowering to its clients 591 /// that want to combine 592 struct TargetLoweringOpt { 593 SelectionDAG &DAG; 594 bool AfterLegalize; 595 SDOperand Old; 596 SDOperand New; 597 598 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize) 599 : DAG(InDAG), AfterLegalize(afterLegalize) {} 600 601 bool CombineTo(SDOperand O, SDOperand N) { 602 Old = O; 603 New = N; 604 return true; 605 } 606 607 /// ShrinkDemandedConstant - Check to see if the specified operand of the 608 /// specified instruction is a constant integer. If so, check to see if 609 /// there are any bits set in the constant that are not demanded. If so, 610 /// shrink the constant and return true. 611 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 612 }; 613 614 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 615 /// DemandedMask bits of the result of Op are ever used downstream. If we can 616 /// use this information to simplify Op, create a new simplified DAG node and 617 /// return true, returning the original and new nodes in Old and New. 618 /// Otherwise, analyze the expression and return a mask of KnownOne and 619 /// KnownZero bits for the expression (used to simplify the caller). 620 /// The KnownZero/One bits may only be accurate for those bits in the 621 /// DemandedMask. 622 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 623 uint64_t &KnownZero, uint64_t &KnownOne, 624 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 625 626 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 627 /// Mask are known to be either zero or one and return them in the 628 /// KnownZero/KnownOne bitsets. 629 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 630 const APInt &Mask, 631 APInt &KnownZero, 632 APInt &KnownOne, 633 const SelectionDAG &DAG, 634 unsigned Depth = 0) const; 635 636 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 637 /// targets that want to expose additional information about sign bits to the 638 /// DAG Combiner. 639 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 640 unsigned Depth = 0) const; 641 642 struct DAGCombinerInfo { 643 void *DC; // The DAG Combiner object. 644 bool BeforeLegalize; 645 bool CalledByLegalizer; 646 public: 647 SelectionDAG &DAG; 648 649 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 650 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 651 652 bool isBeforeLegalize() const { return BeforeLegalize; } 653 bool isCalledByLegalizer() const { return CalledByLegalizer; } 654 655 void AddToWorklist(SDNode *N); 656 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 657 SDOperand CombineTo(SDNode *N, SDOperand Res); 658 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 659 }; 660 661 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 662 /// and cc. If it is unable to simplify it, return a null SDOperand. 663 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 664 ISD::CondCode Cond, bool foldBooleans, 665 DAGCombinerInfo &DCI) const; 666 667 /// PerformDAGCombine - This method will be invoked for all target nodes and 668 /// for any target-independent nodes that the target has registered with 669 /// invoke it for. 670 /// 671 /// The semantics are as follows: 672 /// Return Value: 673 /// SDOperand.Val == 0 - No change was made 674 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 675 /// otherwise - N should be replaced by the returned Operand. 676 /// 677 /// In addition, methods provided by DAGCombinerInfo may be used to perform 678 /// more complex transformations. 679 /// 680 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 681 682 //===--------------------------------------------------------------------===// 683 // TargetLowering Configuration Methods - These methods should be invoked by 684 // the derived class constructor to configure this object for the target. 685 // 686 687protected: 688 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 689 /// GOT for PC-relative code. 690 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 691 692 /// setShiftAmountType - Describe the type that should be used for shift 693 /// amounts. This type defaults to the pointer type. 694 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 695 696 /// setSetCCResultType - Describe the type that shoudl be used as the result 697 /// of a setcc operation. This defaults to the pointer type. 698 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 699 700 /// setSetCCResultContents - Specify how the target extends the result of a 701 /// setcc operation in a register. 702 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 703 704 /// setSchedulingPreference - Specify the target scheduling preference. 705 void setSchedulingPreference(SchedPreference Pref) { 706 SchedPreferenceInfo = Pref; 707 } 708 709 /// setShiftAmountFlavor - Describe how the target handles out of range shift 710 /// amounts. 711 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 712 ShiftAmtHandling = OORSA; 713 } 714 715 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 716 /// use _setjmp to implement llvm.setjmp or the non _ version. 717 /// Defaults to false. 718 void setUseUnderscoreSetJmp(bool Val) { 719 UseUnderscoreSetJmp = Val; 720 } 721 722 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 723 /// use _longjmp to implement llvm.longjmp or the non _ version. 724 /// Defaults to false. 725 void setUseUnderscoreLongJmp(bool Val) { 726 UseUnderscoreLongJmp = Val; 727 } 728 729 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 730 /// specifies the register that llvm.savestack/llvm.restorestack should save 731 /// and restore. 732 void setStackPointerRegisterToSaveRestore(unsigned R) { 733 StackPointerRegisterToSaveRestore = R; 734 } 735 736 /// setExceptionPointerRegister - If set to a physical register, this sets 737 /// the register that receives the exception address on entry to a landing 738 /// pad. 739 void setExceptionPointerRegister(unsigned R) { 740 ExceptionPointerRegister = R; 741 } 742 743 /// setExceptionSelectorRegister - If set to a physical register, this sets 744 /// the register that receives the exception typeid on entry to a landing 745 /// pad. 746 void setExceptionSelectorRegister(unsigned R) { 747 ExceptionSelectorRegister = R; 748 } 749 750 /// SelectIsExpensive - Tells the code generator not to expand operations 751 /// into sequences that use the select operations if possible. 752 void setSelectIsExpensive() { SelectIsExpensive = true; } 753 754 /// setIntDivIsCheap - Tells the code generator that integer divide is 755 /// expensive, and if possible, should be replaced by an alternate sequence 756 /// of instructions not containing an integer divide. 757 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 758 759 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 760 /// srl/add/sra for a signed divide by power of two, and let the target handle 761 /// it. 762 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 763 764 /// addRegisterClass - Add the specified register class as an available 765 /// regclass for the specified value type. This indicates the selector can 766 /// handle values of that class natively. 767 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 768 assert(VT < array_lengthof(RegClassForVT)); 769 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 770 RegClassForVT[VT] = RC; 771 } 772 773 /// computeRegisterProperties - Once all of the register classes are added, 774 /// this allows us to compute derived properties we expose. 775 void computeRegisterProperties(); 776 777 /// setOperationAction - Indicate that the specified operation does not work 778 /// with the specified type and indicate what to do about it. 779 void setOperationAction(unsigned Op, MVT::ValueType VT, 780 LegalizeAction Action) { 781 assert(VT < sizeof(OpActions[0])*4 && Op < array_lengthof(OpActions) && 782 "Table isn't big enough!"); 783 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 784 OpActions[Op] |= (uint64_t)Action << VT*2; 785 } 786 787 /// setLoadXAction - Indicate that the specified load with extension does not 788 /// work with the with specified type and indicate what to do about it. 789 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 790 LegalizeAction Action) { 791 assert(VT < sizeof(LoadXActions[0])*4 && 792 ExtType < array_lengthof(LoadXActions) && 793 "Table isn't big enough!"); 794 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 795 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 796 } 797 798 /// setTruncStoreAction - Indicate that the specified truncating store does 799 /// not work with the with specified type and indicate what to do about it. 800 void setTruncStoreAction(MVT::ValueType ValVT, MVT::ValueType MemVT, 801 LegalizeAction Action) { 802 assert(ValVT < array_lengthof(TruncStoreActions) && 803 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!"); 804 TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2); 805 TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2; 806 } 807 808 /// setIndexedLoadAction - Indicate that the specified indexed load does or 809 /// does not work with the with specified type and indicate what to do abort 810 /// it. NOTE: All indexed mode loads are initialized to Expand in 811 /// TargetLowering.cpp 812 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 813 LegalizeAction Action) { 814 assert(VT < sizeof(IndexedModeActions[0])*4 && IdxMode < 815 array_lengthof(IndexedModeActions[0]) && 816 "Table isn't big enough!"); 817 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 818 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 819 } 820 821 /// setIndexedStoreAction - Indicate that the specified indexed store does or 822 /// does not work with the with specified type and indicate what to do about 823 /// it. NOTE: All indexed mode stores are initialized to Expand in 824 /// TargetLowering.cpp 825 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 826 LegalizeAction Action) { 827 assert(VT < sizeof(IndexedModeActions[1][0])*4 && 828 IdxMode < array_lengthof(IndexedModeActions[1]) && 829 "Table isn't big enough!"); 830 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 831 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 832 } 833 834 /// setConvertAction - Indicate that the specified conversion does or does 835 /// not work with the with specified type and indicate what to do about it. 836 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT, 837 LegalizeAction Action) { 838 assert(FromVT < array_lengthof(ConvertActions) && 839 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!"); 840 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2); 841 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2; 842 } 843 844 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 845 /// promotion code defaults to trying a larger integer/fp until it can find 846 /// one that works. If that default is insufficient, this method can be used 847 /// by the target to override the default. 848 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 849 MVT::ValueType DestVT) { 850 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 851 } 852 853 /// addLegalFPImmediate - Indicate that this target can instruction select 854 /// the specified FP immediate natively. 855 void addLegalFPImmediate(const APFloat& Imm) { 856 LegalFPImmediates.push_back(Imm); 857 } 858 859 /// setTargetDAGCombine - Targets should invoke this method for each target 860 /// independent node that they want to provide a custom DAG combiner for by 861 /// implementing the PerformDAGCombine virtual method. 862 void setTargetDAGCombine(ISD::NodeType NT) { 863 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 864 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 865 } 866 867 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 868 /// bytes); default is 200 869 void setJumpBufSize(unsigned Size) { 870 JumpBufSize = Size; 871 } 872 873 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 874 /// alignment (in bytes); default is 0 875 void setJumpBufAlignment(unsigned Align) { 876 JumpBufAlignment = Align; 877 } 878 879 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 880 /// limit (in number of instructions); default is 2. 881 void setIfCvtBlockSizeLimit(unsigned Limit) { 882 IfCvtBlockSizeLimit = Limit; 883 } 884 885 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 886 /// of instructions) to be considered for code duplication during 887 /// if-conversion; default is 2. 888 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 889 IfCvtDupBlockSizeLimit = Limit; 890 } 891 892public: 893 894 virtual const TargetSubtarget *getSubtarget() { 895 assert(0 && "Not Implemented"); 896 return NULL; // this is here to silence compiler errors 897 } 898 //===--------------------------------------------------------------------===// 899 // Lowering methods - These methods must be implemented by targets so that 900 // the SelectionDAGLowering code knows how to lower these. 901 // 902 903 /// LowerArguments - This hook must be implemented to indicate how we should 904 /// lower the arguments for the specified function, into the specified DAG. 905 virtual std::vector<SDOperand> 906 LowerArguments(Function &F, SelectionDAG &DAG); 907 908 /// LowerCallTo - This hook lowers an abstract call to a function into an 909 /// actual call. This returns a pair of operands. The first element is the 910 /// return value for the function (if RetTy is not VoidTy). The second 911 /// element is the outgoing token chain. 912 struct ArgListEntry { 913 SDOperand Node; 914 const Type* Ty; 915 bool isSExt; 916 bool isZExt; 917 bool isInReg; 918 bool isSRet; 919 bool isNest; 920 bool isByVal; 921 922 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 923 isSRet(false), isNest(false), isByVal(false) { } 924 }; 925 typedef std::vector<ArgListEntry> ArgListTy; 926 virtual std::pair<SDOperand, SDOperand> 927 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 928 bool isVarArg, unsigned CallingConv, bool isTailCall, 929 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 930 931 932 virtual SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG); 933 virtual SDOperand LowerMEMCPYCall(SDOperand Chain, SDOperand Dest, 934 SDOperand Source, SDOperand Count, 935 SelectionDAG &DAG); 936 virtual SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest, 937 SDOperand Source, unsigned Size, 938 unsigned Align, SelectionDAG &DAG) { 939 assert(0 && "Not Implemented"); 940 return SDOperand(); // this is here to silence compiler errors 941 } 942 943 944 /// LowerOperation - This callback is invoked for operations that are 945 /// unsupported by the target, which are registered to use 'custom' lowering, 946 /// and whose defined values are all legal. 947 /// If the target has no operations that require custom lowering, it need not 948 /// implement this. The default implementation of this aborts. 949 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 950 951 /// ExpandOperationResult - This callback is invoked for operations that are 952 /// unsupported by the target, which are registered to use 'custom' lowering, 953 /// and whose result type needs to be expanded. This must return a node whose 954 /// results precisely match the results of the input node. This typically 955 /// involves a MERGE_VALUES node and/or BUILD_PAIR. 956 /// 957 /// If the target has no operations that require custom lowering, it need not 958 /// implement this. The default implementation of this aborts. 959 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { 960 assert(0 && "ExpandOperationResult not implemented for this target!"); 961 return 0; 962 } 963 964 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 965 /// tail call optimization. Targets which want to do tail call optimization 966 /// should override this function. 967 virtual bool IsEligibleForTailCallOptimization(SDOperand Call, 968 SDOperand Ret, 969 SelectionDAG &DAG) const { 970 return false; 971 } 972 973 /// CustomPromoteOperation - This callback is invoked for operations that are 974 /// unsupported by the target, are registered to use 'custom' lowering, and 975 /// whose type needs to be promoted. 976 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 977 978 /// getTargetNodeName() - This method returns the name of a target specific 979 /// DAG node. 980 virtual const char *getTargetNodeName(unsigned Opcode) const; 981 982 //===--------------------------------------------------------------------===// 983 // Inline Asm Support hooks 984 // 985 986 enum ConstraintType { 987 C_Register, // Constraint represents a single register. 988 C_RegisterClass, // Constraint represents one or more registers. 989 C_Memory, // Memory constraint. 990 C_Other, // Something else. 991 C_Unknown // Unsupported constraint. 992 }; 993 994 /// getConstraintType - Given a constraint, return the type of constraint it 995 /// is for this target. 996 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 997 998 999 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1000 /// return a list of registers that can be used to satisfy the constraint. 1001 /// This should only be used for C_RegisterClass constraints. 1002 virtual std::vector<unsigned> 1003 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1004 MVT::ValueType VT) const; 1005 1006 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1007 /// {edx}), return the register number and the register class for the 1008 /// register. 1009 /// 1010 /// Given a register class constraint, like 'r', if this corresponds directly 1011 /// to an LLVM register class, return a register of 0 and the register class 1012 /// pointer. 1013 /// 1014 /// This should only be used for C_Register constraints. On error, 1015 /// this returns a register number of 0 and a null register class pointer.. 1016 virtual std::pair<unsigned, const TargetRegisterClass*> 1017 getRegForInlineAsmConstraint(const std::string &Constraint, 1018 MVT::ValueType VT) const; 1019 1020 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1021 /// with another that has more specific requirements based on the type of the 1022 /// corresponding operand. 1023 virtual void lowerXConstraint(MVT::ValueType ConstraintVT, 1024 std::string&) const; 1025 1026 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1027 /// vector. If it is invalid, don't add anything to Ops. 1028 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter, 1029 std::vector<SDOperand> &Ops, 1030 SelectionDAG &DAG); 1031 1032 //===--------------------------------------------------------------------===// 1033 // Scheduler hooks 1034 // 1035 1036 // EmitInstrWithCustomInserter - This method should be implemented by targets 1037 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1038 // instructions are special in various ways, which require special support to 1039 // insert. The specified MachineInstr is created but not inserted into any 1040 // basic blocks, and the scheduler passes ownership of it to this method. 1041 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1042 MachineBasicBlock *MBB); 1043 1044 //===--------------------------------------------------------------------===// 1045 // Addressing mode description hooks (used by LSR etc). 1046 // 1047 1048 /// AddrMode - This represents an addressing mode of: 1049 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1050 /// If BaseGV is null, there is no BaseGV. 1051 /// If BaseOffs is zero, there is no base offset. 1052 /// If HasBaseReg is false, there is no base register. 1053 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1054 /// no scale. 1055 /// 1056 struct AddrMode { 1057 GlobalValue *BaseGV; 1058 int64_t BaseOffs; 1059 bool HasBaseReg; 1060 int64_t Scale; 1061 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1062 }; 1063 1064 /// isLegalAddressingMode - Return true if the addressing mode represented by 1065 /// AM is legal for this target, for a load/store of the specified type. 1066 /// TODO: Handle pre/postinc as well. 1067 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1068 1069 /// isTruncateFree - Return true if it's free to truncate a value of 1070 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1071 /// register EAX to i16 by referencing its sub-register AX. 1072 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1073 return false; 1074 } 1075 1076 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const { 1077 return false; 1078 } 1079 1080 //===--------------------------------------------------------------------===// 1081 // Div utility functions 1082 // 1083 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 1084 std::vector<SDNode*>* Created) const; 1085 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 1086 std::vector<SDNode*>* Created) const; 1087 1088 1089 //===--------------------------------------------------------------------===// 1090 // Runtime Library hooks 1091 // 1092 1093 /// setLibcallName - Rename the default libcall routine name for the specified 1094 /// libcall. 1095 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1096 LibcallRoutineNames[Call] = Name; 1097 } 1098 1099 /// getLibcallName - Get the libcall routine name for the specified libcall. 1100 /// 1101 const char *getLibcallName(RTLIB::Libcall Call) const { 1102 return LibcallRoutineNames[Call]; 1103 } 1104 1105 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1106 /// result of the comparison libcall against zero. 1107 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1108 CmpLibcallCCs[Call] = CC; 1109 } 1110 1111 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1112 /// the comparison libcall against zero. 1113 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1114 return CmpLibcallCCs[Call]; 1115 } 1116 1117private: 1118 TargetMachine &TM; 1119 const TargetData *TD; 1120 1121 /// IsLittleEndian - True if this is a little endian target. 1122 /// 1123 bool IsLittleEndian; 1124 1125 /// PointerTy - The type to use for pointers, usually i32 or i64. 1126 /// 1127 MVT::ValueType PointerTy; 1128 1129 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1130 /// 1131 bool UsesGlobalOffsetTable; 1132 1133 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1134 /// PointerTy is. 1135 MVT::ValueType ShiftAmountTy; 1136 1137 OutOfRangeShiftAmount ShiftAmtHandling; 1138 1139 /// SelectIsExpensive - Tells the code generator not to expand operations 1140 /// into sequences that use the select operations if possible. 1141 bool SelectIsExpensive; 1142 1143 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1144 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1145 /// a real cost model is in place. If we ever optimize for size, this will be 1146 /// set to true unconditionally. 1147 bool IntDivIsCheap; 1148 1149 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1150 /// srl/add/sra for a signed divide by power of two, and let the target handle 1151 /// it. 1152 bool Pow2DivIsCheap; 1153 1154 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 1155 /// PointerTy. 1156 MVT::ValueType SetCCResultTy; 1157 1158 /// SetCCResultContents - Information about the contents of the high-bits in 1159 /// the result of a setcc comparison operation. 1160 SetCCResultValue SetCCResultContents; 1161 1162 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1163 /// total cycles or lowest register usage. 1164 SchedPreference SchedPreferenceInfo; 1165 1166 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1167 /// llvm.setjmp. Defaults to false. 1168 bool UseUnderscoreSetJmp; 1169 1170 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1171 /// llvm.longjmp. Defaults to false. 1172 bool UseUnderscoreLongJmp; 1173 1174 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1175 unsigned JumpBufSize; 1176 1177 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1178 /// buffers 1179 unsigned JumpBufAlignment; 1180 1181 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1182 /// if-converted. 1183 unsigned IfCvtBlockSizeLimit; 1184 1185 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1186 /// duplicated during if-conversion. 1187 unsigned IfCvtDupBlockSizeLimit; 1188 1189 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1190 /// specifies the register that llvm.savestack/llvm.restorestack should save 1191 /// and restore. 1192 unsigned StackPointerRegisterToSaveRestore; 1193 1194 /// ExceptionPointerRegister - If set to a physical register, this specifies 1195 /// the register that receives the exception address on entry to a landing 1196 /// pad. 1197 unsigned ExceptionPointerRegister; 1198 1199 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1200 /// the register that receives the exception typeid on entry to a landing 1201 /// pad. 1202 unsigned ExceptionSelectorRegister; 1203 1204 /// RegClassForVT - This indicates the default register class to use for 1205 /// each ValueType the target supports natively. 1206 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1207 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1208 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1209 1210 /// TransformToType - For any value types we are promoting or expanding, this 1211 /// contains the value type that we are changing to. For Expanded types, this 1212 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1213 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1214 /// by the system, this holds the same type (e.g. i32 -> i32). 1215 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1216 1217 /// OpActions - For each operation and each value type, keep a LegalizeAction 1218 /// that indicates how instruction selection should deal with the operation. 1219 /// Most operations are Legal (aka, supported natively by the target), but 1220 /// operations that are not should be described. Note that operations on 1221 /// non-legal value types are not described here. 1222 uint64_t OpActions[156]; 1223 1224 /// LoadXActions - For each load of load extension type and each value type, 1225 /// keep a LegalizeAction that indicates how instruction selection should deal 1226 /// with the load. 1227 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1228 1229 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1230 /// indicates how instruction selection should deal with the store. 1231 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1232 1233 /// IndexedModeActions - For each indexed mode and each value type, keep a 1234 /// pair of LegalizeAction that indicates how instruction selection should 1235 /// deal with the load / store. 1236 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1237 1238 /// ConvertActions - For each conversion from source type to destination type, 1239 /// keep a LegalizeAction that indicates how instruction selection should 1240 /// deal with the conversion. 1241 /// Currently, this is used only for floating->floating conversions 1242 /// (FP_EXTEND and FP_ROUND). 1243 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1244 1245 ValueTypeActionImpl ValueTypeActions; 1246 1247 std::vector<APFloat> LegalFPImmediates; 1248 1249 std::vector<std::pair<MVT::ValueType, 1250 TargetRegisterClass*> > AvailableRegClasses; 1251 1252 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1253 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1254 /// which sets a bit in this array. 1255 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1256 1257 /// PromoteToType - For operations that must be promoted to a specific type, 1258 /// this holds the destination type. This map should be sparse, so don't hold 1259 /// it as an array. 1260 /// 1261 /// Targets add entries to this map with AddPromotedToType(..), clients access 1262 /// this with getTypeToPromoteTo(..). 1263 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1264 1265 /// LibcallRoutineNames - Stores the name each libcall. 1266 /// 1267 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1268 1269 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1270 /// of each of the comparison libcall against zero. 1271 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1272 1273protected: 1274 /// When lowering %llvm.memset this field specifies the maximum number of 1275 /// store operations that may be substituted for the call to memset. Targets 1276 /// must set this value based on the cost threshold for that target. Targets 1277 /// should assume that the memset will be done using as many of the largest 1278 /// store operations first, followed by smaller ones, if necessary, per 1279 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1280 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1281 /// store. This only applies to setting a constant array of a constant size. 1282 /// @brief Specify maximum number of store instructions per memset call. 1283 unsigned maxStoresPerMemset; 1284 1285 /// When lowering %llvm.memcpy this field specifies the maximum number of 1286 /// store operations that may be substituted for a call to memcpy. Targets 1287 /// must set this value based on the cost threshold for that target. Targets 1288 /// should assume that the memcpy will be done using as many of the largest 1289 /// store operations first, followed by smaller ones, if necessary, per 1290 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1291 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1292 /// and one 1-byte store. This only applies to copying a constant array of 1293 /// constant size. 1294 /// @brief Specify maximum bytes of store instructions per memcpy call. 1295 unsigned maxStoresPerMemcpy; 1296 1297 /// When lowering %llvm.memmove this field specifies the maximum number of 1298 /// store instructions that may be substituted for a call to memmove. Targets 1299 /// must set this value based on the cost threshold for that target. Targets 1300 /// should assume that the memmove will be done using as many of the largest 1301 /// store operations first, followed by smaller ones, if necessary, per 1302 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1303 /// with 8-bit alignment would result in nine 1-byte stores. This only 1304 /// applies to copying a constant array of constant size. 1305 /// @brief Specify maximum bytes of store instructions per memmove call. 1306 unsigned maxStoresPerMemmove; 1307 1308 /// This field specifies whether the target machine permits unaligned memory 1309 /// accesses. This is used, for example, to determine the size of store 1310 /// operations when copying small arrays and other similar tasks. 1311 /// @brief Indicate whether the target permits unaligned memory accesses. 1312 bool allowUnalignedMemoryAccesses; 1313}; 1314} // end llvm namespace 1315 1316#endif 1317