TargetLowering.h revision a1dc96edd28340bc6e1971835bf09610cc7ecdb3
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include "llvm/ADT/APFloat.h" 28#include "llvm/ADT/STLExtras.h" 29#include <map> 30#include <vector> 31 32namespace llvm { 33 class Value; 34 class Function; 35 class TargetMachine; 36 class TargetData; 37 class TargetRegisterClass; 38 class SDNode; 39 class SDOperand; 40 class SelectionDAG; 41 class MachineBasicBlock; 42 class MachineInstr; 43 class VectorType; 44 class TargetSubtarget; 45 46//===----------------------------------------------------------------------===// 47/// TargetLowering - This class defines information used to lower LLVM code to 48/// legal SelectionDAG operators that the target instruction selector can accept 49/// natively. 50/// 51/// This class also defines callbacks that targets must implement to lower 52/// target-specific constructs to SelectionDAG operators. 53/// 54class TargetLowering { 55public: 56 /// LegalizeAction - This enum indicates whether operations are valid for a 57 /// target, and if not, what action should be used to make them valid. 58 enum LegalizeAction { 59 Legal, // The target natively supports this operation. 60 Promote, // This operation should be executed in a larger type. 61 Expand, // Try to expand this to other ops, otherwise use a libcall. 62 Custom // Use the LowerOperation hook to implement custom lowering. 63 }; 64 65 enum OutOfRangeShiftAmount { 66 Undefined, // Oversized shift amounts are undefined (default). 67 Mask, // Shift amounts are auto masked (anded) to value size. 68 Extend // Oversized shift pulls in zeros or sign bits. 69 }; 70 71 enum SetCCResultValue { 72 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 73 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 74 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 75 }; 76 77 enum SchedPreference { 78 SchedulingForLatency, // Scheduling for shortest total latency. 79 SchedulingForRegPressure // Scheduling for lowest register pressure. 80 }; 81 82 explicit TargetLowering(TargetMachine &TM); 83 virtual ~TargetLowering(); 84 85 TargetMachine &getTargetMachine() const { return TM; } 86 const TargetData *getTargetData() const { return TD; } 87 88 bool isLittleEndian() const { return IsLittleEndian; } 89 MVT::ValueType getPointerTy() const { return PointerTy; } 90 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 91 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 92 93 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 94 /// codegen. 95 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 96 97 /// isSelectExpensive - Return true if the select operation is expensive for 98 /// this target. 99 bool isSelectExpensive() const { return SelectIsExpensive; } 100 101 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 102 /// a sequence of several shifts, adds, and multiplies for this target. 103 bool isIntDivCheap() const { return IntDivIsCheap; } 104 105 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 106 /// srl/add/sra. 107 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 108 109 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 110 /// 111 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 112 113 /// getSetCCResultContents - For targets without boolean registers, this flag 114 /// returns information about the contents of the high-bits in the setcc 115 /// result register. 116 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 117 118 /// getSchedulingPreference - Return target scheduling preference. 119 SchedPreference getSchedulingPreference() const { 120 return SchedPreferenceInfo; 121 } 122 123 /// getRegClassFor - Return the register class that should be used for the 124 /// specified value type. This may only be called on legal types. 125 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 126 assert(!MVT::isExtendedVT(VT)); 127 TargetRegisterClass *RC = RegClassForVT[VT]; 128 assert(RC && "This value type is not natively supported!"); 129 return RC; 130 } 131 132 /// isTypeLegal - Return true if the target has native support for the 133 /// specified value type. This means that it has a register that directly 134 /// holds it without promotions or expansions. 135 bool isTypeLegal(MVT::ValueType VT) const { 136 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; 137 } 138 139 class ValueTypeActionImpl { 140 /// ValueTypeActions - This is a bitvector that contains two bits for each 141 /// value type, where the two bits correspond to the LegalizeAction enum. 142 /// This can be queried with "getTypeAction(VT)". 143 uint32_t ValueTypeActions[2]; 144 public: 145 ValueTypeActionImpl() { 146 ValueTypeActions[0] = ValueTypeActions[1] = 0; 147 } 148 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 149 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 150 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 151 } 152 153 LegalizeAction getTypeAction(MVT::ValueType VT) const { 154 if (MVT::isExtendedVT(VT)) { 155 if (MVT::isVector(VT)) return Expand; 156 if (MVT::isInteger(VT)) 157 // First promote to a power-of-two size, then expand if necessary. 158 return VT == MVT::RoundIntegerType(VT) ? Expand : Promote; 159 assert(0 && "Unsupported extended type!"); 160 } 161 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 162 } 163 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 164 assert(!MVT::isExtendedVT(VT)); 165 assert(unsigned(VT >> 4) < array_lengthof(ValueTypeActions)); 166 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 167 } 168 }; 169 170 const ValueTypeActionImpl &getValueTypeActions() const { 171 return ValueTypeActions; 172 } 173 174 /// getTypeAction - Return how we should legalize values of this type, either 175 /// it is already legal (return 'Legal') or we need to promote it to a larger 176 /// type (return 'Promote'), or we need to expand it into multiple registers 177 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 178 LegalizeAction getTypeAction(MVT::ValueType VT) const { 179 return ValueTypeActions.getTypeAction(VT); 180 } 181 182 /// getTypeToTransformTo - For types supported by the target, this is an 183 /// identity function. For types that must be promoted to larger types, this 184 /// returns the larger type to promote to. For integer types that are larger 185 /// than the largest integer register, this contains one step in the expansion 186 /// to get to the smaller register. For illegal floating point types, this 187 /// returns the integer type to transform to. 188 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 189 if (!MVT::isExtendedVT(VT)) { 190 MVT::ValueType NVT = TransformToType[VT]; 191 assert(getTypeAction(NVT) != Promote && 192 "Promote may not follow Expand or Promote"); 193 return NVT; 194 } 195 196 if (MVT::isVector(VT)) 197 return MVT::getVectorType(MVT::getVectorElementType(VT), 198 MVT::getVectorNumElements(VT) / 2); 199 if (MVT::isInteger(VT)) { 200 MVT::ValueType NVT = MVT::RoundIntegerType(VT); 201 if (NVT == VT) 202 // Size is a power of two - expand to half the size. 203 return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2); 204 else 205 // Promote to a power of two size, avoiding multi-step promotion. 206 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 207 } 208 assert(0 && "Unsupported extended type!"); 209 } 210 211 /// getTypeToExpandTo - For types supported by the target, this is an 212 /// identity function. For types that must be expanded (i.e. integer types 213 /// that are larger than the largest integer register or illegal floating 214 /// point types), this returns the largest legal type it will be expanded to. 215 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 216 assert(!MVT::isVector(VT)); 217 while (true) { 218 switch (getTypeAction(VT)) { 219 case Legal: 220 return VT; 221 case Expand: 222 VT = getTypeToTransformTo(VT); 223 break; 224 default: 225 assert(false && "Type is not legal nor is it to be expanded!"); 226 return VT; 227 } 228 } 229 return VT; 230 } 231 232 /// getVectorTypeBreakdown - Vector types are broken down into some number of 233 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 234 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 235 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 236 /// 237 /// This method returns the number of registers needed, and the VT for each 238 /// register. It also returns the VT and quantity of the intermediate values 239 /// before they are promoted/expanded. 240 /// 241 unsigned getVectorTypeBreakdown(MVT::ValueType VT, 242 MVT::ValueType &IntermediateVT, 243 unsigned &NumIntermediates, 244 MVT::ValueType &RegisterVT) const; 245 246 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 247 legal_fpimm_iterator legal_fpimm_begin() const { 248 return LegalFPImmediates.begin(); 249 } 250 legal_fpimm_iterator legal_fpimm_end() const { 251 return LegalFPImmediates.end(); 252 } 253 254 /// isShuffleMaskLegal - Targets can use this to indicate that they only 255 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 256 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 257 /// are assumed to be legal. 258 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 259 return true; 260 } 261 262 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 263 /// used by Targets can use this to indicate if there is a suitable 264 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 265 /// pool entry. 266 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 267 MVT::ValueType EVT, 268 SelectionDAG &DAG) const { 269 return false; 270 } 271 272 /// getOperationAction - Return how this operation should be treated: either 273 /// it is legal, needs to be promoted to a larger size, needs to be 274 /// expanded to some other code sequence, or the target has a custom expander 275 /// for it. 276 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 277 if (MVT::isExtendedVT(VT)) return Expand; 278 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 279 } 280 281 /// isOperationLegal - Return true if the specified operation is legal on this 282 /// target. 283 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 284 return getOperationAction(Op, VT) == Legal || 285 getOperationAction(Op, VT) == Custom; 286 } 287 288 /// getLoadXAction - Return how this load with extension should be treated: 289 /// either it is legal, needs to be promoted to a larger size, needs to be 290 /// expanded to some other code sequence, or the target has a custom expander 291 /// for it. 292 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 293 if (MVT::isExtendedVT(VT)) return getTypeAction(VT); 294 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); 295 } 296 297 /// isLoadXLegal - Return true if the specified load with extension is legal 298 /// on this target. 299 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 300 return getLoadXAction(LType, VT) == Legal || 301 getLoadXAction(LType, VT) == Custom; 302 } 303 304 /// getStoreXAction - Return how this store with truncation should be treated: 305 /// either it is legal, needs to be promoted to a larger size, needs to be 306 /// expanded to some other code sequence, or the target has a custom expander 307 /// for it. 308 LegalizeAction getStoreXAction(MVT::ValueType VT) const { 309 if (MVT::isExtendedVT(VT)) return getTypeAction(VT); 310 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3); 311 } 312 313 /// isStoreXLegal - Return true if the specified store with truncation is 314 /// legal on this target. 315 bool isStoreXLegal(MVT::ValueType VT) const { 316 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom; 317 } 318 319 /// getIndexedLoadAction - Return how the indexed load should be treated: 320 /// either it is legal, needs to be promoted to a larger size, needs to be 321 /// expanded to some other code sequence, or the target has a custom expander 322 /// for it. 323 LegalizeAction 324 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 325 if (MVT::isExtendedVT(VT)) return getTypeAction(VT); 326 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); 327 } 328 329 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 330 /// on this target. 331 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 332 return getIndexedLoadAction(IdxMode, VT) == Legal || 333 getIndexedLoadAction(IdxMode, VT) == Custom; 334 } 335 336 /// getIndexedStoreAction - Return how the indexed store should be treated: 337 /// either it is legal, needs to be promoted to a larger size, needs to be 338 /// expanded to some other code sequence, or the target has a custom expander 339 /// for it. 340 LegalizeAction 341 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 342 if (MVT::isExtendedVT(VT)) return getTypeAction(VT); 343 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); 344 } 345 346 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 347 /// on this target. 348 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 349 return getIndexedStoreAction(IdxMode, VT) == Legal || 350 getIndexedStoreAction(IdxMode, VT) == Custom; 351 } 352 353 /// getConvertAction - Return how the conversion should be treated: 354 /// either it is legal, needs to be promoted to a larger size, needs to be 355 /// expanded to some other code sequence, or the target has a custom expander 356 /// for it. 357 LegalizeAction 358 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 359 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 && 360 "Table isn't big enough!"); 361 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3); 362 } 363 364 /// isConvertLegal - Return true if the specified conversion is legal 365 /// on this target. 366 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 367 return getConvertAction(FromVT, ToVT) == Legal || 368 getConvertAction(FromVT, ToVT) == Custom; 369 } 370 371 /// getTypeToPromoteTo - If the action for this operation is to promote, this 372 /// method returns the ValueType to promote to. 373 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 374 assert(getOperationAction(Op, VT) == Promote && 375 "This operation isn't promoted!"); 376 377 // See if this has an explicit type specified. 378 std::map<std::pair<unsigned, MVT::ValueType>, 379 MVT::ValueType>::const_iterator PTTI = 380 PromoteToType.find(std::make_pair(Op, VT)); 381 if (PTTI != PromoteToType.end()) return PTTI->second; 382 383 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 384 "Cannot autopromote this type, add it with AddPromotedToType."); 385 386 MVT::ValueType NVT = VT; 387 do { 388 NVT = (MVT::ValueType)(NVT+1); 389 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 390 "Didn't find type to promote to!"); 391 } while (!isTypeLegal(NVT) || 392 getOperationAction(Op, NVT) == Promote); 393 return NVT; 394 } 395 396 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 397 /// This is fixed by the LLVM operations except for the pointer size. If 398 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 399 /// counterpart (e.g. structs), otherwise it will assert. 400 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { 401 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); 402 return VT == MVT::iPTR ? PointerTy : VT; 403 } 404 405 /// getRegisterType - Return the type of registers that this ValueType will 406 /// eventually require. 407 MVT::ValueType getRegisterType(MVT::ValueType VT) const { 408 if (!MVT::isExtendedVT(VT)) 409 return RegisterTypeForVT[VT]; 410 if (MVT::isVector(VT)) { 411 MVT::ValueType VT1, RegisterVT; 412 unsigned NumIntermediates; 413 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 414 return RegisterVT; 415 } 416 assert(0 && "Unsupported extended type!"); 417 } 418 419 /// getNumRegisters - Return the number of registers that this ValueType will 420 /// eventually require. This is one for any types promoted to live in larger 421 /// registers, but may be more than one for types (like i64) that are split 422 /// into pieces. 423 unsigned getNumRegisters(MVT::ValueType VT) const { 424 if (!MVT::isExtendedVT(VT)) 425 return NumRegistersForVT[VT]; 426 if (MVT::isVector(VT)) { 427 MVT::ValueType VT1, VT2; 428 unsigned NumIntermediates; 429 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 430 } 431 assert(0 && "Unsupported extended type!"); 432 } 433 434 /// hasTargetDAGCombine - If true, the target has custom DAG combine 435 /// transformations that it can perform for the specified node. 436 bool hasTargetDAGCombine(ISD::NodeType NT) const { 437 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 438 } 439 440 /// This function returns the maximum number of store operations permitted 441 /// to replace a call to llvm.memset. The value is set by the target at the 442 /// performance threshold for such a replacement. 443 /// @brief Get maximum # of store operations permitted for llvm.memset 444 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 445 446 /// This function returns the maximum number of store operations permitted 447 /// to replace a call to llvm.memcpy. The value is set by the target at the 448 /// performance threshold for such a replacement. 449 /// @brief Get maximum # of store operations permitted for llvm.memcpy 450 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 451 452 /// This function returns the maximum number of store operations permitted 453 /// to replace a call to llvm.memmove. The value is set by the target at the 454 /// performance threshold for such a replacement. 455 /// @brief Get maximum # of store operations permitted for llvm.memmove 456 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 457 458 /// This function returns true if the target allows unaligned memory accesses. 459 /// This is used, for example, in situations where an array copy/move/set is 460 /// converted to a sequence of store operations. It's use helps to ensure that 461 /// such replacements don't generate code that causes an alignment error 462 /// (trap) on the target machine. 463 /// @brief Determine if the target supports unaligned memory accesses. 464 bool allowsUnalignedMemoryAccesses() const { 465 return allowUnalignedMemoryAccesses; 466 } 467 468 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 469 /// to implement llvm.setjmp. 470 bool usesUnderscoreSetJmp() const { 471 return UseUnderscoreSetJmp; 472 } 473 474 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 475 /// to implement llvm.longjmp. 476 bool usesUnderscoreLongJmp() const { 477 return UseUnderscoreLongJmp; 478 } 479 480 /// getStackPointerRegisterToSaveRestore - If a physical register, this 481 /// specifies the register that llvm.savestack/llvm.restorestack should save 482 /// and restore. 483 unsigned getStackPointerRegisterToSaveRestore() const { 484 return StackPointerRegisterToSaveRestore; 485 } 486 487 /// getExceptionAddressRegister - If a physical register, this returns 488 /// the register that receives the exception address on entry to a landing 489 /// pad. 490 unsigned getExceptionAddressRegister() const { 491 return ExceptionPointerRegister; 492 } 493 494 /// getExceptionSelectorRegister - If a physical register, this returns 495 /// the register that receives the exception typeid on entry to a landing 496 /// pad. 497 unsigned getExceptionSelectorRegister() const { 498 return ExceptionSelectorRegister; 499 } 500 501 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 502 /// set, the default is 200) 503 unsigned getJumpBufSize() const { 504 return JumpBufSize; 505 } 506 507 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 508 /// (if never set, the default is 0) 509 unsigned getJumpBufAlignment() const { 510 return JumpBufAlignment; 511 } 512 513 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 514 /// limit. Any block whose size is greater should not be predicated. 515 virtual unsigned getIfCvtBlockSizeLimit() const { 516 return IfCvtBlockSizeLimit; 517 } 518 519 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 520 /// block to be considered for duplication. Any block whose size is greater 521 /// should not be duplicated to facilitate its predication. 522 virtual unsigned getIfCvtDupBlockSizeLimit() const { 523 return IfCvtDupBlockSizeLimit; 524 } 525 526 /// getPreIndexedAddressParts - returns true by value, base pointer and 527 /// offset pointer and addressing mode by reference if the node's address 528 /// can be legally represented as pre-indexed load / store address. 529 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 530 SDOperand &Offset, 531 ISD::MemIndexedMode &AM, 532 SelectionDAG &DAG) { 533 return false; 534 } 535 536 /// getPostIndexedAddressParts - returns true by value, base pointer and 537 /// offset pointer and addressing mode by reference if this node can be 538 /// combined with a load / store to form a post-indexed load / store. 539 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 540 SDOperand &Base, SDOperand &Offset, 541 ISD::MemIndexedMode &AM, 542 SelectionDAG &DAG) { 543 return false; 544 } 545 546 //===--------------------------------------------------------------------===// 547 // TargetLowering Optimization Methods 548 // 549 550 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 551 /// SDOperands for returning information from TargetLowering to its clients 552 /// that want to combine 553 struct TargetLoweringOpt { 554 SelectionDAG &DAG; 555 SDOperand Old; 556 SDOperand New; 557 558 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 559 560 bool CombineTo(SDOperand O, SDOperand N) { 561 Old = O; 562 New = N; 563 return true; 564 } 565 566 /// ShrinkDemandedConstant - Check to see if the specified operand of the 567 /// specified instruction is a constant integer. If so, check to see if 568 /// there are any bits set in the constant that are not demanded. If so, 569 /// shrink the constant and return true. 570 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 571 }; 572 573 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 574 /// DemandedMask bits of the result of Op are ever used downstream. If we can 575 /// use this information to simplify Op, create a new simplified DAG node and 576 /// return true, returning the original and new nodes in Old and New. 577 /// Otherwise, analyze the expression and return a mask of KnownOne and 578 /// KnownZero bits for the expression (used to simplify the caller). 579 /// The KnownZero/One bits may only be accurate for those bits in the 580 /// DemandedMask. 581 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 582 uint64_t &KnownZero, uint64_t &KnownOne, 583 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 584 585 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 586 /// Mask are known to be either zero or one and return them in the 587 /// KnownZero/KnownOne bitsets. 588 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 589 uint64_t Mask, 590 uint64_t &KnownZero, 591 uint64_t &KnownOne, 592 const SelectionDAG &DAG, 593 unsigned Depth = 0) const; 594 595 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 596 /// targets that want to expose additional information about sign bits to the 597 /// DAG Combiner. 598 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 599 unsigned Depth = 0) const; 600 601 struct DAGCombinerInfo { 602 void *DC; // The DAG Combiner object. 603 bool BeforeLegalize; 604 bool CalledByLegalizer; 605 public: 606 SelectionDAG &DAG; 607 608 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 609 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 610 611 bool isBeforeLegalize() const { return BeforeLegalize; } 612 bool isCalledByLegalizer() const { return CalledByLegalizer; } 613 614 void AddToWorklist(SDNode *N); 615 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 616 SDOperand CombineTo(SDNode *N, SDOperand Res); 617 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 618 }; 619 620 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 621 /// and cc. If it is unable to simplify it, return a null SDOperand. 622 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 623 ISD::CondCode Cond, bool foldBooleans, 624 DAGCombinerInfo &DCI) const; 625 626 /// PerformDAGCombine - This method will be invoked for all target nodes and 627 /// for any target-independent nodes that the target has registered with 628 /// invoke it for. 629 /// 630 /// The semantics are as follows: 631 /// Return Value: 632 /// SDOperand.Val == 0 - No change was made 633 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 634 /// otherwise - N should be replaced by the returned Operand. 635 /// 636 /// In addition, methods provided by DAGCombinerInfo may be used to perform 637 /// more complex transformations. 638 /// 639 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 640 641 //===--------------------------------------------------------------------===// 642 // TargetLowering Configuration Methods - These methods should be invoked by 643 // the derived class constructor to configure this object for the target. 644 // 645 646protected: 647 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 648 /// GOT for PC-relative code. 649 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 650 651 /// setShiftAmountType - Describe the type that should be used for shift 652 /// amounts. This type defaults to the pointer type. 653 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 654 655 /// setSetCCResultType - Describe the type that shoudl be used as the result 656 /// of a setcc operation. This defaults to the pointer type. 657 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 658 659 /// setSetCCResultContents - Specify how the target extends the result of a 660 /// setcc operation in a register. 661 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 662 663 /// setSchedulingPreference - Specify the target scheduling preference. 664 void setSchedulingPreference(SchedPreference Pref) { 665 SchedPreferenceInfo = Pref; 666 } 667 668 /// setShiftAmountFlavor - Describe how the target handles out of range shift 669 /// amounts. 670 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 671 ShiftAmtHandling = OORSA; 672 } 673 674 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 675 /// use _setjmp to implement llvm.setjmp or the non _ version. 676 /// Defaults to false. 677 void setUseUnderscoreSetJmp(bool Val) { 678 UseUnderscoreSetJmp = Val; 679 } 680 681 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 682 /// use _longjmp to implement llvm.longjmp or the non _ version. 683 /// Defaults to false. 684 void setUseUnderscoreLongJmp(bool Val) { 685 UseUnderscoreLongJmp = Val; 686 } 687 688 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 689 /// specifies the register that llvm.savestack/llvm.restorestack should save 690 /// and restore. 691 void setStackPointerRegisterToSaveRestore(unsigned R) { 692 StackPointerRegisterToSaveRestore = R; 693 } 694 695 /// setExceptionPointerRegister - If set to a physical register, this sets 696 /// the register that receives the exception address on entry to a landing 697 /// pad. 698 void setExceptionPointerRegister(unsigned R) { 699 ExceptionPointerRegister = R; 700 } 701 702 /// setExceptionSelectorRegister - If set to a physical register, this sets 703 /// the register that receives the exception typeid on entry to a landing 704 /// pad. 705 void setExceptionSelectorRegister(unsigned R) { 706 ExceptionSelectorRegister = R; 707 } 708 709 /// SelectIsExpensive - Tells the code generator not to expand operations 710 /// into sequences that use the select operations if possible. 711 void setSelectIsExpensive() { SelectIsExpensive = true; } 712 713 /// setIntDivIsCheap - Tells the code generator that integer divide is 714 /// expensive, and if possible, should be replaced by an alternate sequence 715 /// of instructions not containing an integer divide. 716 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 717 718 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 719 /// srl/add/sra for a signed divide by power of two, and let the target handle 720 /// it. 721 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 722 723 /// addRegisterClass - Add the specified register class as an available 724 /// regclass for the specified value type. This indicates the selector can 725 /// handle values of that class natively. 726 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 727 assert(!MVT::isExtendedVT(VT)); 728 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 729 RegClassForVT[VT] = RC; 730 } 731 732 /// computeRegisterProperties - Once all of the register classes are added, 733 /// this allows us to compute derived properties we expose. 734 void computeRegisterProperties(); 735 736 /// setOperationAction - Indicate that the specified operation does not work 737 /// with the specified type and indicate what to do about it. 738 void setOperationAction(unsigned Op, MVT::ValueType VT, 739 LegalizeAction Action) { 740 assert(VT < 32 && Op < array_lengthof(OpActions) && 741 "Table isn't big enough!"); 742 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 743 OpActions[Op] |= (uint64_t)Action << VT*2; 744 } 745 746 /// setLoadXAction - Indicate that the specified load with extension does not 747 /// work with the with specified type and indicate what to do about it. 748 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 749 LegalizeAction Action) { 750 assert(VT < 32 && ExtType < array_lengthof(LoadXActions) && 751 "Table isn't big enough!"); 752 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 753 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 754 } 755 756 /// setStoreXAction - Indicate that the specified store with truncation does 757 /// not work with the with specified type and indicate what to do about it. 758 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) { 759 assert(VT < 32 && "Table isn't big enough!"); 760 StoreXActions &= ~(uint64_t(3UL) << VT*2); 761 StoreXActions |= (uint64_t)Action << VT*2; 762 } 763 764 /// setIndexedLoadAction - Indicate that the specified indexed load does or 765 /// does not work with the with specified type and indicate what to do abort 766 /// it. NOTE: All indexed mode loads are initialized to Expand in 767 /// TargetLowering.cpp 768 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 769 LegalizeAction Action) { 770 assert(VT < 32 && IdxMode < 771 array_lengthof(IndexedModeActions[0]) && 772 "Table isn't big enough!"); 773 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 774 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 775 } 776 777 /// setIndexedStoreAction - Indicate that the specified indexed store does or 778 /// does not work with the with specified type and indicate what to do about 779 /// it. NOTE: All indexed mode stores are initialized to Expand in 780 /// TargetLowering.cpp 781 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 782 LegalizeAction Action) { 783 assert(VT < 32 && IdxMode < 784 array_lengthof(IndexedModeActions[1]) && 785 "Table isn't big enough!"); 786 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 787 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 788 } 789 790 /// setConvertAction - Indicate that the specified conversion does or does 791 /// not work with the with specified type and indicate what to do about it. 792 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT, 793 LegalizeAction Action) { 794 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 && 795 "Table isn't big enough!"); 796 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2); 797 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2; 798 } 799 800 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 801 /// promotion code defaults to trying a larger integer/fp until it can find 802 /// one that works. If that default is insufficient, this method can be used 803 /// by the target to override the default. 804 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 805 MVT::ValueType DestVT) { 806 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 807 } 808 809 /// addLegalFPImmediate - Indicate that this target can instruction select 810 /// the specified FP immediate natively. 811 void addLegalFPImmediate(const APFloat& Imm) { 812 LegalFPImmediates.push_back(Imm); 813 } 814 815 /// setTargetDAGCombine - Targets should invoke this method for each target 816 /// independent node that they want to provide a custom DAG combiner for by 817 /// implementing the PerformDAGCombine virtual method. 818 void setTargetDAGCombine(ISD::NodeType NT) { 819 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 820 } 821 822 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 823 /// bytes); default is 200 824 void setJumpBufSize(unsigned Size) { 825 JumpBufSize = Size; 826 } 827 828 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 829 /// alignment (in bytes); default is 0 830 void setJumpBufAlignment(unsigned Align) { 831 JumpBufAlignment = Align; 832 } 833 834 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 835 /// limit (in number of instructions); default is 2. 836 void setIfCvtBlockSizeLimit(unsigned Limit) { 837 IfCvtBlockSizeLimit = Limit; 838 } 839 840 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 841 /// of instructions) to be considered for code duplication during 842 /// if-conversion; default is 2. 843 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 844 IfCvtDupBlockSizeLimit = Limit; 845 } 846 847public: 848 849 virtual const TargetSubtarget *getSubtarget() { 850 assert(0 && "Not Implemented"); 851 return NULL; // this is here to silence compiler errors 852 } 853 //===--------------------------------------------------------------------===// 854 // Lowering methods - These methods must be implemented by targets so that 855 // the SelectionDAGLowering code knows how to lower these. 856 // 857 858 /// LowerArguments - This hook must be implemented to indicate how we should 859 /// lower the arguments for the specified function, into the specified DAG. 860 virtual std::vector<SDOperand> 861 LowerArguments(Function &F, SelectionDAG &DAG); 862 863 /// LowerCallTo - This hook lowers an abstract call to a function into an 864 /// actual call. This returns a pair of operands. The first element is the 865 /// return value for the function (if RetTy is not VoidTy). The second 866 /// element is the outgoing token chain. 867 struct ArgListEntry { 868 SDOperand Node; 869 const Type* Ty; 870 bool isSExt; 871 bool isZExt; 872 bool isInReg; 873 bool isSRet; 874 bool isNest; 875 bool isByVal; 876 877 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 878 isSRet(false), isNest(false), isByVal(false) { } 879 }; 880 typedef std::vector<ArgListEntry> ArgListTy; 881 virtual std::pair<SDOperand, SDOperand> 882 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 883 bool isVarArg, unsigned CallingConv, bool isTailCall, 884 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 885 886 887 virtual SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG); 888 virtual SDOperand LowerMEMCPYCall(SDOperand Chain, SDOperand Dest, 889 SDOperand Source, SDOperand Count, 890 SelectionDAG &DAG); 891 virtual SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest, 892 SDOperand Source, unsigned Size, 893 unsigned Align, SelectionDAG &DAG) { 894 assert(0 && "Not Implemented"); 895 return SDOperand(); // this is here to silence compiler errors 896 } 897 898 899 /// LowerOperation - This callback is invoked for operations that are 900 /// unsupported by the target, which are registered to use 'custom' lowering, 901 /// and whose defined values are all legal. 902 /// If the target has no operations that require custom lowering, it need not 903 /// implement this. The default implementation of this aborts. 904 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 905 906 /// ExpandOperationResult - This callback is invoked for operations that are 907 /// unsupported by the target, which are registered to use 'custom' lowering, 908 /// and whose result type needs to be expanded. 909 /// 910 /// If the target has no operations that require custom lowering, it need not 911 /// implement this. The default implementation of this aborts. 912 virtual std::pair<SDOperand,SDOperand> 913 ExpandOperationResult(SDNode *N, SelectionDAG &DAG); 914 915 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 916 /// tail call optimization. Targets which want to do tail call optimization 917 /// should override this function. 918 virtual bool IsEligibleForTailCallOptimization(SDOperand Call, 919 SDOperand Ret, 920 SelectionDAG &DAG) const { 921 return false; 922 } 923 924 /// CustomPromoteOperation - This callback is invoked for operations that are 925 /// unsupported by the target, are registered to use 'custom' lowering, and 926 /// whose type needs to be promoted. 927 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 928 929 /// getTargetNodeName() - This method returns the name of a target specific 930 /// DAG node. 931 virtual const char *getTargetNodeName(unsigned Opcode) const; 932 933 //===--------------------------------------------------------------------===// 934 // Inline Asm Support hooks 935 // 936 937 enum ConstraintType { 938 C_Register, // Constraint represents a single register. 939 C_RegisterClass, // Constraint represents one or more registers. 940 C_Memory, // Memory constraint. 941 C_Other, // Something else. 942 C_Unknown // Unsupported constraint. 943 }; 944 945 /// getConstraintType - Given a constraint, return the type of constraint it 946 /// is for this target. 947 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 948 949 950 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 951 /// return a list of registers that can be used to satisfy the constraint. 952 /// This should only be used for C_RegisterClass constraints. 953 virtual std::vector<unsigned> 954 getRegClassForInlineAsmConstraint(const std::string &Constraint, 955 MVT::ValueType VT) const; 956 957 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 958 /// {edx}), return the register number and the register class for the 959 /// register. 960 /// 961 /// Given a register class constraint, like 'r', if this corresponds directly 962 /// to an LLVM register class, return a register of 0 and the register class 963 /// pointer. 964 /// 965 /// This should only be used for C_Register constraints. On error, 966 /// this returns a register number of 0 and a null register class pointer.. 967 virtual std::pair<unsigned, const TargetRegisterClass*> 968 getRegForInlineAsmConstraint(const std::string &Constraint, 969 MVT::ValueType VT) const; 970 971 972 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 973 /// vector. If it is invalid, don't add anything to Ops. 974 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter, 975 std::vector<SDOperand> &Ops, 976 SelectionDAG &DAG); 977 978 //===--------------------------------------------------------------------===// 979 // Scheduler hooks 980 // 981 982 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 983 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 984 // instructions are special in various ways, which require special support to 985 // insert. The specified MachineInstr is created but not inserted into any 986 // basic blocks, and the scheduler passes ownership of it to this method. 987 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 988 MachineBasicBlock *MBB); 989 990 //===--------------------------------------------------------------------===// 991 // Addressing mode description hooks (used by LSR etc). 992 // 993 994 /// AddrMode - This represents an addressing mode of: 995 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 996 /// If BaseGV is null, there is no BaseGV. 997 /// If BaseOffs is zero, there is no base offset. 998 /// If HasBaseReg is false, there is no base register. 999 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1000 /// no scale. 1001 /// 1002 struct AddrMode { 1003 GlobalValue *BaseGV; 1004 int64_t BaseOffs; 1005 bool HasBaseReg; 1006 int64_t Scale; 1007 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1008 }; 1009 1010 /// isLegalAddressingMode - Return true if the addressing mode represented by 1011 /// AM is legal for this target, for a load/store of the specified type. 1012 /// TODO: Handle pre/postinc as well. 1013 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1014 1015 /// isTruncateFree - Return true if it's free to truncate a value of 1016 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1017 /// register EAX to i16 by referencing its sub-register AX. 1018 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1019 return false; 1020 } 1021 1022 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const { 1023 return false; 1024 } 1025 1026 //===--------------------------------------------------------------------===// 1027 // Div utility functions 1028 // 1029 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 1030 std::vector<SDNode*>* Created) const; 1031 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 1032 std::vector<SDNode*>* Created) const; 1033 1034 1035 //===--------------------------------------------------------------------===// 1036 // Runtime Library hooks 1037 // 1038 1039 /// setLibcallName - Rename the default libcall routine name for the specified 1040 /// libcall. 1041 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1042 LibcallRoutineNames[Call] = Name; 1043 } 1044 1045 /// getLibcallName - Get the libcall routine name for the specified libcall. 1046 /// 1047 const char *getLibcallName(RTLIB::Libcall Call) const { 1048 return LibcallRoutineNames[Call]; 1049 } 1050 1051 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1052 /// result of the comparison libcall against zero. 1053 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1054 CmpLibcallCCs[Call] = CC; 1055 } 1056 1057 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1058 /// the comparison libcall against zero. 1059 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1060 return CmpLibcallCCs[Call]; 1061 } 1062 1063private: 1064 TargetMachine &TM; 1065 const TargetData *TD; 1066 1067 /// IsLittleEndian - True if this is a little endian target. 1068 /// 1069 bool IsLittleEndian; 1070 1071 /// PointerTy - The type to use for pointers, usually i32 or i64. 1072 /// 1073 MVT::ValueType PointerTy; 1074 1075 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1076 /// 1077 bool UsesGlobalOffsetTable; 1078 1079 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1080 /// PointerTy is. 1081 MVT::ValueType ShiftAmountTy; 1082 1083 OutOfRangeShiftAmount ShiftAmtHandling; 1084 1085 /// SelectIsExpensive - Tells the code generator not to expand operations 1086 /// into sequences that use the select operations if possible. 1087 bool SelectIsExpensive; 1088 1089 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1090 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1091 /// a real cost model is in place. If we ever optimize for size, this will be 1092 /// set to true unconditionally. 1093 bool IntDivIsCheap; 1094 1095 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1096 /// srl/add/sra for a signed divide by power of two, and let the target handle 1097 /// it. 1098 bool Pow2DivIsCheap; 1099 1100 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 1101 /// PointerTy. 1102 MVT::ValueType SetCCResultTy; 1103 1104 /// SetCCResultContents - Information about the contents of the high-bits in 1105 /// the result of a setcc comparison operation. 1106 SetCCResultValue SetCCResultContents; 1107 1108 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1109 /// total cycles or lowest register usage. 1110 SchedPreference SchedPreferenceInfo; 1111 1112 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1113 /// llvm.setjmp. Defaults to false. 1114 bool UseUnderscoreSetJmp; 1115 1116 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1117 /// llvm.longjmp. Defaults to false. 1118 bool UseUnderscoreLongJmp; 1119 1120 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1121 unsigned JumpBufSize; 1122 1123 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1124 /// buffers 1125 unsigned JumpBufAlignment; 1126 1127 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1128 /// if-converted. 1129 unsigned IfCvtBlockSizeLimit; 1130 1131 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1132 /// duplicated during if-conversion. 1133 unsigned IfCvtDupBlockSizeLimit; 1134 1135 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1136 /// specifies the register that llvm.savestack/llvm.restorestack should save 1137 /// and restore. 1138 unsigned StackPointerRegisterToSaveRestore; 1139 1140 /// ExceptionPointerRegister - If set to a physical register, this specifies 1141 /// the register that receives the exception address on entry to a landing 1142 /// pad. 1143 unsigned ExceptionPointerRegister; 1144 1145 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1146 /// the register that receives the exception typeid on entry to a landing 1147 /// pad. 1148 unsigned ExceptionSelectorRegister; 1149 1150 /// RegClassForVT - This indicates the default register class to use for 1151 /// each ValueType the target supports natively. 1152 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1153 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1154 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1155 1156 /// TransformToType - For any value types we are promoting or expanding, this 1157 /// contains the value type that we are changing to. For Expanded types, this 1158 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1159 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1160 /// by the system, this holds the same type (e.g. i32 -> i32). 1161 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1162 1163 /// OpActions - For each operation and each value type, keep a LegalizeAction 1164 /// that indicates how instruction selection should deal with the operation. 1165 /// Most operations are Legal (aka, supported natively by the target), but 1166 /// operations that are not should be described. Note that operations on 1167 /// non-legal value types are not described here. 1168 uint64_t OpActions[156]; 1169 1170 /// LoadXActions - For each load of load extension type and each value type, 1171 /// keep a LegalizeAction that indicates how instruction selection should deal 1172 /// with the load. 1173 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1174 1175 /// StoreXActions - For each store with truncation of each value type, keep a 1176 /// LegalizeAction that indicates how instruction selection should deal with 1177 /// the store. 1178 uint64_t StoreXActions; 1179 1180 /// IndexedModeActions - For each indexed mode and each value type, keep a 1181 /// pair of LegalizeAction that indicates how instruction selection should 1182 /// deal with the load / store. 1183 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1184 1185 /// ConvertActions - For each conversion from source type to destination type, 1186 /// keep a LegalizeAction that indicates how instruction selection should 1187 /// deal with the conversion. 1188 /// Currently, this is used only for floating->floating conversions 1189 /// (FP_EXTEND and FP_ROUND). 1190 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1191 1192 ValueTypeActionImpl ValueTypeActions; 1193 1194 std::vector<APFloat> LegalFPImmediates; 1195 1196 std::vector<std::pair<MVT::ValueType, 1197 TargetRegisterClass*> > AvailableRegClasses; 1198 1199 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1200 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1201 /// which sets a bit in this array. 1202 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1203 1204 /// PromoteToType - For operations that must be promoted to a specific type, 1205 /// this holds the destination type. This map should be sparse, so don't hold 1206 /// it as an array. 1207 /// 1208 /// Targets add entries to this map with AddPromotedToType(..), clients access 1209 /// this with getTypeToPromoteTo(..). 1210 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1211 1212 /// LibcallRoutineNames - Stores the name each libcall. 1213 /// 1214 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1215 1216 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1217 /// of each of the comparison libcall against zero. 1218 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1219 1220protected: 1221 /// When lowering %llvm.memset this field specifies the maximum number of 1222 /// store operations that may be substituted for the call to memset. Targets 1223 /// must set this value based on the cost threshold for that target. Targets 1224 /// should assume that the memset will be done using as many of the largest 1225 /// store operations first, followed by smaller ones, if necessary, per 1226 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1227 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1228 /// store. This only applies to setting a constant array of a constant size. 1229 /// @brief Specify maximum number of store instructions per memset call. 1230 unsigned maxStoresPerMemset; 1231 1232 /// When lowering %llvm.memcpy this field specifies the maximum number of 1233 /// store operations that may be substituted for a call to memcpy. Targets 1234 /// must set this value based on the cost threshold for that target. Targets 1235 /// should assume that the memcpy will be done using as many of the largest 1236 /// store operations first, followed by smaller ones, if necessary, per 1237 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1238 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1239 /// and one 1-byte store. This only applies to copying a constant array of 1240 /// constant size. 1241 /// @brief Specify maximum bytes of store instructions per memcpy call. 1242 unsigned maxStoresPerMemcpy; 1243 1244 /// When lowering %llvm.memmove this field specifies the maximum number of 1245 /// store instructions that may be substituted for a call to memmove. Targets 1246 /// must set this value based on the cost threshold for that target. Targets 1247 /// should assume that the memmove will be done using as many of the largest 1248 /// store operations first, followed by smaller ones, if necessary, per 1249 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1250 /// with 8-bit alignment would result in nine 1-byte stores. This only 1251 /// applies to copying a constant array of constant size. 1252 /// @brief Specify maximum bytes of store instructions per memmove call. 1253 unsigned maxStoresPerMemmove; 1254 1255 /// This field specifies whether the target machine permits unaligned memory 1256 /// accesses. This is used, for example, to determine the size of store 1257 /// operations when copying small arrays and other similar tasks. 1258 /// @brief Indicate whether the target permits unaligned memory accesses. 1259 bool allowUnalignedMemoryAccesses; 1260}; 1261} // end llvm namespace 1262 1263#endif 1264