TargetLowering.h revision a54b7cbd452b3adb2f51346140d996b29c2cdb30
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/DerivedTypes.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include <map> 28 29namespace llvm { 30 class Value; 31 class Function; 32 class TargetMachine; 33 class TargetData; 34 class TargetRegisterClass; 35 class SDNode; 36 class SDOperand; 37 class SelectionDAG; 38 class MachineBasicBlock; 39 class MachineInstr; 40 41namespace RTLIB { 42 /// RTLIB::Libcall enum - This enum defines all of the runtime library calls 43 /// the backend can emit. 44 /// 45 enum Libcall { 46 // Integer 47 SHL_I32, 48 SHL_I64, 49 SRL_I32, 50 SRL_I64, 51 SRA_I32, 52 SRA_I64, 53 MUL_I32, 54 MUL_I64, 55 SDIV_I32, 56 SDIV_I64, 57 UDIV_I32, 58 UDIV_I64, 59 SREM_I32, 60 SREM_I64, 61 UREM_I32, 62 UREM_I64, 63 NEG_I32, 64 NEG_I64, 65 66 // FLOATING POINT 67 ADD_F32, 68 ADD_F64, 69 SUB_F32, 70 SUB_F64, 71 MUL_F32, 72 MUL_F64, 73 DIV_F32, 74 DIV_F64, 75 REM_F32, 76 REM_F64, 77 NEG_F32, 78 NEG_F64, 79 POWI_F32, 80 POWI_F64, 81 SQRT_F32, 82 SQRT_F64, 83 SIN_F32, 84 SIN_F64, 85 COS_F32, 86 COS_F64, 87 88 // CONVERSION 89 FPEXT_F32_F64, 90 FPROUND_F64_F32, 91 FPTOSINT_F32_I32, 92 FPTOSINT_F32_I64, 93 FPTOSINT_F64_I32, 94 FPTOSINT_F64_I64, 95 FPTOUINT_F32_I32, 96 FPTOUINT_F32_I64, 97 FPTOUINT_F64_I32, 98 FPTOUINT_F64_I64, 99 SINTTOFP_I32_F32, 100 SINTTOFP_I32_F64, 101 SINTTOFP_I64_F32, 102 SINTTOFP_I64_F64, 103 UINTTOFP_I32_F32, 104 UINTTOFP_I32_F64, 105 UINTTOFP_I64_F32, 106 UINTTOFP_I64_F64, 107 108 // COMPARISON 109 OEQ_F32, 110 OEQ_F64, 111 UNE_F32, 112 UNE_F64, 113 OGE_F32, 114 OGE_F64, 115 OLT_F32, 116 OLT_F64, 117 OLE_F32, 118 OLE_F64, 119 OGT_F32, 120 OGT_F64, 121 UO_F32, 122 UO_F64, 123 124 UNKNOWN_LIBCALL 125 }; 126 } 127 128//===----------------------------------------------------------------------===// 129/// TargetLowering - This class defines information used to lower LLVM code to 130/// legal SelectionDAG operators that the target instruction selector can accept 131/// natively. 132/// 133/// This class also defines callbacks that targets must implement to lower 134/// target-specific constructs to SelectionDAG operators. 135/// 136class TargetLowering { 137public: 138 /// LegalizeAction - This enum indicates whether operations are valid for a 139 /// target, and if not, what action should be used to make them valid. 140 enum LegalizeAction { 141 Legal, // The target natively supports this operation. 142 Promote, // This operation should be executed in a larger type. 143 Expand, // Try to expand this to other ops, otherwise use a libcall. 144 Custom // Use the LowerOperation hook to implement custom lowering. 145 }; 146 147 enum OutOfRangeShiftAmount { 148 Undefined, // Oversized shift amounts are undefined (default). 149 Mask, // Shift amounts are auto masked (anded) to value size. 150 Extend // Oversized shift pulls in zeros or sign bits. 151 }; 152 153 enum SetCCResultValue { 154 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 155 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 156 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 157 }; 158 159 enum SchedPreference { 160 SchedulingForLatency, // Scheduling for shortest total latency. 161 SchedulingForRegPressure // Scheduling for lowest register pressure. 162 }; 163 164 TargetLowering(TargetMachine &TM); 165 virtual ~TargetLowering(); 166 167 TargetMachine &getTargetMachine() const { return TM; } 168 const TargetData *getTargetData() const { return TD; } 169 170 bool isLittleEndian() const { return IsLittleEndian; } 171 MVT::ValueType getPointerTy() const { return PointerTy; } 172 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 173 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 174 175 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 176 /// codegen. 177 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 178 179 /// isSelectExpensive - Return true if the select operation is expensive for 180 /// this target. 181 bool isSelectExpensive() const { return SelectIsExpensive; } 182 183 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 184 /// a sequence of several shifts, adds, and multiplies for this target. 185 bool isIntDivCheap() const { return IntDivIsCheap; } 186 187 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 188 /// srl/add/sra. 189 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 190 191 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 192 /// 193 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 194 195 /// getSetCCResultContents - For targets without boolean registers, this flag 196 /// returns information about the contents of the high-bits in the setcc 197 /// result register. 198 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 199 200 /// getSchedulingPreference - Return target scheduling preference. 201 SchedPreference getSchedulingPreference() const { 202 return SchedPreferenceInfo; 203 } 204 205 /// getRegClassFor - Return the register class that should be used for the 206 /// specified value type. This may only be called on legal types. 207 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 208 TargetRegisterClass *RC = RegClassForVT[VT]; 209 assert(RC && "This value type is not natively supported!"); 210 return RC; 211 } 212 213 /// isTypeLegal - Return true if the target has native support for the 214 /// specified value type. This means that it has a register that directly 215 /// holds it without promotions or expansions. 216 bool isTypeLegal(MVT::ValueType VT) const { 217 return RegClassForVT[VT] != 0; 218 } 219 220 class ValueTypeActionImpl { 221 /// ValueTypeActions - This is a bitvector that contains two bits for each 222 /// value type, where the two bits correspond to the LegalizeAction enum. 223 /// This can be queried with "getTypeAction(VT)". 224 uint32_t ValueTypeActions[2]; 225 public: 226 ValueTypeActionImpl() { 227 ValueTypeActions[0] = ValueTypeActions[1] = 0; 228 } 229 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 230 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 231 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 232 } 233 234 LegalizeAction getTypeAction(MVT::ValueType VT) const { 235 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 236 } 237 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 238 assert(unsigned(VT >> 4) < 239 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 240 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 241 } 242 }; 243 244 const ValueTypeActionImpl &getValueTypeActions() const { 245 return ValueTypeActions; 246 } 247 248 /// getTypeAction - Return how we should legalize values of this type, either 249 /// it is already legal (return 'Legal') or we need to promote it to a larger 250 /// type (return 'Promote'), or we need to expand it into multiple registers 251 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 252 LegalizeAction getTypeAction(MVT::ValueType VT) const { 253 return ValueTypeActions.getTypeAction(VT); 254 } 255 256 /// getTypeToTransformTo - For types supported by the target, this is an 257 /// identity function. For types that must be promoted to larger types, this 258 /// returns the larger type to promote to. For integer types that are larger 259 /// than the largest integer register, this contains one step in the expansion 260 /// to get to the smaller register. For illegal floating point types, this 261 /// returns the integer type to transform to. 262 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 263 return TransformToType[VT]; 264 } 265 266 /// getTypeToExpandTo - For types supported by the target, this is an 267 /// identity function. For types that must be expanded (i.e. integer types 268 /// that are larger than the largest integer register or illegal floating 269 /// point types), this returns the largest legal type it will be expanded to. 270 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 271 while (true) { 272 switch (getTypeAction(VT)) { 273 case Legal: 274 return VT; 275 case Expand: 276 VT = TransformToType[VT]; 277 break; 278 default: 279 assert(false && "Type is not legal nor is it to be expanded!"); 280 return VT; 281 } 282 } 283 return VT; 284 } 285 286 /// getPackedTypeBreakdown - Packed types are broken down into some number of 287 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32 288 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 289 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86. 290 /// 291 /// This method returns the number of registers needed, and the VT for each 292 /// register. It also returns the VT of the PackedType elements before they 293 /// are promoted/expanded. 294 /// 295 unsigned getPackedTypeBreakdown(const PackedType *PTy, 296 MVT::ValueType &PTyElementVT, 297 MVT::ValueType &PTyLegalElementVT) const; 298 299 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 300 legal_fpimm_iterator legal_fpimm_begin() const { 301 return LegalFPImmediates.begin(); 302 } 303 legal_fpimm_iterator legal_fpimm_end() const { 304 return LegalFPImmediates.end(); 305 } 306 307 /// isShuffleMaskLegal - Targets can use this to indicate that they only 308 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 309 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 310 /// are assumed to be legal. 311 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 312 return true; 313 } 314 315 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 316 /// used by Targets can use this to indicate if there is a suitable 317 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 318 /// pool entry. 319 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 320 MVT::ValueType EVT, 321 SelectionDAG &DAG) const { 322 return false; 323 } 324 325 /// getOperationAction - Return how this operation should be treated: either 326 /// it is legal, needs to be promoted to a larger size, needs to be 327 /// expanded to some other code sequence, or the target has a custom expander 328 /// for it. 329 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 330 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 331 } 332 333 /// isOperationLegal - Return true if the specified operation is legal on this 334 /// target. 335 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 336 return getOperationAction(Op, VT) == Legal || 337 getOperationAction(Op, VT) == Custom; 338 } 339 340 /// getLoadXAction - Return how this load with extension should be treated: 341 /// either it is legal, needs to be promoted to a larger size, needs to be 342 /// expanded to some other code sequence, or the target has a custom expander 343 /// for it. 344 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 345 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); 346 } 347 348 /// isLoadXLegal - Return true if the specified load with extension is legal 349 /// on this target. 350 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 351 return getLoadXAction(LType, VT) == Legal || 352 getLoadXAction(LType, VT) == Custom; 353 } 354 355 /// getStoreXAction - Return how this store with truncation should be treated: 356 /// either it is legal, needs to be promoted to a larger size, needs to be 357 /// expanded to some other code sequence, or the target has a custom expander 358 /// for it. 359 LegalizeAction getStoreXAction(MVT::ValueType VT) const { 360 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3); 361 } 362 363 /// isStoreXLegal - Return true if the specified store with truncation is 364 /// legal on this target. 365 bool isStoreXLegal(MVT::ValueType VT) const { 366 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom; 367 } 368 369 /// getIndexedLoadAction - Return how the indexed load should be treated: 370 /// either it is legal, needs to be promoted to a larger size, needs to be 371 /// expanded to some other code sequence, or the target has a custom expander 372 /// for it. 373 LegalizeAction 374 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 375 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); 376 } 377 378 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 379 /// on this target. 380 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 381 return getIndexedLoadAction(IdxMode, VT) == Legal || 382 getIndexedLoadAction(IdxMode, VT) == Custom; 383 } 384 385 /// getIndexedStoreAction - Return how the indexed store should be treated: 386 /// either it is legal, needs to be promoted to a larger size, needs to be 387 /// expanded to some other code sequence, or the target has a custom expander 388 /// for it. 389 LegalizeAction 390 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 391 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); 392 } 393 394 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 395 /// on this target. 396 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 397 return getIndexedStoreAction(IdxMode, VT) == Legal || 398 getIndexedStoreAction(IdxMode, VT) == Custom; 399 } 400 401 /// getTypeToPromoteTo - If the action for this operation is to promote, this 402 /// method returns the ValueType to promote to. 403 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 404 assert(getOperationAction(Op, VT) == Promote && 405 "This operation isn't promoted!"); 406 407 // See if this has an explicit type specified. 408 std::map<std::pair<unsigned, MVT::ValueType>, 409 MVT::ValueType>::const_iterator PTTI = 410 PromoteToType.find(std::make_pair(Op, VT)); 411 if (PTTI != PromoteToType.end()) return PTTI->second; 412 413 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 414 "Cannot autopromote this type, add it with AddPromotedToType."); 415 416 MVT::ValueType NVT = VT; 417 do { 418 NVT = (MVT::ValueType)(NVT+1); 419 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 420 "Didn't find type to promote to!"); 421 } while (!isTypeLegal(NVT) || 422 getOperationAction(Op, NVT) == Promote); 423 return NVT; 424 } 425 426 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 427 /// This is fixed by the LLVM operations except for the pointer size. 428 MVT::ValueType getValueType(const Type *Ty) const { 429 switch (Ty->getTypeID()) { 430 default: assert(0 && "Unknown type!"); 431 case Type::VoidTyID: return MVT::isVoid; 432 case Type::IntegerTyID: 433 switch (cast<IntegerType>(Ty)->getBitWidth()) { 434 default: assert(0 && "Invalid width for value type"); 435 case 1: return MVT::i1; 436 case 8: return MVT::i8; 437 case 16: return MVT::i16; 438 case 32: return MVT::i32; 439 case 64: return MVT::i64; 440 } 441 break; 442 case Type::FloatTyID: return MVT::f32; 443 case Type::DoubleTyID: return MVT::f64; 444 case Type::PointerTyID: return PointerTy; 445 case Type::PackedTyID: return MVT::Vector; 446 } 447 } 448 449 /// getNumElements - Return the number of registers that this ValueType will 450 /// eventually require. This is one for any types promoted to live in larger 451 /// registers, but may be more than one for types (like i64) that are split 452 /// into pieces. 453 unsigned getNumElements(MVT::ValueType VT) const { 454 return NumElementsForVT[VT]; 455 } 456 457 /// hasTargetDAGCombine - If true, the target has custom DAG combine 458 /// transformations that it can perform for the specified node. 459 bool hasTargetDAGCombine(ISD::NodeType NT) const { 460 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 461 } 462 463 /// This function returns the maximum number of store operations permitted 464 /// to replace a call to llvm.memset. The value is set by the target at the 465 /// performance threshold for such a replacement. 466 /// @brief Get maximum # of store operations permitted for llvm.memset 467 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 468 469 /// This function returns the maximum number of store operations permitted 470 /// to replace a call to llvm.memcpy. The value is set by the target at the 471 /// performance threshold for such a replacement. 472 /// @brief Get maximum # of store operations permitted for llvm.memcpy 473 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 474 475 /// This function returns the maximum number of store operations permitted 476 /// to replace a call to llvm.memmove. The value is set by the target at the 477 /// performance threshold for such a replacement. 478 /// @brief Get maximum # of store operations permitted for llvm.memmove 479 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 480 481 /// This function returns true if the target allows unaligned memory accesses. 482 /// This is used, for example, in situations where an array copy/move/set is 483 /// converted to a sequence of store operations. It's use helps to ensure that 484 /// such replacements don't generate code that causes an alignment error 485 /// (trap) on the target machine. 486 /// @brief Determine if the target supports unaligned memory accesses. 487 bool allowsUnalignedMemoryAccesses() const { 488 return allowUnalignedMemoryAccesses; 489 } 490 491 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 492 /// to implement llvm.setjmp. 493 bool usesUnderscoreSetJmp() const { 494 return UseUnderscoreSetJmp; 495 } 496 497 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 498 /// to implement llvm.longjmp. 499 bool usesUnderscoreLongJmp() const { 500 return UseUnderscoreLongJmp; 501 } 502 503 /// getStackPointerRegisterToSaveRestore - If a physical register, this 504 /// specifies the register that llvm.savestack/llvm.restorestack should save 505 /// and restore. 506 unsigned getStackPointerRegisterToSaveRestore() const { 507 return StackPointerRegisterToSaveRestore; 508 } 509 510 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 511 /// set, the default is 200) 512 unsigned getJumpBufSize() const { 513 return JumpBufSize; 514 } 515 516 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 517 /// (if never set, the default is 0) 518 unsigned getJumpBufAlignment() const { 519 return JumpBufAlignment; 520 } 521 522 /// getPreIndexedAddressParts - returns true by value, base pointer and 523 /// offset pointer and addressing mode by reference if the node's address 524 /// can be legally represented as pre-indexed load / store address. 525 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 526 SDOperand &Offset, 527 ISD::MemIndexedMode &AM, 528 SelectionDAG &DAG) { 529 return false; 530 } 531 532 /// getPostIndexedAddressParts - returns true by value, base pointer and 533 /// offset pointer and addressing mode by reference if this node can be 534 /// combined with a load / store to form a post-indexed load / store. 535 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 536 SDOperand &Base, SDOperand &Offset, 537 ISD::MemIndexedMode &AM, 538 SelectionDAG &DAG) { 539 return false; 540 } 541 542 //===--------------------------------------------------------------------===// 543 // TargetLowering Optimization Methods 544 // 545 546 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 547 /// SDOperands for returning information from TargetLowering to its clients 548 /// that want to combine 549 struct TargetLoweringOpt { 550 SelectionDAG &DAG; 551 SDOperand Old; 552 SDOperand New; 553 554 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 555 556 bool CombineTo(SDOperand O, SDOperand N) { 557 Old = O; 558 New = N; 559 return true; 560 } 561 562 /// ShrinkDemandedConstant - Check to see if the specified operand of the 563 /// specified instruction is a constant integer. If so, check to see if there 564 /// are any bits set in the constant that are not demanded. If so, shrink the 565 /// constant and return true. 566 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 567 }; 568 569 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We 570 /// use this predicate to simplify operations downstream. Op and Mask are 571 /// known to be the same type. 572 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) 573 const; 574 575 /// ComputeMaskedBits - Determine which of the bits specified in Mask are 576 /// known to be either zero or one and return them in the KnownZero/KnownOne 577 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit 578 /// processing. Targets can implement the computeMaskedBitsForTargetNode 579 /// method, to allow target nodes to be understood. 580 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, 581 uint64_t &KnownOne, unsigned Depth = 0) const; 582 583 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 584 /// DemandedMask bits of the result of Op are ever used downstream. If we can 585 /// use this information to simplify Op, create a new simplified DAG node and 586 /// return true, returning the original and new nodes in Old and New. 587 /// Otherwise, analyze the expression and return a mask of KnownOne and 588 /// KnownZero bits for the expression (used to simplify the caller). 589 /// The KnownZero/One bits may only be accurate for those bits in the 590 /// DemandedMask. 591 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 592 uint64_t &KnownZero, uint64_t &KnownOne, 593 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 594 595 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 596 /// Mask are known to be either zero or one and return them in the 597 /// KnownZero/KnownOne bitsets. 598 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 599 uint64_t Mask, 600 uint64_t &KnownZero, 601 uint64_t &KnownOne, 602 unsigned Depth = 0) const; 603 604 /// ComputeNumSignBits - Return the number of times the sign bit of the 605 /// register is replicated into the other bits. We know that at least 1 bit 606 /// is always equal to the sign bit (itself), but other cases can give us 607 /// information. For example, immediately after an "SRA X, 2", we know that 608 /// the top 3 bits are all equal to each other, so we return 3. 609 unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const; 610 611 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 612 /// targets that want to expose additional information about sign bits to the 613 /// DAG Combiner. 614 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 615 unsigned Depth = 0) const; 616 617 struct DAGCombinerInfo { 618 void *DC; // The DAG Combiner object. 619 bool BeforeLegalize; 620 public: 621 SelectionDAG &DAG; 622 623 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc) 624 : DC(dc), BeforeLegalize(bl), DAG(dag) {} 625 626 bool isBeforeLegalize() const { return BeforeLegalize; } 627 628 void AddToWorklist(SDNode *N); 629 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 630 SDOperand CombineTo(SDNode *N, SDOperand Res); 631 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 632 }; 633 634 /// PerformDAGCombine - This method will be invoked for all target nodes and 635 /// for any target-independent nodes that the target has registered with 636 /// invoke it for. 637 /// 638 /// The semantics are as follows: 639 /// Return Value: 640 /// SDOperand.Val == 0 - No change was made 641 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 642 /// otherwise - N should be replaced by the returned Operand. 643 /// 644 /// In addition, methods provided by DAGCombinerInfo may be used to perform 645 /// more complex transformations. 646 /// 647 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 648 649 //===--------------------------------------------------------------------===// 650 // TargetLowering Configuration Methods - These methods should be invoked by 651 // the derived class constructor to configure this object for the target. 652 // 653 654protected: 655 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 656 /// GOT for PC-relative code. 657 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 658 659 /// setShiftAmountType - Describe the type that should be used for shift 660 /// amounts. This type defaults to the pointer type. 661 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 662 663 /// setSetCCResultType - Describe the type that shoudl be used as the result 664 /// of a setcc operation. This defaults to the pointer type. 665 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 666 667 /// setSetCCResultContents - Specify how the target extends the result of a 668 /// setcc operation in a register. 669 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 670 671 /// setSchedulingPreference - Specify the target scheduling preference. 672 void setSchedulingPreference(SchedPreference Pref) { 673 SchedPreferenceInfo = Pref; 674 } 675 676 /// setShiftAmountFlavor - Describe how the target handles out of range shift 677 /// amounts. 678 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 679 ShiftAmtHandling = OORSA; 680 } 681 682 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 683 /// use _setjmp to implement llvm.setjmp or the non _ version. 684 /// Defaults to false. 685 void setUseUnderscoreSetJmp(bool Val) { 686 UseUnderscoreSetJmp = Val; 687 } 688 689 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 690 /// use _longjmp to implement llvm.longjmp or the non _ version. 691 /// Defaults to false. 692 void setUseUnderscoreLongJmp(bool Val) { 693 UseUnderscoreLongJmp = Val; 694 } 695 696 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 697 /// specifies the register that llvm.savestack/llvm.restorestack should save 698 /// and restore. 699 void setStackPointerRegisterToSaveRestore(unsigned R) { 700 StackPointerRegisterToSaveRestore = R; 701 } 702 703 /// SelectIsExpensive - Tells the code generator not to expand operations 704 /// into sequences that use the select operations if possible. 705 void setSelectIsExpensive() { SelectIsExpensive = true; } 706 707 /// setIntDivIsCheap - Tells the code generator that integer divide is 708 /// expensive, and if possible, should be replaced by an alternate sequence 709 /// of instructions not containing an integer divide. 710 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 711 712 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 713 /// srl/add/sra for a signed divide by power of two, and let the target handle 714 /// it. 715 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 716 717 /// addRegisterClass - Add the specified register class as an available 718 /// regclass for the specified value type. This indicates the selector can 719 /// handle values of that class natively. 720 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 721 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 722 RegClassForVT[VT] = RC; 723 } 724 725 /// computeRegisterProperties - Once all of the register classes are added, 726 /// this allows us to compute derived properties we expose. 727 void computeRegisterProperties(); 728 729 /// setOperationAction - Indicate that the specified operation does not work 730 /// with the specified type and indicate what to do about it. 731 void setOperationAction(unsigned Op, MVT::ValueType VT, 732 LegalizeAction Action) { 733 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 734 "Table isn't big enough!"); 735 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 736 OpActions[Op] |= (uint64_t)Action << VT*2; 737 } 738 739 /// setLoadXAction - Indicate that the specified load with extension does not 740 /// work with the with specified type and indicate what to do about it. 741 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 742 LegalizeAction Action) { 743 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) && 744 "Table isn't big enough!"); 745 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 746 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 747 } 748 749 /// setStoreXAction - Indicate that the specified store with truncation does 750 /// not work with the with specified type and indicate what to do about it. 751 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) { 752 assert(VT < 32 && "Table isn't big enough!"); 753 StoreXActions &= ~(uint64_t(3UL) << VT*2); 754 StoreXActions |= (uint64_t)Action << VT*2; 755 } 756 757 /// setIndexedLoadAction - Indicate that the specified indexed load does or 758 /// does not work with the with specified type and indicate what to do abort 759 /// it. NOTE: All indexed mode loads are initialized to Expand in 760 /// TargetLowering.cpp 761 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 762 LegalizeAction Action) { 763 assert(VT < 32 && IdxMode < 764 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) && 765 "Table isn't big enough!"); 766 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 767 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 768 } 769 770 /// setIndexedStoreAction - Indicate that the specified indexed store does or 771 /// does not work with the with specified type and indicate what to do about 772 /// it. NOTE: All indexed mode stores are initialized to Expand in 773 /// TargetLowering.cpp 774 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 775 LegalizeAction Action) { 776 assert(VT < 32 && IdxMode < 777 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) && 778 "Table isn't big enough!"); 779 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 780 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 781 } 782 783 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 784 /// promotion code defaults to trying a larger integer/fp until it can find 785 /// one that works. If that default is insufficient, this method can be used 786 /// by the target to override the default. 787 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 788 MVT::ValueType DestVT) { 789 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 790 } 791 792 /// addLegalFPImmediate - Indicate that this target can instruction select 793 /// the specified FP immediate natively. 794 void addLegalFPImmediate(double Imm) { 795 LegalFPImmediates.push_back(Imm); 796 } 797 798 /// setTargetDAGCombine - Targets should invoke this method for each target 799 /// independent node that they want to provide a custom DAG combiner for by 800 /// implementing the PerformDAGCombine virtual method. 801 void setTargetDAGCombine(ISD::NodeType NT) { 802 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 803 } 804 805 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 806 /// bytes); default is 200 807 void setJumpBufSize(unsigned Size) { 808 JumpBufSize = Size; 809 } 810 811 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 812 /// alignment (in bytes); default is 0 813 void setJumpBufAlignment(unsigned Align) { 814 JumpBufAlignment = Align; 815 } 816 817public: 818 819 //===--------------------------------------------------------------------===// 820 // Lowering methods - These methods must be implemented by targets so that 821 // the SelectionDAGLowering code knows how to lower these. 822 // 823 824 /// LowerArguments - This hook must be implemented to indicate how we should 825 /// lower the arguments for the specified function, into the specified DAG. 826 virtual std::vector<SDOperand> 827 LowerArguments(Function &F, SelectionDAG &DAG); 828 829 /// LowerCallTo - This hook lowers an abstract call to a function into an 830 /// actual call. This returns a pair of operands. The first element is the 831 /// return value for the function (if RetTy is not VoidTy). The second 832 /// element is the outgoing token chain. 833 struct ArgListEntry { 834 SDOperand Node; 835 const Type* Ty; 836 bool isSigned; 837 }; 838 typedef std::vector<ArgListEntry> ArgListTy; 839 virtual std::pair<SDOperand, SDOperand> 840 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 841 bool isVarArg, unsigned CallingConv, bool isTailCall, 842 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 843 844 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or 845 /// llvm.frameaddress (depending on the value of the first argument). The 846 /// return values are the result pointer and the resultant token chain. If 847 /// not implemented, both of these intrinsics will return null. 848 virtual std::pair<SDOperand, SDOperand> 849 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 850 SelectionDAG &DAG); 851 852 /// LowerOperation - This callback is invoked for operations that are 853 /// unsupported by the target, which are registered to use 'custom' lowering, 854 /// and whose defined values are all legal. 855 /// If the target has no operations that require custom lowering, it need not 856 /// implement this. The default implementation of this aborts. 857 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 858 859 /// CustomPromoteOperation - This callback is invoked for operations that are 860 /// unsupported by the target, are registered to use 'custom' lowering, and 861 /// whose type needs to be promoted. 862 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 863 864 /// getTargetNodeName() - This method returns the name of a target specific 865 /// DAG node. 866 virtual const char *getTargetNodeName(unsigned Opcode) const; 867 868 //===--------------------------------------------------------------------===// 869 // Inline Asm Support hooks 870 // 871 872 enum ConstraintType { 873 C_Register, // Constraint represents a single register. 874 C_RegisterClass, // Constraint represents one or more registers. 875 C_Memory, // Memory constraint. 876 C_Other, // Something else. 877 C_Unknown // Unsupported constraint. 878 }; 879 880 /// getConstraintType - Given a constraint letter, return the type of 881 /// constraint it is for this target. 882 virtual ConstraintType getConstraintType(char ConstraintLetter) const; 883 884 885 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 886 /// return a list of registers that can be used to satisfy the constraint. 887 /// This should only be used for C_RegisterClass constraints. 888 virtual std::vector<unsigned> 889 getRegClassForInlineAsmConstraint(const std::string &Constraint, 890 MVT::ValueType VT) const; 891 892 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 893 /// {edx}), return the register number and the register class for the 894 /// register. 895 /// 896 /// Given a register class constraint, like 'r', if this corresponds directly 897 /// to an LLVM register class, return a register of 0 and the register class 898 /// pointer. 899 /// 900 /// This should only be used for C_Register constraints. On error, 901 /// this returns a register number of 0 and a null register class pointer.. 902 virtual std::pair<unsigned, const TargetRegisterClass*> 903 getRegForInlineAsmConstraint(const std::string &Constraint, 904 MVT::ValueType VT) const; 905 906 907 /// isOperandValidForConstraint - Return the specified operand (possibly 908 /// modified) if the specified SDOperand is valid for the specified target 909 /// constraint letter, otherwise return null. 910 virtual SDOperand 911 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter, 912 SelectionDAG &DAG); 913 914 //===--------------------------------------------------------------------===// 915 // Scheduler hooks 916 // 917 918 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 919 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 920 // instructions are special in various ways, which require special support to 921 // insert. The specified MachineInstr is created but not inserted into any 922 // basic blocks, and the scheduler passes ownership of it to this method. 923 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 924 MachineBasicBlock *MBB); 925 926 //===--------------------------------------------------------------------===// 927 // Loop Strength Reduction hooks 928 // 929 930 /// isLegalAddressImmediate - Return true if the integer value or GlobalValue 931 /// can be used as the offset of the target addressing mode. 932 virtual bool isLegalAddressImmediate(int64_t V) const; 933 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 934 935 typedef std::vector<unsigned>::const_iterator legal_am_scale_iterator; 936 legal_am_scale_iterator legal_am_scale_begin() const { 937 return LegalAddressScales.begin(); 938 } 939 legal_am_scale_iterator legal_am_scale_end() const { 940 return LegalAddressScales.end(); 941 } 942 943 //===--------------------------------------------------------------------===// 944 // Div utility functions 945 // 946 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 947 std::vector<SDNode*>* Created) const; 948 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 949 std::vector<SDNode*>* Created) const; 950 951 952 //===--------------------------------------------------------------------===// 953 // Runtime Library hooks 954 // 955 956 /// setLibcallName - Rename the default libcall routine name for the specified 957 /// libcall. 958 void setLibcallName(RTLIB::Libcall Call, std::string Name) { 959 LibcallRoutineNames[Call] = Name; 960 } 961 962 /// getLibcallName - Get the libcall routine name for the specified libcall. 963 /// 964 const char *getLibcallName(RTLIB::Libcall Call) const { 965 return LibcallRoutineNames[Call].c_str(); 966 } 967 968protected: 969 /// addLegalAddressScale - Add a integer (> 1) value which can be used as 970 /// scale in the target addressing mode. Note: the ordering matters so the 971 /// least efficient ones should be entered first. 972 void addLegalAddressScale(unsigned Scale) { 973 LegalAddressScales.push_back(Scale); 974 } 975 976private: 977 std::vector<unsigned> LegalAddressScales; 978 979 TargetMachine &TM; 980 const TargetData *TD; 981 982 /// IsLittleEndian - True if this is a little endian target. 983 /// 984 bool IsLittleEndian; 985 986 /// PointerTy - The type to use for pointers, usually i32 or i64. 987 /// 988 MVT::ValueType PointerTy; 989 990 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 991 /// 992 bool UsesGlobalOffsetTable; 993 994 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 995 /// PointerTy is. 996 MVT::ValueType ShiftAmountTy; 997 998 OutOfRangeShiftAmount ShiftAmtHandling; 999 1000 /// SelectIsExpensive - Tells the code generator not to expand operations 1001 /// into sequences that use the select operations if possible. 1002 bool SelectIsExpensive; 1003 1004 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1005 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1006 /// a real cost model is in place. If we ever optimize for size, this will be 1007 /// set to true unconditionally. 1008 bool IntDivIsCheap; 1009 1010 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1011 /// srl/add/sra for a signed divide by power of two, and let the target handle 1012 /// it. 1013 bool Pow2DivIsCheap; 1014 1015 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 1016 /// PointerTy. 1017 MVT::ValueType SetCCResultTy; 1018 1019 /// SetCCResultContents - Information about the contents of the high-bits in 1020 /// the result of a setcc comparison operation. 1021 SetCCResultValue SetCCResultContents; 1022 1023 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1024 /// total cycles or lowest register usage. 1025 SchedPreference SchedPreferenceInfo; 1026 1027 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1028 /// llvm.setjmp. Defaults to false. 1029 bool UseUnderscoreSetJmp; 1030 1031 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1032 /// llvm.longjmp. Defaults to false. 1033 bool UseUnderscoreLongJmp; 1034 1035 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1036 unsigned JumpBufSize; 1037 1038 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1039 /// buffers 1040 unsigned JumpBufAlignment; 1041 1042 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1043 /// specifies the register that llvm.savestack/llvm.restorestack should save 1044 /// and restore. 1045 unsigned StackPointerRegisterToSaveRestore; 1046 1047 /// RegClassForVT - This indicates the default register class to use for 1048 /// each ValueType the target supports natively. 1049 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1050 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; 1051 1052 /// TransformToType - For any value types we are promoting or expanding, this 1053 /// contains the value type that we are changing to. For Expanded types, this 1054 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1055 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1056 /// by the system, this holds the same type (e.g. i32 -> i32). 1057 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1058 1059 /// OpActions - For each operation and each value type, keep a LegalizeAction 1060 /// that indicates how instruction selection should deal with the operation. 1061 /// Most operations are Legal (aka, supported natively by the target), but 1062 /// operations that are not should be described. Note that operations on 1063 /// non-legal value types are not described here. 1064 uint64_t OpActions[156]; 1065 1066 /// LoadXActions - For each load of load extension type and each value type, 1067 /// keep a LegalizeAction that indicates how instruction selection should deal 1068 /// with the load. 1069 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1070 1071 /// StoreXActions - For each store with truncation of each value type, keep a 1072 /// LegalizeAction that indicates how instruction selection should deal with 1073 /// the store. 1074 uint64_t StoreXActions; 1075 1076 /// IndexedModeActions - For each indexed mode and each value type, keep a 1077 /// pair of LegalizeAction that indicates how instruction selection should 1078 /// deal with the load / store. 1079 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1080 1081 ValueTypeActionImpl ValueTypeActions; 1082 1083 std::vector<double> LegalFPImmediates; 1084 1085 std::vector<std::pair<MVT::ValueType, 1086 TargetRegisterClass*> > AvailableRegClasses; 1087 1088 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1089 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1090 /// which sets a bit in this array. 1091 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1092 1093 /// PromoteToType - For operations that must be promoted to a specific type, 1094 /// this holds the destination type. This map should be sparse, so don't hold 1095 /// it as an array. 1096 /// 1097 /// Targets add entries to this map with AddPromotedToType(..), clients access 1098 /// this with getTypeToPromoteTo(..). 1099 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1100 1101 /// LibcallRoutineNames - Stores the name each libcall. 1102 /// 1103 std::string LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1104 1105protected: 1106 /// When lowering %llvm.memset this field specifies the maximum number of 1107 /// store operations that may be substituted for the call to memset. Targets 1108 /// must set this value based on the cost threshold for that target. Targets 1109 /// should assume that the memset will be done using as many of the largest 1110 /// store operations first, followed by smaller ones, if necessary, per 1111 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1112 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1113 /// store. This only applies to setting a constant array of a constant size. 1114 /// @brief Specify maximum number of store instructions per memset call. 1115 unsigned maxStoresPerMemset; 1116 1117 /// When lowering %llvm.memcpy this field specifies the maximum number of 1118 /// store operations that may be substituted for a call to memcpy. Targets 1119 /// must set this value based on the cost threshold for that target. Targets 1120 /// should assume that the memcpy will be done using as many of the largest 1121 /// store operations first, followed by smaller ones, if necessary, per 1122 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1123 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1124 /// and one 1-byte store. This only applies to copying a constant array of 1125 /// constant size. 1126 /// @brief Specify maximum bytes of store instructions per memcpy call. 1127 unsigned maxStoresPerMemcpy; 1128 1129 /// When lowering %llvm.memmove this field specifies the maximum number of 1130 /// store instructions that may be substituted for a call to memmove. Targets 1131 /// must set this value based on the cost threshold for that target. Targets 1132 /// should assume that the memmove will be done using as many of the largest 1133 /// store operations first, followed by smaller ones, if necessary, per 1134 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1135 /// with 8-bit alignment would result in nine 1-byte stores. This only 1136 /// applies to copying a constant array of constant size. 1137 /// @brief Specify maximum bytes of store instructions per memmove call. 1138 unsigned maxStoresPerMemmove; 1139 1140 /// This field specifies whether the target machine permits unaligned memory 1141 /// accesses. This is used, for example, to determine the size of store 1142 /// operations when copying small arrays and other similar tasks. 1143 /// @brief Indicate whether the target permits unaligned memory accesses. 1144 bool allowUnalignedMemoryAccesses; 1145}; 1146} // end llvm namespace 1147 1148#endif 1149