TargetLowering.h revision aafe626c7fa9f99150cccd27d0151a2cf7c8c00b
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Attributes.h" 28#include "llvm/CodeGen/SelectionDAGNodes.h" 29#include "llvm/CodeGen/RuntimeLibcalls.h" 30#include "llvm/ADT/APFloat.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/SmallSet.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/STLExtras.h" 35#include "llvm/Support/DebugLoc.h" 36#include "llvm/Target/TargetCallingConv.h" 37#include "llvm/Target/TargetMachine.h" 38#include <climits> 39#include <map> 40#include <vector> 41 42namespace llvm { 43 class AllocaInst; 44 class CallInst; 45 class Function; 46 class FastISel; 47 class FunctionLoweringInfo; 48 class MachineBasicBlock; 49 class MachineFunction; 50 class MachineFrameInfo; 51 class MachineInstr; 52 class MachineJumpTableInfo; 53 class MCContext; 54 class MCExpr; 55 class SDNode; 56 class SDValue; 57 class SelectionDAG; 58 class TargetData; 59 class TargetMachine; 60 class TargetRegisterClass; 61 class TargetLoweringObjectFile; 62 class Value; 63 64 // FIXME: should this be here? 65 namespace TLSModel { 66 enum Model { 67 GeneralDynamic, 68 LocalDynamic, 69 InitialExec, 70 LocalExec 71 }; 72 } 73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 74 75 76//===----------------------------------------------------------------------===// 77/// TargetLowering - This class defines information used to lower LLVM code to 78/// legal SelectionDAG operators that the target instruction selector can accept 79/// natively. 80/// 81/// This class also defines callbacks that targets must implement to lower 82/// target-specific constructs to SelectionDAG operators. 83/// 84class TargetLowering { 85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 87public: 88 /// LegalizeAction - This enum indicates whether operations are valid for a 89 /// target, and if not, what action should be used to make them valid. 90 enum LegalizeAction { 91 Legal, // The target natively supports this operation. 92 Promote, // This operation should be executed in a larger type. 93 Expand, // Try to expand this to other ops, otherwise use a libcall. 94 Custom // Use the LowerOperation hook to implement custom lowering. 95 }; 96 97 enum BooleanContent { // How the target represents true/false values. 98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 99 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 101 }; 102 103 /// NOTE: The constructor takes ownership of TLOF. 104 explicit TargetLowering(const TargetMachine &TM, 105 const TargetLoweringObjectFile *TLOF); 106 virtual ~TargetLowering(); 107 108 const TargetMachine &getTargetMachine() const { return TM; } 109 const TargetData *getTargetData() const { return TD; } 110 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 111 112 bool isBigEndian() const { return !IsLittleEndian; } 113 bool isLittleEndian() const { return IsLittleEndian; } 114 MVT getPointerTy() const { return PointerTy; } 115 MVT getShiftAmountTy() const { return ShiftAmountTy; } 116 117 /// isSelectExpensive - Return true if the select operation is expensive for 118 /// this target. 119 bool isSelectExpensive() const { return SelectIsExpensive; } 120 121 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 122 /// a sequence of several shifts, adds, and multiplies for this target. 123 bool isIntDivCheap() const { return IntDivIsCheap; } 124 125 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 126 /// srl/add/sra. 127 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 128 129 /// getSetCCResultType - Return the ValueType of the result of SETCC 130 /// operations. Also used to obtain the target's preferred type for 131 /// the condition operand of SELECT and BRCOND nodes. In the case of 132 /// BRCOND the argument passed is MVT::Other since there are no other 133 /// operands to get a type hint from. 134 virtual 135 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 136 137 /// getCmpLibcallReturnType - Return the ValueType for comparison 138 /// libcalls. Comparions libcalls include floating point comparion calls, 139 /// and Ordered/Unordered check calls on floating point numbers. 140 virtual 141 MVT::SimpleValueType getCmpLibcallReturnType() const; 142 143 /// getBooleanContents - For targets without i1 registers, this gives the 144 /// nature of the high-bits of boolean values held in types wider than i1. 145 /// "Boolean values" are special true/false values produced by nodes like 146 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 147 /// Not to be confused with general values promoted from i1. 148 BooleanContent getBooleanContents() const { return BooleanContents;} 149 150 /// getSchedulingPreference - Return target scheduling preference. 151 Sched::Preference getSchedulingPreference() const { 152 return SchedPreferenceInfo; 153 } 154 155 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 156 /// different scheduling heuristics for different nodes. This function returns 157 /// the preference (or none) for the given node. 158 virtual Sched::Preference getSchedulingPreference(SDNode *N) const { 159 return Sched::None; 160 } 161 162 /// getRegClassFor - Return the register class that should be used for the 163 /// specified value type. 164 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { 165 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 166 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 167 assert(RC && "This value type is not natively supported!"); 168 return RC; 169 } 170 171 /// getRepRegClassFor - Return the 'representative' register class for the 172 /// specified value type. The 'representative' register class is the largest 173 /// legal super-reg register class for the register class of the value type. 174 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 175 /// while the rep register class is GR64 on x86_64. 176 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { 177 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!"); 178 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; 179 return RC; 180 } 181 182 /// getRepRegClassCostFor - Return the cost of the 'representative' register 183 /// class for the specified value type. 184 virtual uint8_t getRepRegClassCostFor(EVT VT) const { 185 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!"); 186 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; 187 } 188 189 /// getRegPressureLimit - Return the register pressure "high water mark" for 190 /// the specific register class. The scheduler is in high register pressure 191 /// mode (for the specific register class) if it goes over the limit. 192 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 193 MachineFunction &MF) const { 194 return 0; 195 } 196 197 /// isTypeLegal - Return true if the target has native support for the 198 /// specified value type. This means that it has a register that directly 199 /// holds it without promotions or expansions. 200 bool isTypeLegal(EVT VT) const { 201 assert(!VT.isSimple() || 202 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 203 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 204 } 205 206 /// isTypeSynthesizable - Return true if it's OK for the compiler to create 207 /// new operations of this type. All Legal types are synthesizable except 208 /// MMX vector types on X86. Non-Legal types are not synthesizable. 209 bool isTypeSynthesizable(EVT VT) const { 210 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy]; 211 } 212 213 class ValueTypeActionImpl { 214 /// ValueTypeActions - For each value type, keep a LegalizeAction enum 215 /// that indicates how instruction selection should deal with the type. 216 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 217 218 LegalizeAction getExtendedTypeAction(EVT VT) const { 219 // Handle non-vector integers. 220 if (!VT.isVector()) { 221 assert(VT.isInteger() && "Unsupported extended type!"); 222 unsigned BitSize = VT.getSizeInBits(); 223 // First promote to a power-of-two size, then expand if necessary. 224 if (BitSize < 8 || !isPowerOf2_32(BitSize)) 225 return Promote; 226 return Expand; 227 } 228 229 // If this is a type smaller than a legal vector type, promote to that 230 // type, e.g. <2 x float> -> <4 x float>. 231 if (VT.getVectorElementType().isSimple() && 232 VT.getVectorNumElements() != 1) { 233 MVT EltType = VT.getVectorElementType().getSimpleVT(); 234 unsigned NumElts = VT.getVectorNumElements(); 235 while (1) { 236 // Round up to the nearest power of 2. 237 NumElts = (unsigned)NextPowerOf2(NumElts); 238 239 MVT LargerVector = MVT::getVectorVT(EltType, NumElts); 240 if (LargerVector == MVT()) break; 241 242 // If this the larger type is legal, promote to it. 243 if (getTypeAction(LargerVector) == Legal) return Promote; 244 } 245 } 246 247 return VT.isPow2VectorType() ? Expand : Promote; 248 } 249 public: 250 ValueTypeActionImpl() { 251 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 252 } 253 254 LegalizeAction getTypeAction(EVT VT) const { 255 if (!VT.isExtended()) 256 return getTypeAction(VT.getSimpleVT()); 257 return getExtendedTypeAction(VT); 258 } 259 260 LegalizeAction getTypeAction(MVT VT) const { 261 return (LegalizeAction)ValueTypeActions[VT.SimpleTy]; 262 } 263 264 265 void setTypeAction(EVT VT, LegalizeAction Action) { 266 unsigned I = VT.getSimpleVT().SimpleTy; 267 ValueTypeActions[I] = Action; 268 } 269 }; 270 271 const ValueTypeActionImpl &getValueTypeActions() const { 272 return ValueTypeActions; 273 } 274 275 /// getTypeAction - Return how we should legalize values of this type, either 276 /// it is already legal (return 'Legal') or we need to promote it to a larger 277 /// type (return 'Promote'), or we need to expand it into multiple registers 278 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 279 LegalizeAction getTypeAction(EVT VT) const { 280 return ValueTypeActions.getTypeAction(VT); 281 } 282 283 /// getTypeToTransformTo - For types supported by the target, this is an 284 /// identity function. For types that must be promoted to larger types, this 285 /// returns the larger type to promote to. For integer types that are larger 286 /// than the largest integer register, this contains one step in the expansion 287 /// to get to the smaller register. For illegal floating point types, this 288 /// returns the integer type to transform to. 289 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 290 if (VT.isSimple()) { 291 assert((unsigned)VT.getSimpleVT().SimpleTy < 292 array_lengthof(TransformToType)); 293 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 294 assert(getTypeAction(NVT) != Promote && 295 "Promote may not follow Expand or Promote"); 296 return NVT; 297 } 298 299 if (VT.isVector()) { 300 EVT NVT = VT.getPow2VectorType(Context); 301 if (NVT == VT) { 302 // Vector length is a power of 2 - split to half the size. 303 unsigned NumElts = VT.getVectorNumElements(); 304 EVT EltVT = VT.getVectorElementType(); 305 return (NumElts == 1) ? 306 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 307 } 308 // Promote to a power of two size, avoiding multi-step promotion. 309 return getTypeAction(NVT) == Promote ? 310 getTypeToTransformTo(Context, NVT) : NVT; 311 } else if (VT.isInteger()) { 312 EVT NVT = VT.getRoundIntegerType(Context); 313 if (NVT == VT) // Size is a power of two - expand to half the size. 314 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 315 316 // Promote to a power of two size, avoiding multi-step promotion. 317 return getTypeAction(NVT) == Promote ? 318 getTypeToTransformTo(Context, NVT) : NVT; 319 } 320 assert(0 && "Unsupported extended type!"); 321 return MVT(MVT::Other); // Not reached 322 } 323 324 /// getTypeToExpandTo - For types supported by the target, this is an 325 /// identity function. For types that must be expanded (i.e. integer types 326 /// that are larger than the largest integer register or illegal floating 327 /// point types), this returns the largest legal type it will be expanded to. 328 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 329 assert(!VT.isVector()); 330 while (true) { 331 switch (getTypeAction(VT)) { 332 case Legal: 333 return VT; 334 case Expand: 335 VT = getTypeToTransformTo(Context, VT); 336 break; 337 default: 338 assert(false && "Type is not legal nor is it to be expanded!"); 339 return VT; 340 } 341 } 342 return VT; 343 } 344 345 /// getVectorTypeBreakdown - Vector types are broken down into some number of 346 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 347 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 348 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 349 /// 350 /// This method returns the number of registers needed, and the VT for each 351 /// register. It also returns the VT and quantity of the intermediate values 352 /// before they are promoted/expanded. 353 /// 354 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 355 EVT &IntermediateVT, 356 unsigned &NumIntermediates, 357 EVT &RegisterVT) const; 358 359 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 360 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 361 /// this is the case, it returns true and store the intrinsic 362 /// information into the IntrinsicInfo that was passed to the function. 363 struct IntrinsicInfo { 364 unsigned opc; // target opcode 365 EVT memVT; // memory VT 366 const Value* ptrVal; // value representing memory location 367 int offset; // offset off of ptrVal 368 unsigned align; // alignment 369 bool vol; // is volatile? 370 bool readMem; // reads memory? 371 bool writeMem; // writes memory? 372 }; 373 374 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 375 const CallInst &I, unsigned Intrinsic) const { 376 return false; 377 } 378 379 /// isFPImmLegal - Returns true if the target can instruction select the 380 /// specified FP immediate natively. If false, the legalizer will materialize 381 /// the FP immediate as a load from a constant pool. 382 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 383 return false; 384 } 385 386 /// isShuffleMaskLegal - Targets can use this to indicate that they only 387 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 388 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 389 /// are assumed to be legal. 390 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 391 EVT VT) const { 392 return true; 393 } 394 395 /// canOpTrap - Returns true if the operation can trap for the value type. 396 /// VT must be a legal type. By default, we optimistically assume most 397 /// operations don't trap except for divide and remainder. 398 virtual bool canOpTrap(unsigned Op, EVT VT) const; 399 400 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 401 /// used by Targets can use this to indicate if there is a suitable 402 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 403 /// pool entry. 404 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 405 EVT VT) const { 406 return false; 407 } 408 409 /// getOperationAction - Return how this operation should be treated: either 410 /// it is legal, needs to be promoted to a larger size, needs to be 411 /// expanded to some other code sequence, or the target has a custom expander 412 /// for it. 413 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 414 if (VT.isExtended()) return Expand; 415 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 416 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 417 return (LegalizeAction)OpActions[I][Op]; 418 } 419 420 /// isOperationLegalOrCustom - Return true if the specified operation is 421 /// legal on this target or can be made legal with custom lowering. This 422 /// is used to help guide high-level lowering decisions. 423 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 424 return (VT == MVT::Other || isTypeLegal(VT)) && 425 (getOperationAction(Op, VT) == Legal || 426 getOperationAction(Op, VT) == Custom); 427 } 428 429 /// isOperationLegal - Return true if the specified operation is legal on this 430 /// target. 431 bool isOperationLegal(unsigned Op, EVT VT) const { 432 return (VT == MVT::Other || isTypeLegal(VT)) && 433 getOperationAction(Op, VT) == Legal; 434 } 435 436 /// getLoadExtAction - Return how this load with extension should be treated: 437 /// either it is legal, needs to be promoted to a larger size, needs to be 438 /// expanded to some other code sequence, or the target has a custom expander 439 /// for it. 440 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 441 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 442 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 443 "Table isn't big enough!"); 444 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 445 } 446 447 /// isLoadExtLegal - Return true if the specified load with extension is legal 448 /// on this target. 449 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 450 return VT.isSimple() && 451 (getLoadExtAction(ExtType, VT) == Legal || 452 getLoadExtAction(ExtType, VT) == Custom); 453 } 454 455 /// getTruncStoreAction - Return how this store with truncation should be 456 /// treated: either it is legal, needs to be promoted to a larger size, needs 457 /// to be expanded to some other code sequence, or the target has a custom 458 /// expander for it. 459 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 460 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 461 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 462 "Table isn't big enough!"); 463 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 464 [MemVT.getSimpleVT().SimpleTy]; 465 } 466 467 /// isTruncStoreLegal - Return true if the specified store with truncation is 468 /// legal on this target. 469 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 470 return isTypeLegal(ValVT) && MemVT.isSimple() && 471 (getTruncStoreAction(ValVT, MemVT) == Legal || 472 getTruncStoreAction(ValVT, MemVT) == Custom); 473 } 474 475 /// getIndexedLoadAction - Return how the indexed load should be treated: 476 /// either it is legal, needs to be promoted to a larger size, needs to be 477 /// expanded to some other code sequence, or the target has a custom expander 478 /// for it. 479 LegalizeAction 480 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 481 assert( IdxMode < ISD::LAST_INDEXED_MODE && 482 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 483 "Table isn't big enough!"); 484 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 485 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 486 } 487 488 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 489 /// on this target. 490 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 491 return VT.isSimple() && 492 (getIndexedLoadAction(IdxMode, VT) == Legal || 493 getIndexedLoadAction(IdxMode, VT) == Custom); 494 } 495 496 /// getIndexedStoreAction - Return how the indexed store should be treated: 497 /// either it is legal, needs to be promoted to a larger size, needs to be 498 /// expanded to some other code sequence, or the target has a custom expander 499 /// for it. 500 LegalizeAction 501 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 502 assert( IdxMode < ISD::LAST_INDEXED_MODE && 503 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 504 "Table isn't big enough!"); 505 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 506 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 507 } 508 509 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 510 /// on this target. 511 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 512 return VT.isSimple() && 513 (getIndexedStoreAction(IdxMode, VT) == Legal || 514 getIndexedStoreAction(IdxMode, VT) == Custom); 515 } 516 517 /// getCondCodeAction - Return how the condition code should be treated: 518 /// either it is legal, needs to be expanded to some other code sequence, 519 /// or the target has a custom expander for it. 520 LegalizeAction 521 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 522 assert((unsigned)CC < array_lengthof(CondCodeActions) && 523 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 524 "Table isn't big enough!"); 525 LegalizeAction Action = (LegalizeAction) 526 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 527 assert(Action != Promote && "Can't promote condition code!"); 528 return Action; 529 } 530 531 /// isCondCodeLegal - Return true if the specified condition code is legal 532 /// on this target. 533 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 534 return getCondCodeAction(CC, VT) == Legal || 535 getCondCodeAction(CC, VT) == Custom; 536 } 537 538 539 /// getTypeToPromoteTo - If the action for this operation is to promote, this 540 /// method returns the ValueType to promote to. 541 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 542 assert(getOperationAction(Op, VT) == Promote && 543 "This operation isn't promoted!"); 544 545 // See if this has an explicit type specified. 546 std::map<std::pair<unsigned, MVT::SimpleValueType>, 547 MVT::SimpleValueType>::const_iterator PTTI = 548 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 549 if (PTTI != PromoteToType.end()) return PTTI->second; 550 551 assert((VT.isInteger() || VT.isFloatingPoint()) && 552 "Cannot autopromote this type, add it with AddPromotedToType."); 553 554 EVT NVT = VT; 555 do { 556 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 557 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 558 "Didn't find type to promote to!"); 559 } while (!isTypeLegal(NVT) || 560 getOperationAction(Op, NVT) == Promote); 561 return NVT; 562 } 563 564 /// getValueType - Return the EVT corresponding to this LLVM type. 565 /// This is fixed by the LLVM operations except for the pointer size. If 566 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 567 /// counterpart (e.g. structs), otherwise it will assert. 568 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 569 EVT VT = EVT::getEVT(Ty, AllowUnknown); 570 return VT == MVT::iPTR ? PointerTy : VT; 571 } 572 573 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 574 /// function arguments in the caller parameter area. This is the actual 575 /// alignment, not its logarithm. 576 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 577 578 /// getRegisterType - Return the type of registers that this ValueType will 579 /// eventually require. 580 EVT getRegisterType(MVT VT) const { 581 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 582 return RegisterTypeForVT[VT.SimpleTy]; 583 } 584 585 /// getRegisterType - Return the type of registers that this ValueType will 586 /// eventually require. 587 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 588 if (VT.isSimple()) { 589 assert((unsigned)VT.getSimpleVT().SimpleTy < 590 array_lengthof(RegisterTypeForVT)); 591 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 592 } 593 if (VT.isVector()) { 594 EVT VT1, RegisterVT; 595 unsigned NumIntermediates; 596 (void)getVectorTypeBreakdown(Context, VT, VT1, 597 NumIntermediates, RegisterVT); 598 return RegisterVT; 599 } 600 if (VT.isInteger()) { 601 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 602 } 603 assert(0 && "Unsupported extended type!"); 604 return EVT(MVT::Other); // Not reached 605 } 606 607 /// getNumRegisters - Return the number of registers that this ValueType will 608 /// eventually require. This is one for any types promoted to live in larger 609 /// registers, but may be more than one for types (like i64) that are split 610 /// into pieces. For types like i140, which are first promoted then expanded, 611 /// it is the number of registers needed to hold all the bits of the original 612 /// type. For an i140 on a 32 bit machine this means 5 registers. 613 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 614 if (VT.isSimple()) { 615 assert((unsigned)VT.getSimpleVT().SimpleTy < 616 array_lengthof(NumRegistersForVT)); 617 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 618 } 619 if (VT.isVector()) { 620 EVT VT1, VT2; 621 unsigned NumIntermediates; 622 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 623 } 624 if (VT.isInteger()) { 625 unsigned BitWidth = VT.getSizeInBits(); 626 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 627 return (BitWidth + RegWidth - 1) / RegWidth; 628 } 629 assert(0 && "Unsupported extended type!"); 630 return 0; // Not reached 631 } 632 633 /// ShouldShrinkFPConstant - If true, then instruction selection should 634 /// seek to shrink the FP constant of the specified type to a smaller type 635 /// in order to save space and / or reduce runtime. 636 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 637 638 /// hasTargetDAGCombine - If true, the target has custom DAG combine 639 /// transformations that it can perform for the specified node. 640 bool hasTargetDAGCombine(ISD::NodeType NT) const { 641 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 642 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 643 } 644 645 /// This function returns the maximum number of store operations permitted 646 /// to replace a call to llvm.memset. The value is set by the target at the 647 /// performance threshold for such a replacement. 648 /// @brief Get maximum # of store operations permitted for llvm.memset 649 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 650 651 /// This function returns the maximum number of store operations permitted 652 /// to replace a call to llvm.memcpy. The value is set by the target at the 653 /// performance threshold for such a replacement. 654 /// @brief Get maximum # of store operations permitted for llvm.memcpy 655 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 656 657 /// This function returns the maximum number of store operations permitted 658 /// to replace a call to llvm.memmove. The value is set by the target at the 659 /// performance threshold for such a replacement. 660 /// @brief Get maximum # of store operations permitted for llvm.memmove 661 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 662 663 /// This function returns true if the target allows unaligned memory accesses. 664 /// of the specified type. This is used, for example, in situations where an 665 /// array copy/move/set is converted to a sequence of store operations. It's 666 /// use helps to ensure that such replacements don't generate code that causes 667 /// an alignment error (trap) on the target machine. 668 /// @brief Determine if the target supports unaligned memory accesses. 669 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 670 return false; 671 } 672 673 /// This function returns true if the target would benefit from code placement 674 /// optimization. 675 /// @brief Determine if the target should perform code placement optimization. 676 bool shouldOptimizeCodePlacement() const { 677 return benefitFromCodePlacementOpt; 678 } 679 680 /// getOptimalMemOpType - Returns the target specific optimal type for load 681 /// and store operations as a result of memset, memcpy, and memmove 682 /// lowering. If DstAlign is zero that means it's safe to destination 683 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 684 /// means there isn't a need to check it against alignment requirement, 685 /// probably because the source does not need to be loaded. If 686 /// 'NonScalarIntSafe' is true, that means it's safe to return a 687 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 688 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 689 /// constant so it does not need to be loaded. 690 /// It returns EVT::Other if the type should be determined using generic 691 /// target-independent logic. 692 virtual EVT getOptimalMemOpType(uint64_t Size, 693 unsigned DstAlign, unsigned SrcAlign, 694 bool NonScalarIntSafe, bool MemcpyStrSrc, 695 MachineFunction &MF) const { 696 return MVT::Other; 697 } 698 699 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 700 /// to implement llvm.setjmp. 701 bool usesUnderscoreSetJmp() const { 702 return UseUnderscoreSetJmp; 703 } 704 705 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 706 /// to implement llvm.longjmp. 707 bool usesUnderscoreLongJmp() const { 708 return UseUnderscoreLongJmp; 709 } 710 711 /// getStackPointerRegisterToSaveRestore - If a physical register, this 712 /// specifies the register that llvm.savestack/llvm.restorestack should save 713 /// and restore. 714 unsigned getStackPointerRegisterToSaveRestore() const { 715 return StackPointerRegisterToSaveRestore; 716 } 717 718 /// getExceptionAddressRegister - If a physical register, this returns 719 /// the register that receives the exception address on entry to a landing 720 /// pad. 721 unsigned getExceptionAddressRegister() const { 722 return ExceptionPointerRegister; 723 } 724 725 /// getExceptionSelectorRegister - If a physical register, this returns 726 /// the register that receives the exception typeid on entry to a landing 727 /// pad. 728 unsigned getExceptionSelectorRegister() const { 729 return ExceptionSelectorRegister; 730 } 731 732 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 733 /// set, the default is 200) 734 unsigned getJumpBufSize() const { 735 return JumpBufSize; 736 } 737 738 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 739 /// (if never set, the default is 0) 740 unsigned getJumpBufAlignment() const { 741 return JumpBufAlignment; 742 } 743 744 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 745 /// argument. 746 unsigned getMinStackArgumentAlignment() const { 747 return MinStackArgumentAlignment; 748 } 749 750 /// getPrefLoopAlignment - return the preferred loop alignment. 751 /// 752 unsigned getPrefLoopAlignment() const { 753 return PrefLoopAlignment; 754 } 755 756 /// getShouldFoldAtomicFences - return whether the combiner should fold 757 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 758 /// 759 bool getShouldFoldAtomicFences() const { 760 return ShouldFoldAtomicFences; 761 } 762 763 /// getPreIndexedAddressParts - returns true by value, base pointer and 764 /// offset pointer and addressing mode by reference if the node's address 765 /// can be legally represented as pre-indexed load / store address. 766 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 767 SDValue &Offset, 768 ISD::MemIndexedMode &AM, 769 SelectionDAG &DAG) const { 770 return false; 771 } 772 773 /// getPostIndexedAddressParts - returns true by value, base pointer and 774 /// offset pointer and addressing mode by reference if this node can be 775 /// combined with a load / store to form a post-indexed load / store. 776 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 777 SDValue &Base, SDValue &Offset, 778 ISD::MemIndexedMode &AM, 779 SelectionDAG &DAG) const { 780 return false; 781 } 782 783 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 784 /// current function. The returned value is a member of the 785 /// MachineJumpTableInfo::JTEntryKind enum. 786 virtual unsigned getJumpTableEncoding() const; 787 788 virtual const MCExpr * 789 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 790 const MachineBasicBlock *MBB, unsigned uid, 791 MCContext &Ctx) const { 792 assert(0 && "Need to implement this hook if target has custom JTIs"); 793 return 0; 794 } 795 796 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 797 /// jumptable. 798 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 799 SelectionDAG &DAG) const; 800 801 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 802 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 803 /// MCExpr. 804 virtual const MCExpr * 805 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 806 unsigned JTI, MCContext &Ctx) const; 807 808 /// isOffsetFoldingLegal - Return true if folding a constant offset 809 /// with the given GlobalAddress is legal. It is frequently not legal in 810 /// PIC relocation models. 811 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 812 813 /// getFunctionAlignment - Return the Log2 alignment of this function. 814 virtual unsigned getFunctionAlignment(const Function *) const = 0; 815 816 /// getStackCookieLocation - Return true if the target stores stack 817 /// protector cookies at a fixed offset in some non-standard address 818 /// space, and populates the address space and offset as 819 /// appropriate. 820 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const { 821 return false; 822 } 823 824 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 825 /// used for loads / stores from the global. 826 virtual unsigned getMaximalGlobalOffset() const { 827 return 0; 828 } 829 830 //===--------------------------------------------------------------------===// 831 // TargetLowering Optimization Methods 832 // 833 834 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 835 /// SDValues for returning information from TargetLowering to its clients 836 /// that want to combine 837 struct TargetLoweringOpt { 838 SelectionDAG &DAG; 839 bool LegalTys; 840 bool LegalOps; 841 SDValue Old; 842 SDValue New; 843 844 explicit TargetLoweringOpt(SelectionDAG &InDAG, 845 bool LT, bool LO) : 846 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 847 848 bool LegalTypes() const { return LegalTys; } 849 bool LegalOperations() const { return LegalOps; } 850 851 bool CombineTo(SDValue O, SDValue N) { 852 Old = O; 853 New = N; 854 return true; 855 } 856 857 /// ShrinkDemandedConstant - Check to see if the specified operand of the 858 /// specified instruction is a constant integer. If so, check to see if 859 /// there are any bits set in the constant that are not demanded. If so, 860 /// shrink the constant and return true. 861 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 862 863 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 864 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 865 /// cast, but it could be generalized for targets with other types of 866 /// implicit widening casts. 867 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 868 DebugLoc dl); 869 }; 870 871 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 872 /// DemandedMask bits of the result of Op are ever used downstream. If we can 873 /// use this information to simplify Op, create a new simplified DAG node and 874 /// return true, returning the original and new nodes in Old and New. 875 /// Otherwise, analyze the expression and return a mask of KnownOne and 876 /// KnownZero bits for the expression (used to simplify the caller). 877 /// The KnownZero/One bits may only be accurate for those bits in the 878 /// DemandedMask. 879 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 880 APInt &KnownZero, APInt &KnownOne, 881 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 882 883 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 884 /// Mask are known to be either zero or one and return them in the 885 /// KnownZero/KnownOne bitsets. 886 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 887 const APInt &Mask, 888 APInt &KnownZero, 889 APInt &KnownOne, 890 const SelectionDAG &DAG, 891 unsigned Depth = 0) const; 892 893 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 894 /// targets that want to expose additional information about sign bits to the 895 /// DAG Combiner. 896 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 897 unsigned Depth = 0) const; 898 899 struct DAGCombinerInfo { 900 void *DC; // The DAG Combiner object. 901 bool BeforeLegalize; 902 bool BeforeLegalizeOps; 903 bool CalledByLegalizer; 904 public: 905 SelectionDAG &DAG; 906 907 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 908 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 909 CalledByLegalizer(cl), DAG(dag) {} 910 911 bool isBeforeLegalize() const { return BeforeLegalize; } 912 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 913 bool isCalledByLegalizer() const { return CalledByLegalizer; } 914 915 void AddToWorklist(SDNode *N); 916 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 917 bool AddTo = true); 918 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 919 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 920 921 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 922 }; 923 924 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 925 /// and cc. If it is unable to simplify it, return a null SDValue. 926 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 927 ISD::CondCode Cond, bool foldBooleans, 928 DAGCombinerInfo &DCI, DebugLoc dl) const; 929 930 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 931 /// node is a GlobalAddress + offset. 932 virtual bool 933 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 934 935 /// PerformDAGCombine - This method will be invoked for all target nodes and 936 /// for any target-independent nodes that the target has registered with 937 /// invoke it for. 938 /// 939 /// The semantics are as follows: 940 /// Return Value: 941 /// SDValue.Val == 0 - No change was made 942 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 943 /// otherwise - N should be replaced by the returned Operand. 944 /// 945 /// In addition, methods provided by DAGCombinerInfo may be used to perform 946 /// more complex transformations. 947 /// 948 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 949 950 /// isTypeDesirableForOp - Return true if the target has native support for 951 /// the specified value type and it is 'desirable' to use the type for the 952 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 953 /// instruction encodings are longer and some i16 instructions are slow. 954 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const { 955 // By default, assume all legal types are desirable. 956 return isTypeLegal(VT); 957 } 958 959 /// IsDesirableToPromoteOp - This method query the target whether it is 960 /// beneficial for dag combiner to promote the specified node. If true, it 961 /// should return the desired promotion type by reference. 962 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 963 return false; 964 } 965 966 //===--------------------------------------------------------------------===// 967 // TargetLowering Configuration Methods - These methods should be invoked by 968 // the derived class constructor to configure this object for the target. 969 // 970 971protected: 972 /// setShiftAmountType - Describe the type that should be used for shift 973 /// amounts. This type defaults to the pointer type. 974 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 975 976 /// setBooleanContents - Specify how the target extends the result of a 977 /// boolean value from i1 to a wider type. See getBooleanContents. 978 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 979 980 /// setSchedulingPreference - Specify the target scheduling preference. 981 void setSchedulingPreference(Sched::Preference Pref) { 982 SchedPreferenceInfo = Pref; 983 } 984 985 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 986 /// use _setjmp to implement llvm.setjmp or the non _ version. 987 /// Defaults to false. 988 void setUseUnderscoreSetJmp(bool Val) { 989 UseUnderscoreSetJmp = Val; 990 } 991 992 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 993 /// use _longjmp to implement llvm.longjmp or the non _ version. 994 /// Defaults to false. 995 void setUseUnderscoreLongJmp(bool Val) { 996 UseUnderscoreLongJmp = Val; 997 } 998 999 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 1000 /// specifies the register that llvm.savestack/llvm.restorestack should save 1001 /// and restore. 1002 void setStackPointerRegisterToSaveRestore(unsigned R) { 1003 StackPointerRegisterToSaveRestore = R; 1004 } 1005 1006 /// setExceptionPointerRegister - If set to a physical register, this sets 1007 /// the register that receives the exception address on entry to a landing 1008 /// pad. 1009 void setExceptionPointerRegister(unsigned R) { 1010 ExceptionPointerRegister = R; 1011 } 1012 1013 /// setExceptionSelectorRegister - If set to a physical register, this sets 1014 /// the register that receives the exception typeid on entry to a landing 1015 /// pad. 1016 void setExceptionSelectorRegister(unsigned R) { 1017 ExceptionSelectorRegister = R; 1018 } 1019 1020 /// SelectIsExpensive - Tells the code generator not to expand operations 1021 /// into sequences that use the select operations if possible. 1022 void setSelectIsExpensive() { SelectIsExpensive = true; } 1023 1024 /// setIntDivIsCheap - Tells the code generator that integer divide is 1025 /// expensive, and if possible, should be replaced by an alternate sequence 1026 /// of instructions not containing an integer divide. 1027 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 1028 1029 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 1030 /// srl/add/sra for a signed divide by power of two, and let the target handle 1031 /// it. 1032 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 1033 1034 /// addRegisterClass - Add the specified register class as an available 1035 /// regclass for the specified value type. This indicates the selector can 1036 /// handle values of that class natively. 1037 void addRegisterClass(EVT VT, TargetRegisterClass *RC, 1038 bool isSynthesizable = true) { 1039 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 1040 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 1041 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 1042 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable; 1043 } 1044 1045 /// findRepresentativeClass - Return the largest legal super-reg register class 1046 /// of the register class for the specified type and its associated "cost". 1047 virtual std::pair<const TargetRegisterClass*, uint8_t> 1048 findRepresentativeClass(EVT VT) const; 1049 1050 /// computeRegisterProperties - Once all of the register classes are added, 1051 /// this allows us to compute derived properties we expose. 1052 void computeRegisterProperties(); 1053 1054 /// setOperationAction - Indicate that the specified operation does not work 1055 /// with the specified type and indicate what to do about it. 1056 void setOperationAction(unsigned Op, MVT VT, 1057 LegalizeAction Action) { 1058 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 1059 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 1060 } 1061 1062 /// setLoadExtAction - Indicate that the specified load with extension does 1063 /// not work with the specified type and indicate what to do about it. 1064 void setLoadExtAction(unsigned ExtType, MVT VT, 1065 LegalizeAction Action) { 1066 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 1067 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1068 "Table isn't big enough!"); 1069 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 1070 } 1071 1072 /// setTruncStoreAction - Indicate that the specified truncating store does 1073 /// not work with the specified type and indicate what to do about it. 1074 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1075 LegalizeAction Action) { 1076 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE && 1077 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE && 1078 "Table isn't big enough!"); 1079 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1080 } 1081 1082 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1083 /// does not work with the specified type and indicate what to do abort 1084 /// it. NOTE: All indexed mode loads are initialized to Expand in 1085 /// TargetLowering.cpp 1086 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1087 LegalizeAction Action) { 1088 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1089 IdxMode < ISD::LAST_INDEXED_MODE && 1090 (unsigned)Action < 0xf && 1091 "Table isn't big enough!"); 1092 // Load action are kept in the upper half. 1093 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1094 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1095 } 1096 1097 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1098 /// does not work with the specified type and indicate what to do about 1099 /// it. NOTE: All indexed mode stores are initialized to Expand in 1100 /// TargetLowering.cpp 1101 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1102 LegalizeAction Action) { 1103 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1104 IdxMode < ISD::LAST_INDEXED_MODE && 1105 (unsigned)Action < 0xf && 1106 "Table isn't big enough!"); 1107 // Store action are kept in the lower half. 1108 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1109 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1110 } 1111 1112 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1113 /// supported on the target and indicate what to do about it. 1114 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1115 LegalizeAction Action) { 1116 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1117 (unsigned)CC < array_lengthof(CondCodeActions) && 1118 "Table isn't big enough!"); 1119 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1120 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1121 } 1122 1123 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1124 /// promotion code defaults to trying a larger integer/fp until it can find 1125 /// one that works. If that default is insufficient, this method can be used 1126 /// by the target to override the default. 1127 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1128 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1129 } 1130 1131 /// setTargetDAGCombine - Targets should invoke this method for each target 1132 /// independent node that they want to provide a custom DAG combiner for by 1133 /// implementing the PerformDAGCombine virtual method. 1134 void setTargetDAGCombine(ISD::NodeType NT) { 1135 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1136 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1137 } 1138 1139 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1140 /// bytes); default is 200 1141 void setJumpBufSize(unsigned Size) { 1142 JumpBufSize = Size; 1143 } 1144 1145 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1146 /// alignment (in bytes); default is 0 1147 void setJumpBufAlignment(unsigned Align) { 1148 JumpBufAlignment = Align; 1149 } 1150 1151 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1152 /// alignment is zero, it means the target does not care about loop alignment. 1153 void setPrefLoopAlignment(unsigned Align) { 1154 PrefLoopAlignment = Align; 1155 } 1156 1157 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1158 /// argument. 1159 void setMinStackArgumentAlignment(unsigned Align) { 1160 MinStackArgumentAlignment = Align; 1161 } 1162 1163 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1164 /// atomic operation intrinsics includes locking. Default is false. 1165 void setShouldFoldAtomicFences(bool fold) { 1166 ShouldFoldAtomicFences = fold; 1167 } 1168 1169public: 1170 //===--------------------------------------------------------------------===// 1171 // Lowering methods - These methods must be implemented by targets so that 1172 // the SelectionDAGLowering code knows how to lower these. 1173 // 1174 1175 /// LowerFormalArguments - This hook must be implemented to lower the 1176 /// incoming (formal) arguments, described by the Ins array, into the 1177 /// specified DAG. The implementation should fill in the InVals array 1178 /// with legal-type argument values, and return the resulting token 1179 /// chain value. 1180 /// 1181 virtual SDValue 1182 LowerFormalArguments(SDValue Chain, 1183 CallingConv::ID CallConv, bool isVarArg, 1184 const SmallVectorImpl<ISD::InputArg> &Ins, 1185 DebugLoc dl, SelectionDAG &DAG, 1186 SmallVectorImpl<SDValue> &InVals) const { 1187 assert(0 && "Not Implemented"); 1188 return SDValue(); // this is here to silence compiler errors 1189 } 1190 1191 /// LowerCallTo - This function lowers an abstract call to a function into an 1192 /// actual call. This returns a pair of operands. The first element is the 1193 /// return value for the function (if RetTy is not VoidTy). The second 1194 /// element is the outgoing token chain. It calls LowerCall to do the actual 1195 /// lowering. 1196 struct ArgListEntry { 1197 SDValue Node; 1198 const Type* Ty; 1199 bool isSExt : 1; 1200 bool isZExt : 1; 1201 bool isInReg : 1; 1202 bool isSRet : 1; 1203 bool isNest : 1; 1204 bool isByVal : 1; 1205 uint16_t Alignment; 1206 1207 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1208 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1209 }; 1210 typedef std::vector<ArgListEntry> ArgListTy; 1211 std::pair<SDValue, SDValue> 1212 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1213 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1214 CallingConv::ID CallConv, bool isTailCall, 1215 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1216 SelectionDAG &DAG, DebugLoc dl) const; 1217 1218 /// LowerCall - This hook must be implemented to lower calls into the 1219 /// the specified DAG. The outgoing arguments to the call are described 1220 /// by the Outs array, and the values to be returned by the call are 1221 /// described by the Ins array. The implementation should fill in the 1222 /// InVals array with legal-type return values from the call, and return 1223 /// the resulting token chain value. 1224 virtual SDValue 1225 LowerCall(SDValue Chain, SDValue Callee, 1226 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 1227 const SmallVectorImpl<ISD::OutputArg> &Outs, 1228 const SmallVectorImpl<SDValue> &OutVals, 1229 const SmallVectorImpl<ISD::InputArg> &Ins, 1230 DebugLoc dl, SelectionDAG &DAG, 1231 SmallVectorImpl<SDValue> &InVals) const { 1232 assert(0 && "Not Implemented"); 1233 return SDValue(); // this is here to silence compiler errors 1234 } 1235 1236 /// CanLowerReturn - This hook should be implemented to check whether the 1237 /// return values described by the Outs array can fit into the return 1238 /// registers. If false is returned, an sret-demotion is performed. 1239 /// 1240 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1241 const SmallVectorImpl<ISD::OutputArg> &Outs, 1242 LLVMContext &Context) const 1243 { 1244 // Return true by default to get preexisting behavior. 1245 return true; 1246 } 1247 1248 /// LowerReturn - This hook must be implemented to lower outgoing 1249 /// return values, described by the Outs array, into the specified 1250 /// DAG. The implementation should return the resulting token chain 1251 /// value. 1252 /// 1253 virtual SDValue 1254 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1255 const SmallVectorImpl<ISD::OutputArg> &Outs, 1256 const SmallVectorImpl<SDValue> &OutVals, 1257 DebugLoc dl, SelectionDAG &DAG) const { 1258 assert(0 && "Not Implemented"); 1259 return SDValue(); // this is here to silence compiler errors 1260 } 1261 1262 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1263 /// to legalize nodes with an illegal operand type but legal result types. 1264 /// It replaces the LowerOperation callback in the type Legalizer. 1265 /// The reason we can not do away with LowerOperation entirely is that 1266 /// LegalizeDAG isn't yet ready to use this callback. 1267 /// TODO: Consider merging with ReplaceNodeResults. 1268 1269 /// The target places new result values for the node in Results (their number 1270 /// and types must exactly match those of the original return values of 1271 /// the node), or leaves Results empty, which indicates that the node is not 1272 /// to be custom lowered after all. 1273 /// The default implementation calls LowerOperation. 1274 virtual void LowerOperationWrapper(SDNode *N, 1275 SmallVectorImpl<SDValue> &Results, 1276 SelectionDAG &DAG) const; 1277 1278 /// LowerOperation - This callback is invoked for operations that are 1279 /// unsupported by the target, which are registered to use 'custom' lowering, 1280 /// and whose defined values are all legal. 1281 /// If the target has no operations that require custom lowering, it need not 1282 /// implement this. The default implementation of this aborts. 1283 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1284 1285 /// ReplaceNodeResults - This callback is invoked when a node result type is 1286 /// illegal for the target, and the operation was registered to use 'custom' 1287 /// lowering for that result type. The target places new result values for 1288 /// the node in Results (their number and types must exactly match those of 1289 /// the original return values of the node), or leaves Results empty, which 1290 /// indicates that the node is not to be custom lowered after all. 1291 /// 1292 /// If the target has no operations that require custom lowering, it need not 1293 /// implement this. The default implementation aborts. 1294 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1295 SelectionDAG &DAG) const { 1296 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1297 } 1298 1299 /// getTargetNodeName() - This method returns the name of a target specific 1300 /// DAG node. 1301 virtual const char *getTargetNodeName(unsigned Opcode) const; 1302 1303 /// createFastISel - This method returns a target specific FastISel object, 1304 /// or null if the target does not support "fast" ISel. 1305 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const { 1306 return 0; 1307 } 1308 1309 //===--------------------------------------------------------------------===// 1310 // Inline Asm Support hooks 1311 // 1312 1313 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1314 /// call to be explicit llvm code if it wants to. This is useful for 1315 /// turning simple inline asms into LLVM intrinsics, which gives the 1316 /// compiler more information about the behavior of the code. 1317 virtual bool ExpandInlineAsm(CallInst *CI) const { 1318 return false; 1319 } 1320 1321 enum ConstraintType { 1322 C_Register, // Constraint represents specific register(s). 1323 C_RegisterClass, // Constraint represents any of register(s) in class. 1324 C_Memory, // Memory constraint. 1325 C_Other, // Something else. 1326 C_Unknown // Unsupported constraint. 1327 }; 1328 1329 /// AsmOperandInfo - This contains information for each constraint that we are 1330 /// lowering. 1331 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1332 /// ConstraintCode - This contains the actual string for the code, like "m". 1333 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1334 /// most closely matches the operand. 1335 std::string ConstraintCode; 1336 1337 /// ConstraintType - Information about the constraint code, e.g. Register, 1338 /// RegisterClass, Memory, Other, Unknown. 1339 TargetLowering::ConstraintType ConstraintType; 1340 1341 /// CallOperandval - If this is the result output operand or a 1342 /// clobber, this is null, otherwise it is the incoming operand to the 1343 /// CallInst. This gets modified as the asm is processed. 1344 Value *CallOperandVal; 1345 1346 /// ConstraintVT - The ValueType for the operand value. 1347 EVT ConstraintVT; 1348 1349 /// isMatchingInputConstraint - Return true of this is an input operand that 1350 /// is a matching constraint like "4". 1351 bool isMatchingInputConstraint() const; 1352 1353 /// getMatchedOperand - If this is an input matching constraint, this method 1354 /// returns the output operand it matches. 1355 unsigned getMatchedOperand() const; 1356 1357 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1358 : InlineAsm::ConstraintInfo(info), 1359 ConstraintType(TargetLowering::C_Unknown), 1360 CallOperandVal(0), ConstraintVT(MVT::Other) { 1361 } 1362 }; 1363 1364 /// ComputeConstraintToUse - Determines the constraint code and constraint 1365 /// type to use for the specific AsmOperandInfo, setting 1366 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1367 /// being passed in is available, it can be passed in as Op, otherwise an 1368 /// empty SDValue can be passed. 1369 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1370 SDValue Op, 1371 SelectionDAG *DAG = 0) const; 1372 1373 /// getConstraintType - Given a constraint, return the type of constraint it 1374 /// is for this target. 1375 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1376 1377 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1378 /// return a list of registers that can be used to satisfy the constraint. 1379 /// This should only be used for C_RegisterClass constraints. 1380 virtual std::vector<unsigned> 1381 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1382 EVT VT) const; 1383 1384 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1385 /// {edx}), return the register number and the register class for the 1386 /// register. 1387 /// 1388 /// Given a register class constraint, like 'r', if this corresponds directly 1389 /// to an LLVM register class, return a register of 0 and the register class 1390 /// pointer. 1391 /// 1392 /// This should only be used for C_Register constraints. On error, 1393 /// this returns a register number of 0 and a null register class pointer.. 1394 virtual std::pair<unsigned, const TargetRegisterClass*> 1395 getRegForInlineAsmConstraint(const std::string &Constraint, 1396 EVT VT) const; 1397 1398 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1399 /// with another that has more specific requirements based on the type of the 1400 /// corresponding operand. This returns null if there is no replacement to 1401 /// make. 1402 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1403 1404 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1405 /// vector. If it is invalid, don't add anything to Ops. 1406 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1407 std::vector<SDValue> &Ops, 1408 SelectionDAG &DAG) const; 1409 1410 //===--------------------------------------------------------------------===// 1411 // Instruction Emitting Hooks 1412 // 1413 1414 // EmitInstrWithCustomInserter - This method should be implemented by targets 1415 // that mark instructions with the 'usesCustomInserter' flag. These 1416 // instructions are special in various ways, which require special support to 1417 // insert. The specified MachineInstr is created but not inserted into any 1418 // basic blocks, and this method is called to expand it into a sequence of 1419 // instructions, potentially also creating new basic blocks and control flow. 1420 virtual MachineBasicBlock * 1421 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1422 1423 //===--------------------------------------------------------------------===// 1424 // Addressing mode description hooks (used by LSR etc). 1425 // 1426 1427 /// AddrMode - This represents an addressing mode of: 1428 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1429 /// If BaseGV is null, there is no BaseGV. 1430 /// If BaseOffs is zero, there is no base offset. 1431 /// If HasBaseReg is false, there is no base register. 1432 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1433 /// no scale. 1434 /// 1435 struct AddrMode { 1436 GlobalValue *BaseGV; 1437 int64_t BaseOffs; 1438 bool HasBaseReg; 1439 int64_t Scale; 1440 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1441 }; 1442 1443 /// isLegalAddressingMode - Return true if the addressing mode represented by 1444 /// AM is legal for this target, for a load/store of the specified type. 1445 /// The type may be VoidTy, in which case only return true if the addressing 1446 /// mode is legal for a load/store of any legal type. 1447 /// TODO: Handle pre/postinc as well. 1448 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1449 1450 /// isTruncateFree - Return true if it's free to truncate a value of 1451 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1452 /// register EAX to i16 by referencing its sub-register AX. 1453 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1454 return false; 1455 } 1456 1457 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1458 return false; 1459 } 1460 1461 /// isZExtFree - Return true if any actual instruction that defines a 1462 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1463 /// register. This does not necessarily include registers defined in 1464 /// unknown ways, such as incoming arguments, or copies from unknown 1465 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1466 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1467 /// all instructions that define 32-bit values implicit zero-extend the 1468 /// result out to 64 bits. 1469 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1470 return false; 1471 } 1472 1473 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1474 return false; 1475 } 1476 1477 /// isNarrowingProfitable - Return true if it's profitable to narrow 1478 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1479 /// from i32 to i8 but not from i32 to i16. 1480 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1481 return false; 1482 } 1483 1484 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1485 /// icmp immediate, that is the target has icmp instructions which can compare 1486 /// a register against the immediate without having to materialize the 1487 /// immediate into a register. 1488 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1489 return true; 1490 } 1491 1492 //===--------------------------------------------------------------------===// 1493 // Div utility functions 1494 // 1495 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1496 std::vector<SDNode*>* Created) const; 1497 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1498 std::vector<SDNode*>* Created) const; 1499 1500 1501 //===--------------------------------------------------------------------===// 1502 // Runtime Library hooks 1503 // 1504 1505 /// setLibcallName - Rename the default libcall routine name for the specified 1506 /// libcall. 1507 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1508 LibcallRoutineNames[Call] = Name; 1509 } 1510 1511 /// getLibcallName - Get the libcall routine name for the specified libcall. 1512 /// 1513 const char *getLibcallName(RTLIB::Libcall Call) const { 1514 return LibcallRoutineNames[Call]; 1515 } 1516 1517 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1518 /// result of the comparison libcall against zero. 1519 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1520 CmpLibcallCCs[Call] = CC; 1521 } 1522 1523 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1524 /// the comparison libcall against zero. 1525 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1526 return CmpLibcallCCs[Call]; 1527 } 1528 1529 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1530 /// specified libcall. 1531 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1532 LibcallCallingConvs[Call] = CC; 1533 } 1534 1535 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1536 /// specified libcall. 1537 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1538 return LibcallCallingConvs[Call]; 1539 } 1540 1541private: 1542 const TargetMachine &TM; 1543 const TargetData *TD; 1544 const TargetLoweringObjectFile &TLOF; 1545 1546 /// PointerTy - The type to use for pointers, usually i32 or i64. 1547 /// 1548 MVT PointerTy; 1549 1550 /// IsLittleEndian - True if this is a little endian target. 1551 /// 1552 bool IsLittleEndian; 1553 1554 /// SelectIsExpensive - Tells the code generator not to expand operations 1555 /// into sequences that use the select operations if possible. 1556 bool SelectIsExpensive; 1557 1558 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1559 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1560 /// a real cost model is in place. If we ever optimize for size, this will be 1561 /// set to true unconditionally. 1562 bool IntDivIsCheap; 1563 1564 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1565 /// srl/add/sra for a signed divide by power of two, and let the target handle 1566 /// it. 1567 bool Pow2DivIsCheap; 1568 1569 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1570 /// llvm.setjmp. Defaults to false. 1571 bool UseUnderscoreSetJmp; 1572 1573 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1574 /// llvm.longjmp. Defaults to false. 1575 bool UseUnderscoreLongJmp; 1576 1577 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1578 /// PointerTy is. 1579 MVT ShiftAmountTy; 1580 1581 /// BooleanContents - Information about the contents of the high-bits in 1582 /// boolean values held in a type wider than i1. See getBooleanContents. 1583 BooleanContent BooleanContents; 1584 1585 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1586 /// total cycles or lowest register usage. 1587 Sched::Preference SchedPreferenceInfo; 1588 1589 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1590 unsigned JumpBufSize; 1591 1592 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1593 /// buffers 1594 unsigned JumpBufAlignment; 1595 1596 /// MinStackArgumentAlignment - The minimum alignment that any argument 1597 /// on the stack needs to have. 1598 /// 1599 unsigned MinStackArgumentAlignment; 1600 1601 /// PrefLoopAlignment - The perferred loop alignment. 1602 /// 1603 unsigned PrefLoopAlignment; 1604 1605 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1606 /// be folded into the enclosed atomic intrinsic instruction by the 1607 /// combiner. 1608 bool ShouldFoldAtomicFences; 1609 1610 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1611 /// specifies the register that llvm.savestack/llvm.restorestack should save 1612 /// and restore. 1613 unsigned StackPointerRegisterToSaveRestore; 1614 1615 /// ExceptionPointerRegister - If set to a physical register, this specifies 1616 /// the register that receives the exception address on entry to a landing 1617 /// pad. 1618 unsigned ExceptionPointerRegister; 1619 1620 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1621 /// the register that receives the exception typeid on entry to a landing 1622 /// pad. 1623 unsigned ExceptionSelectorRegister; 1624 1625 /// RegClassForVT - This indicates the default register class to use for 1626 /// each ValueType the target supports natively. 1627 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1628 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1629 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1630 1631 /// RepRegClassForVT - This indicates the "representative" register class to 1632 /// use for each ValueType the target supports natively. This information is 1633 /// used by the scheduler to track register pressure. By default, the 1634 /// representative register class is the largest legal super-reg register 1635 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1636 /// and i32's representative class would be GR32. 1637 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1638 1639 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1640 /// register class for each ValueType. The cost is used by the scheduler to 1641 /// approximate register pressure. 1642 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1643 1644 /// Synthesizable indicates whether it is OK for the compiler to create new 1645 /// operations using this type. All Legal types are Synthesizable except 1646 /// MMX types on X86. Non-Legal types are not Synthesizable. 1647 bool Synthesizable[MVT::LAST_VALUETYPE]; 1648 1649 /// TransformToType - For any value types we are promoting or expanding, this 1650 /// contains the value type that we are changing to. For Expanded types, this 1651 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1652 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1653 /// by the system, this holds the same type (e.g. i32 -> i32). 1654 EVT TransformToType[MVT::LAST_VALUETYPE]; 1655 1656 /// OpActions - For each operation and each value type, keep a LegalizeAction 1657 /// that indicates how instruction selection should deal with the operation. 1658 /// Most operations are Legal (aka, supported natively by the target), but 1659 /// operations that are not should be described. Note that operations on 1660 /// non-legal value types are not described here. 1661 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1662 1663 /// LoadExtActions - For each load extension type and each value type, 1664 /// keep a LegalizeAction that indicates how instruction selection should deal 1665 /// with a load of a specific value type and extension type. 1666 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1667 1668 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1669 /// indicates whether a truncating store of a specific value type and 1670 /// truncating type is legal. 1671 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1672 1673 /// IndexedModeActions - For each indexed mode and each value type, 1674 /// keep a pair of LegalizeAction that indicates how instruction 1675 /// selection should deal with the load / store. The first dimension is the 1676 /// value_type for the reference. The second dimension represents the various 1677 /// modes for load store. 1678 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1679 1680 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1681 /// LegalizeAction that indicates how instruction selection should 1682 /// deal with the condition code. 1683 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1684 1685 ValueTypeActionImpl ValueTypeActions; 1686 1687 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1688 1689 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1690 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1691 /// which sets a bit in this array. 1692 unsigned char 1693 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1694 1695 /// PromoteToType - For operations that must be promoted to a specific type, 1696 /// this holds the destination type. This map should be sparse, so don't hold 1697 /// it as an array. 1698 /// 1699 /// Targets add entries to this map with AddPromotedToType(..), clients access 1700 /// this with getTypeToPromoteTo(..). 1701 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1702 PromoteToType; 1703 1704 /// LibcallRoutineNames - Stores the name each libcall. 1705 /// 1706 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1707 1708 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1709 /// of each of the comparison libcall against zero. 1710 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1711 1712 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1713 /// libcall. 1714 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1715 1716protected: 1717 /// When lowering \@llvm.memset this field specifies the maximum number of 1718 /// store operations that may be substituted for the call to memset. Targets 1719 /// must set this value based on the cost threshold for that target. Targets 1720 /// should assume that the memset will be done using as many of the largest 1721 /// store operations first, followed by smaller ones, if necessary, per 1722 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1723 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1724 /// store. This only applies to setting a constant array of a constant size. 1725 /// @brief Specify maximum number of store instructions per memset call. 1726 unsigned maxStoresPerMemset; 1727 1728 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1729 /// store operations that may be substituted for a call to memcpy. Targets 1730 /// must set this value based on the cost threshold for that target. Targets 1731 /// should assume that the memcpy will be done using as many of the largest 1732 /// store operations first, followed by smaller ones, if necessary, per 1733 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1734 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1735 /// and one 1-byte store. This only applies to copying a constant array of 1736 /// constant size. 1737 /// @brief Specify maximum bytes of store instructions per memcpy call. 1738 unsigned maxStoresPerMemcpy; 1739 1740 /// When lowering \@llvm.memmove this field specifies the maximum number of 1741 /// store instructions that may be substituted for a call to memmove. Targets 1742 /// must set this value based on the cost threshold for that target. Targets 1743 /// should assume that the memmove will be done using as many of the largest 1744 /// store operations first, followed by smaller ones, if necessary, per 1745 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1746 /// with 8-bit alignment would result in nine 1-byte stores. This only 1747 /// applies to copying a constant array of constant size. 1748 /// @brief Specify maximum bytes of store instructions per memmove call. 1749 unsigned maxStoresPerMemmove; 1750 1751 /// This field specifies whether the target can benefit from code placement 1752 /// optimization. 1753 bool benefitFromCodePlacementOpt; 1754 1755private: 1756 /// isLegalRC - Return true if the value types that can be represented by the 1757 /// specified register class are all legal. 1758 bool isLegalRC(const TargetRegisterClass *RC) const; 1759 1760 /// hasLegalSuperRegRegClasses - Return true if the specified register class 1761 /// has one or more super-reg register classes that are legal. 1762 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const; 1763}; 1764 1765/// GetReturnInfo - Given an LLVM IR type and return type attributes, 1766/// compute the return value EVTs and flags, and optionally also 1767/// the offsets, if the return value is being lowered to memory. 1768void GetReturnInfo(const Type* ReturnType, Attributes attr, 1769 SmallVectorImpl<ISD::OutputArg> &Outs, 1770 const TargetLowering &TLI, 1771 SmallVectorImpl<uint64_t> *Offsets = 0); 1772 1773} // end llvm namespace 1774 1775#endif 1776