TargetLowering.h revision dae9cbe8d4fcd8f182a99403d67cae906bdb3175
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/Type.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include <map> 28#include <list> 29 30namespace llvm { 31 class Value; 32 class Function; 33 class TargetMachine; 34 class TargetData; 35 class TargetRegisterClass; 36 class SDNode; 37 class SDOperand; 38 class SelectionDAG; 39 class MachineBasicBlock; 40 class MachineInstr; 41 42//===----------------------------------------------------------------------===// 43/// TargetLowering - This class defines information used to lower LLVM code to 44/// legal SelectionDAG operators that the target instruction selector can accept 45/// natively. 46/// 47/// This class also defines callbacks that targets must implement to lower 48/// target-specific constructs to SelectionDAG operators. 49/// 50class TargetLowering { 51public: 52 /// LegalizeAction - This enum indicates whether operations are valid for a 53 /// target, and if not, what action should be used to make them valid. 54 enum LegalizeAction { 55 Legal, // The target natively supports this operation. 56 Promote, // This operation should be executed in a larger type. 57 Expand, // Try to expand this to other ops, otherwise use a libcall. 58 Custom // Use the LowerOperation hook to implement custom lowering. 59 }; 60 61 enum OutOfRangeShiftAmount { 62 Undefined, // Oversized shift amounts are undefined (default). 63 Mask, // Shift amounts are auto masked (anded) to value size. 64 Extend // Oversized shift pulls in zeros or sign bits. 65 }; 66 67 enum SetCCResultValue { 68 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 69 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 70 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 71 }; 72 73 enum SchedPreference { 74 SchedulingForLatency, // Scheduling for shortest total latency. 75 SchedulingForRegPressure // Scheduling for lowest register pressure. 76 }; 77 78 TargetLowering(TargetMachine &TM); 79 virtual ~TargetLowering(); 80 81 TargetMachine &getTargetMachine() const { return TM; } 82 const TargetData *getTargetData() const { return TD; } 83 84 bool isLittleEndian() const { return IsLittleEndian; } 85 MVT::ValueType getPointerTy() const { return PointerTy; } 86 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 87 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 88 89 /// isSetCCExpensive - Return true if the setcc operation is expensive for 90 /// this target. 91 bool isSetCCExpensive() const { return SetCCIsExpensive; } 92 93 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 94 /// a sequence of several shifts, adds, and multiplies for this target. 95 bool isIntDivCheap() const { return IntDivIsCheap; } 96 97 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 98 /// srl/add/sra. 99 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 100 101 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 102 /// 103 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 104 105 /// getSetCCResultContents - For targets without boolean registers, this flag 106 /// returns information about the contents of the high-bits in the setcc 107 /// result register. 108 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 109 110 /// getSchedulingPreference - Return target scheduling preference. 111 SchedPreference getSchedulingPreference() const { 112 return SchedPreferenceInfo; 113 } 114 115 /// getRegClassFor - Return the register class that should be used for the 116 /// specified value type. This may only be called on legal types. 117 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 118 TargetRegisterClass *RC = RegClassForVT[VT]; 119 assert(RC && "This value type is not natively supported!"); 120 return RC; 121 } 122 123 /// isTypeLegal - Return true if the target has native support for the 124 /// specified value type. This means that it has a register that directly 125 /// holds it without promotions or expansions. 126 bool isTypeLegal(MVT::ValueType VT) const { 127 return RegClassForVT[VT] != 0; 128 } 129 130 class ValueTypeActionImpl { 131 /// ValueTypeActions - This is a bitvector that contains two bits for each 132 /// value type, where the two bits correspond to the LegalizeAction enum. 133 /// This can be queried with "getTypeAction(VT)". 134 uint32_t ValueTypeActions[2]; 135 public: 136 ValueTypeActionImpl() { 137 ValueTypeActions[0] = ValueTypeActions[1] = 0; 138 } 139 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 140 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 141 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 142 } 143 144 LegalizeAction getTypeAction(MVT::ValueType VT) const { 145 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 146 } 147 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 148 assert(unsigned(VT >> 4) < 149 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 150 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 151 } 152 }; 153 154 const ValueTypeActionImpl &getValueTypeActions() const { 155 return ValueTypeActions; 156 } 157 158 /// getTypeAction - Return how we should legalize values of this type, either 159 /// it is already legal (return 'Legal') or we need to promote it to a larger 160 /// type (return 'Promote'), or we need to expand it into multiple registers 161 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 162 LegalizeAction getTypeAction(MVT::ValueType VT) const { 163 return ValueTypeActions.getTypeAction(VT); 164 } 165 166 /// getTypeToTransformTo - For types supported by the target, this is an 167 /// identity function. For types that must be promoted to larger types, this 168 /// returns the larger type to promote to. For types that are larger than the 169 /// largest integer register, this contains one step in the expansion to get 170 /// to the smaller register. 171 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 172 return TransformToType[VT]; 173 } 174 175 /// getPackedTypeBreakdown - Packed types are broken down into some number of 176 /// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values 177 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 178 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86. 179 /// 180 /// This method returns the number of registers needed, and the VT for each 181 /// register. It also returns the VT of the PackedType elements before they 182 /// are promoted/expanded. 183 /// 184 unsigned getPackedTypeBreakdown(const PackedType *PTy, 185 MVT::ValueType &PTyElementVT, 186 MVT::ValueType &PTyLegalElementVT) const; 187 188 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 189 legal_fpimm_iterator legal_fpimm_begin() const { 190 return LegalFPImmediates.begin(); 191 } 192 legal_fpimm_iterator legal_fpimm_end() const { 193 return LegalFPImmediates.end(); 194 } 195 196 /// isShuffleMaskLegal - Targets can use this to indicate that they only 197 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 198 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 199 /// are assumed to be legal. 200 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 201 return true; 202 } 203 204 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 205 /// used by Targets can use this to indicate if there is a suitable 206 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 207 /// pool entry. 208 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 209 MVT::ValueType EVT, 210 SelectionDAG &DAG) const { 211 return false; 212 } 213 214 /// getOperationAction - Return how this operation should be treated: either 215 /// it is legal, needs to be promoted to a larger size, needs to be 216 /// expanded to some other code sequence, or the target has a custom expander 217 /// for it. 218 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 219 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 220 } 221 222 /// isOperationLegal - Return true if the specified operation is legal on this 223 /// target. 224 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 225 return getOperationAction(Op, VT) == Legal || 226 getOperationAction(Op, VT) == Custom; 227 } 228 229 /// getTypeToPromoteTo - If the action for this operation is to promote, this 230 /// method returns the ValueType to promote to. 231 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 232 assert(getOperationAction(Op, VT) == Promote && 233 "This operation isn't promoted!"); 234 235 // See if this has an explicit type specified. 236 std::map<std::pair<unsigned, MVT::ValueType>, 237 MVT::ValueType>::const_iterator PTTI = 238 PromoteToType.find(std::make_pair(Op, VT)); 239 if (PTTI != PromoteToType.end()) return PTTI->second; 240 241 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 242 "Cannot autopromote this type, add it with AddPromotedToType."); 243 244 MVT::ValueType NVT = VT; 245 do { 246 NVT = (MVT::ValueType)(NVT+1); 247 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 248 "Didn't find type to promote to!"); 249 } while (!isTypeLegal(NVT) || 250 getOperationAction(Op, NVT) == Promote); 251 return NVT; 252 } 253 254 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 255 /// This is fixed by the LLVM operations except for the pointer size. 256 MVT::ValueType getValueType(const Type *Ty) const { 257 switch (Ty->getTypeID()) { 258 default: assert(0 && "Unknown type!"); 259 case Type::VoidTyID: return MVT::isVoid; 260 case Type::BoolTyID: return MVT::i1; 261 case Type::UByteTyID: 262 case Type::SByteTyID: return MVT::i8; 263 case Type::ShortTyID: 264 case Type::UShortTyID: return MVT::i16; 265 case Type::IntTyID: 266 case Type::UIntTyID: return MVT::i32; 267 case Type::LongTyID: 268 case Type::ULongTyID: return MVT::i64; 269 case Type::FloatTyID: return MVT::f32; 270 case Type::DoubleTyID: return MVT::f64; 271 case Type::PointerTyID: return PointerTy; 272 case Type::PackedTyID: return MVT::Vector; 273 } 274 } 275 276 /// getNumElements - Return the number of registers that this ValueType will 277 /// eventually require. This is always one for all non-integer types, is 278 /// one for any types promoted to live in larger registers, but may be more 279 /// than one for types (like i64) that are split into pieces. 280 unsigned getNumElements(MVT::ValueType VT) const { 281 return NumElementsForVT[VT]; 282 } 283 284 /// hasTargetDAGCombine - If true, the target has custom DAG combine 285 /// transformations that it can perform for the specified node. 286 bool hasTargetDAGCombine(ISD::NodeType NT) const { 287 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 288 } 289 290 /// This function returns the maximum number of store operations permitted 291 /// to replace a call to llvm.memset. The value is set by the target at the 292 /// performance threshold for such a replacement. 293 /// @brief Get maximum # of store operations permitted for llvm.memset 294 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 295 296 /// This function returns the maximum number of store operations permitted 297 /// to replace a call to llvm.memcpy. The value is set by the target at the 298 /// performance threshold for such a replacement. 299 /// @brief Get maximum # of store operations permitted for llvm.memcpy 300 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 301 302 /// This function returns the maximum number of store operations permitted 303 /// to replace a call to llvm.memmove. The value is set by the target at the 304 /// performance threshold for such a replacement. 305 /// @brief Get maximum # of store operations permitted for llvm.memmove 306 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 307 308 /// This function returns true if the target allows unaligned memory accesses. 309 /// This is used, for example, in situations where an array copy/move/set is 310 /// converted to a sequence of store operations. It's use helps to ensure that 311 /// such replacements don't generate code that causes an alignment error 312 /// (trap) on the target machine. 313 /// @brief Determine if the target supports unaligned memory accesses. 314 bool allowsUnalignedMemoryAccesses() const { 315 return allowUnalignedMemoryAccesses; 316 } 317 318 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp 319 /// to implement llvm.setjmp. 320 bool usesUnderscoreSetJmpLongJmp() const { 321 return UseUnderscoreSetJmpLongJmp; 322 } 323 324 /// getStackPointerRegisterToSaveRestore - If a physical register, this 325 /// specifies the register that llvm.savestack/llvm.restorestack should save 326 /// and restore. 327 unsigned getStackPointerRegisterToSaveRestore() const { 328 return StackPointerRegisterToSaveRestore; 329 } 330 331 //===--------------------------------------------------------------------===// 332 // TargetLowering Optimization Methods 333 // 334 335 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 336 /// SDOperands for returning information from TargetLowering to its clients 337 /// that want to combine 338 struct TargetLoweringOpt { 339 SelectionDAG &DAG; 340 SDOperand Old; 341 SDOperand New; 342 343 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 344 345 bool CombineTo(SDOperand O, SDOperand N) { 346 Old = O; 347 New = N; 348 return true; 349 } 350 351 /// ShrinkDemandedConstant - Check to see if the specified operand of the 352 /// specified instruction is a constant integer. If so, check to see if there 353 /// are any bits set in the constant that are not demanded. If so, shrink the 354 /// constant and return true. 355 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 356 }; 357 358 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We 359 /// use this predicate to simplify operations downstream. Op and Mask are 360 /// known to be the same type. 361 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) 362 const; 363 364 /// ComputeMaskedBits - Determine which of the bits specified in Mask are 365 /// known to be either zero or one and return them in the KnownZero/KnownOne 366 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit 367 /// processing. Targets can implement the computeMaskedBitsForTargetNode 368 /// method, to allow target nodes to be understood. 369 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, 370 uint64_t &KnownOne, unsigned Depth = 0) const; 371 372 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 373 /// DemandedMask bits of the result of Op are ever used downstream. If we can 374 /// use this information to simplify Op, create a new simplified DAG node and 375 /// return true, returning the original and new nodes in Old and New. 376 /// Otherwise, analyze the expression and return a mask of KnownOne and 377 /// KnownZero bits for the expression (used to simplify the caller). 378 /// The KnownZero/One bits may only be accurate for those bits in the 379 /// DemandedMask. 380 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 381 uint64_t &KnownZero, uint64_t &KnownOne, 382 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 383 384 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 385 /// Mask are known to be either zero or one and return them in the 386 /// KnownZero/KnownOne bitsets. 387 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 388 uint64_t Mask, 389 uint64_t &KnownZero, 390 uint64_t &KnownOne, 391 unsigned Depth = 0) const; 392 393 /// ComputeNumSignBits - Return the number of times the sign bit of the 394 /// register is replicated into the other bits. We know that at least 1 bit 395 /// is always equal to the sign bit (itself), but other cases can give us 396 /// information. For example, immediately after an "SRA X, 2", we know that 397 /// the top 3 bits are all equal to each other, so we return 3. 398 unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const; 399 400 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 401 /// targets that want to expose additional information about sign bits to the 402 /// DAG Combiner. 403 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 404 unsigned Depth = 0) const; 405 406 struct DAGCombinerInfo { 407 void *DC; // The DAG Combiner object. 408 bool BeforeLegalize; 409 public: 410 SelectionDAG &DAG; 411 412 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc) 413 : DC(dc), BeforeLegalize(bl), DAG(dag) {} 414 415 bool isBeforeLegalize() const { return BeforeLegalize; } 416 417 void AddToWorklist(SDNode *N); 418 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 419 SDOperand CombineTo(SDNode *N, SDOperand Res); 420 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 421 }; 422 423 /// PerformDAGCombine - This method will be invoked for all target nodes and 424 /// for any target-independent nodes that the target has registered with 425 /// invoke it for. 426 /// 427 /// The semantics are as follows: 428 /// Return Value: 429 /// SDOperand.Val == 0 - No change was made 430 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 431 /// otherwise - N should be replaced by the returned Operand. 432 /// 433 /// In addition, methods provided by DAGCombinerInfo may be used to perform 434 /// more complex transformations. 435 /// 436 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 437 438 //===--------------------------------------------------------------------===// 439 // TargetLowering Configuration Methods - These methods should be invoked by 440 // the derived class constructor to configure this object for the target. 441 // 442 443protected: 444 445 /// setShiftAmountType - Describe the type that should be used for shift 446 /// amounts. This type defaults to the pointer type. 447 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 448 449 /// setSetCCResultType - Describe the type that shoudl be used as the result 450 /// of a setcc operation. This defaults to the pointer type. 451 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 452 453 /// setSetCCResultContents - Specify how the target extends the result of a 454 /// setcc operation in a register. 455 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 456 457 /// setSchedulingPreference - Specify the target scheduling preference. 458 void setSchedulingPreference(SchedPreference Pref) { 459 SchedPreferenceInfo = Pref; 460 } 461 462 /// setShiftAmountFlavor - Describe how the target handles out of range shift 463 /// amounts. 464 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 465 ShiftAmtHandling = OORSA; 466 } 467 468 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to 469 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or 470 /// the non _ versions. Defaults to false. 471 void setUseUnderscoreSetJmpLongJmp(bool Val) { 472 UseUnderscoreSetJmpLongJmp = Val; 473 } 474 475 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 476 /// specifies the register that llvm.savestack/llvm.restorestack should save 477 /// and restore. 478 void setStackPointerRegisterToSaveRestore(unsigned R) { 479 StackPointerRegisterToSaveRestore = R; 480 } 481 482 /// setSetCCIxExpensive - This is a short term hack for targets that codegen 483 /// setcc as a conditional branch. This encourages the code generator to fold 484 /// setcc operations into other operations if possible. 485 void setSetCCIsExpensive() { SetCCIsExpensive = true; } 486 487 /// setIntDivIsCheap - Tells the code generator that integer divide is 488 /// expensive, and if possible, should be replaced by an alternate sequence 489 /// of instructions not containing an integer divide. 490 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 491 492 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 493 /// srl/add/sra for a signed divide by power of two, and let the target handle 494 /// it. 495 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 496 497 /// addRegisterClass - Add the specified register class as an available 498 /// regclass for the specified value type. This indicates the selector can 499 /// handle values of that class natively. 500 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 501 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 502 RegClassForVT[VT] = RC; 503 } 504 505 /// computeRegisterProperties - Once all of the register classes are added, 506 /// this allows us to compute derived properties we expose. 507 void computeRegisterProperties(); 508 509 /// setOperationAction - Indicate that the specified operation does not work 510 /// with the specified type and indicate what to do about it. 511 void setOperationAction(unsigned Op, MVT::ValueType VT, 512 LegalizeAction Action) { 513 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 514 "Table isn't big enough!"); 515 OpActions[Op] &= ~(3ULL << VT*2); 516 OpActions[Op] |= (uint64_t)Action << VT*2; 517 } 518 519 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 520 /// promotion code defaults to trying a larger integer/fp until it can find 521 /// one that works. If that default is insufficient, this method can be used 522 /// by the target to override the default. 523 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 524 MVT::ValueType DestVT) { 525 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 526 } 527 528 /// addLegalFPImmediate - Indicate that this target can instruction select 529 /// the specified FP immediate natively. 530 void addLegalFPImmediate(double Imm) { 531 LegalFPImmediates.push_back(Imm); 532 } 533 534 /// setTargetDAGCombine - Targets should invoke this method for each target 535 /// independent node that they want to provide a custom DAG combiner for by 536 /// implementing the PerformDAGCombine virtual method. 537 void setTargetDAGCombine(ISD::NodeType NT) { 538 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 539 } 540 541public: 542 543 //===--------------------------------------------------------------------===// 544 // Lowering methods - These methods must be implemented by targets so that 545 // the SelectionDAGLowering code knows how to lower these. 546 // 547 548 /// LowerArguments - This hook must be implemented to indicate how we should 549 /// lower the arguments for the specified function, into the specified DAG. 550 virtual std::vector<SDOperand> 551 LowerArguments(Function &F, SelectionDAG &DAG); 552 553 /// LowerCallTo - This hook lowers an abstract call to a function into an 554 /// actual call. This returns a pair of operands. The first element is the 555 /// return value for the function (if RetTy is not VoidTy). The second 556 /// element is the outgoing token chain. 557 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy; 558 virtual std::pair<SDOperand, SDOperand> 559 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 560 unsigned CallingConv, bool isTailCall, SDOperand Callee, 561 ArgListTy &Args, SelectionDAG &DAG) = 0; 562 563 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or 564 /// llvm.frameaddress (depending on the value of the first argument). The 565 /// return values are the result pointer and the resultant token chain. If 566 /// not implemented, both of these intrinsics will return null. 567 virtual std::pair<SDOperand, SDOperand> 568 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 569 SelectionDAG &DAG); 570 571 /// LowerOperation - This callback is invoked for operations that are 572 /// unsupported by the target, which are registered to use 'custom' lowering, 573 /// and whose defined values are all legal. 574 /// If the target has no operations that require custom lowering, it need not 575 /// implement this. The default implementation of this aborts. 576 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 577 578 /// CustomPromoteOperation - This callback is invoked for operations that are 579 /// unsupported by the target, are registered to use 'custom' lowering, and 580 /// whose type needs to be promoted. 581 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 582 583 /// getTargetNodeName() - This method returns the name of a target specific 584 /// DAG node. 585 virtual const char *getTargetNodeName(unsigned Opcode) const; 586 587 //===--------------------------------------------------------------------===// 588 // Inline Asm Support hooks 589 // 590 591 enum ConstraintType { 592 C_Register, // Constraint represents a single register. 593 C_RegisterClass, // Constraint represents one or more registers. 594 C_Memory, // Memory constraint. 595 C_Other, // Something else. 596 C_Unknown // Unsupported constraint. 597 }; 598 599 /// getConstraintType - Given a constraint letter, return the type of 600 /// constraint it is for this target. 601 virtual ConstraintType getConstraintType(char ConstraintLetter) const; 602 603 604 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 605 /// return a list of registers that can be used to satisfy the constraint. 606 /// This should only be used for C_RegisterClass constraints. 607 virtual std::vector<unsigned> 608 getRegClassForInlineAsmConstraint(const std::string &Constraint, 609 MVT::ValueType VT) const; 610 611 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 612 /// {edx}), return the register number and the register class for the 613 /// register. This should only be used for C_Register constraints. On error, 614 /// this returns a register number of 0. 615 virtual std::pair<unsigned, const TargetRegisterClass*> 616 getRegForInlineAsmConstraint(const std::string &Constraint, 617 MVT::ValueType VT) const; 618 619 620 /// isOperandValidForConstraint - Return true if the specified SDOperand is 621 /// valid for the specified target constraint letter. 622 virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); 623 624 //===--------------------------------------------------------------------===// 625 // Scheduler hooks 626 // 627 628 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 629 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 630 // instructions are special in various ways, which require special support to 631 // insert. The specified MachineInstr is created but not inserted into any 632 // basic blocks, and the scheduler passes ownership of it to this method. 633 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 634 MachineBasicBlock *MBB); 635 636 //===--------------------------------------------------------------------===// 637 // Loop Strength Reduction hooks 638 // 639 640 /// isLegalAddressImmediate - Return true if the integer value or GlobalValue 641 /// can be used as the offset of the target addressing mode. 642 virtual bool isLegalAddressImmediate(int64_t V) const; 643 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 644 645 typedef std::vector<unsigned>::const_iterator legal_am_scale_iterator; 646 legal_am_scale_iterator legal_am_scale_begin() const { 647 return LegalAddressScales.begin(); 648 } 649 legal_am_scale_iterator legal_am_scale_end() const { 650 return LegalAddressScales.end(); 651 } 652 653 //===--------------------------------------------------------------------===// 654 // Div utility functions 655 // 656 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 657 std::list<SDNode*>* Created) const; 658 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 659 std::list<SDNode*>* Created) const; 660 661 662protected: 663 /// addLegalAddressScale - Add a integer (> 1) value which can be used as 664 /// scale in the target addressing mode. Note: the ordering matters so the 665 /// least efficient ones should be entered first. 666 void addLegalAddressScale(unsigned Scale) { 667 LegalAddressScales.push_back(Scale); 668 } 669 670private: 671 std::vector<unsigned> LegalAddressScales; 672 673 TargetMachine &TM; 674 const TargetData *TD; 675 676 /// IsLittleEndian - True if this is a little endian target. 677 /// 678 bool IsLittleEndian; 679 680 /// PointerTy - The type to use for pointers, usually i32 or i64. 681 /// 682 MVT::ValueType PointerTy; 683 684 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 685 /// PointerTy is. 686 MVT::ValueType ShiftAmountTy; 687 688 OutOfRangeShiftAmount ShiftAmtHandling; 689 690 /// SetCCIsExpensive - This is a short term hack for targets that codegen 691 /// setcc as a conditional branch. This encourages the code generator to fold 692 /// setcc operations into other operations if possible. 693 bool SetCCIsExpensive; 694 695 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 696 /// constants into a sequence of muls, adds, and shifts. This is a hack until 697 /// a real cost model is in place. If we ever optimize for size, this will be 698 /// set to true unconditionally. 699 bool IntDivIsCheap; 700 701 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 702 /// srl/add/sra for a signed divide by power of two, and let the target handle 703 /// it. 704 bool Pow2DivIsCheap; 705 706 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 707 /// PointerTy. 708 MVT::ValueType SetCCResultTy; 709 710 /// SetCCResultContents - Information about the contents of the high-bits in 711 /// the result of a setcc comparison operation. 712 SetCCResultValue SetCCResultContents; 713 714 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 715 /// total cycles or lowest register usage. 716 SchedPreference SchedPreferenceInfo; 717 718 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and 719 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false. 720 bool UseUnderscoreSetJmpLongJmp; 721 722 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 723 /// specifies the register that llvm.savestack/llvm.restorestack should save 724 /// and restore. 725 unsigned StackPointerRegisterToSaveRestore; 726 727 /// RegClassForVT - This indicates the default register class to use for 728 /// each ValueType the target supports natively. 729 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 730 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; 731 732 /// TransformToType - For any value types we are promoting or expanding, this 733 /// contains the value type that we are changing to. For Expanded types, this 734 /// contains one step of the expand (e.g. i64 -> i32), even if there are 735 /// multiple steps required (e.g. i64 -> i16). For types natively supported 736 /// by the system, this holds the same type (e.g. i32 -> i32). 737 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 738 739 /// OpActions - For each operation and each value type, keep a LegalizeAction 740 /// that indicates how instruction selection should deal with the operation. 741 /// Most operations are Legal (aka, supported natively by the target), but 742 /// operations that are not should be described. Note that operations on 743 /// non-legal value types are not described here. 744 uint64_t OpActions[156]; 745 746 ValueTypeActionImpl ValueTypeActions; 747 748 std::vector<double> LegalFPImmediates; 749 750 std::vector<std::pair<MVT::ValueType, 751 TargetRegisterClass*> > AvailableRegClasses; 752 753 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 754 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 755 /// which sets a bit in this array. 756 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 757 758 /// PromoteToType - For operations that must be promoted to a specific type, 759 /// this holds the destination type. This map should be sparse, so don't hold 760 /// it as an array. 761 /// 762 /// Targets add entries to this map with AddPromotedToType(..), clients access 763 /// this with getTypeToPromoteTo(..). 764 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 765 766protected: 767 /// When lowering %llvm.memset this field specifies the maximum number of 768 /// store operations that may be substituted for the call to memset. Targets 769 /// must set this value based on the cost threshold for that target. Targets 770 /// should assume that the memset will be done using as many of the largest 771 /// store operations first, followed by smaller ones, if necessary, per 772 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 773 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 774 /// store. This only applies to setting a constant array of a constant size. 775 /// @brief Specify maximum number of store instructions per memset call. 776 unsigned maxStoresPerMemset; 777 778 /// When lowering %llvm.memcpy this field specifies the maximum number of 779 /// store operations that may be substituted for a call to memcpy. Targets 780 /// must set this value based on the cost threshold for that target. Targets 781 /// should assume that the memcpy will be done using as many of the largest 782 /// store operations first, followed by smaller ones, if necessary, per 783 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 784 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 785 /// and one 1-byte store. This only applies to copying a constant array of 786 /// constant size. 787 /// @brief Specify maximum bytes of store instructions per memcpy call. 788 unsigned maxStoresPerMemcpy; 789 790 /// When lowering %llvm.memmove this field specifies the maximum number of 791 /// store instructions that may be substituted for a call to memmove. Targets 792 /// must set this value based on the cost threshold for that target. Targets 793 /// should assume that the memmove will be done using as many of the largest 794 /// store operations first, followed by smaller ones, if necessary, per 795 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 796 /// with 8-bit alignment would result in nine 1-byte stores. This only 797 /// applies to copying a constant array of constant size. 798 /// @brief Specify maximum bytes of store instructions per memmove call. 799 unsigned maxStoresPerMemmove; 800 801 /// This field specifies whether the target machine permits unaligned memory 802 /// accesses. This is used, for example, to determine the size of store 803 /// operations when copying small arrays and other similar tasks. 804 /// @brief Indicate whether the target permits unaligned memory accesses. 805 bool allowUnalignedMemoryAccesses; 806}; 807} // end llvm namespace 808 809#endif 810