TargetLowering.h revision f04afdbb48568ef09f11fd10ac03426101f2dbf8
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include "llvm/ADT/APFloat.h" 28#include <map> 29#include <vector> 30 31namespace llvm { 32 class Value; 33 class Function; 34 class TargetMachine; 35 class TargetData; 36 class TargetRegisterClass; 37 class SDNode; 38 class SDOperand; 39 class SelectionDAG; 40 class MachineBasicBlock; 41 class MachineInstr; 42 class VectorType; 43 44//===----------------------------------------------------------------------===// 45/// TargetLowering - This class defines information used to lower LLVM code to 46/// legal SelectionDAG operators that the target instruction selector can accept 47/// natively. 48/// 49/// This class also defines callbacks that targets must implement to lower 50/// target-specific constructs to SelectionDAG operators. 51/// 52class TargetLowering { 53public: 54 /// LegalizeAction - This enum indicates whether operations are valid for a 55 /// target, and if not, what action should be used to make them valid. 56 enum LegalizeAction { 57 Legal, // The target natively supports this operation. 58 Promote, // This operation should be executed in a larger type. 59 Expand, // Try to expand this to other ops, otherwise use a libcall. 60 Custom // Use the LowerOperation hook to implement custom lowering. 61 }; 62 63 enum OutOfRangeShiftAmount { 64 Undefined, // Oversized shift amounts are undefined (default). 65 Mask, // Shift amounts are auto masked (anded) to value size. 66 Extend // Oversized shift pulls in zeros or sign bits. 67 }; 68 69 enum SetCCResultValue { 70 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 71 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 72 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 73 }; 74 75 enum SchedPreference { 76 SchedulingForLatency, // Scheduling for shortest total latency. 77 SchedulingForRegPressure // Scheduling for lowest register pressure. 78 }; 79 80 explicit TargetLowering(TargetMachine &TM); 81 virtual ~TargetLowering(); 82 83 TargetMachine &getTargetMachine() const { return TM; } 84 const TargetData *getTargetData() const { return TD; } 85 86 bool isLittleEndian() const { return IsLittleEndian; } 87 MVT::ValueType getPointerTy() const { return PointerTy; } 88 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 89 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 90 91 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 92 /// codegen. 93 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 94 95 /// isSelectExpensive - Return true if the select operation is expensive for 96 /// this target. 97 bool isSelectExpensive() const { return SelectIsExpensive; } 98 99 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 100 /// a sequence of several shifts, adds, and multiplies for this target. 101 bool isIntDivCheap() const { return IntDivIsCheap; } 102 103 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 104 /// srl/add/sra. 105 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 106 107 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 108 /// 109 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 110 111 /// getSetCCResultContents - For targets without boolean registers, this flag 112 /// returns information about the contents of the high-bits in the setcc 113 /// result register. 114 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 115 116 /// getSchedulingPreference - Return target scheduling preference. 117 SchedPreference getSchedulingPreference() const { 118 return SchedPreferenceInfo; 119 } 120 121 /// getRegClassFor - Return the register class that should be used for the 122 /// specified value type. This may only be called on legal types. 123 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 124 assert(!MVT::isExtendedVT(VT)); 125 TargetRegisterClass *RC = RegClassForVT[VT]; 126 assert(RC && "This value type is not natively supported!"); 127 return RC; 128 } 129 130 /// isTypeLegal - Return true if the target has native support for the 131 /// specified value type. This means that it has a register that directly 132 /// holds it without promotions or expansions. 133 bool isTypeLegal(MVT::ValueType VT) const { 134 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; 135 } 136 137 class ValueTypeActionImpl { 138 /// ValueTypeActions - This is a bitvector that contains two bits for each 139 /// value type, where the two bits correspond to the LegalizeAction enum. 140 /// This can be queried with "getTypeAction(VT)". 141 uint32_t ValueTypeActions[2]; 142 public: 143 ValueTypeActionImpl() { 144 ValueTypeActions[0] = ValueTypeActions[1] = 0; 145 } 146 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 147 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 148 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 149 } 150 151 LegalizeAction getTypeAction(MVT::ValueType VT) const { 152 if (MVT::isExtendedVT(VT)) return Expand; 153 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 154 } 155 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 156 assert(!MVT::isExtendedVT(VT)); 157 assert(unsigned(VT >> 4) < 158 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 159 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 160 } 161 }; 162 163 const ValueTypeActionImpl &getValueTypeActions() const { 164 return ValueTypeActions; 165 } 166 167 /// getTypeAction - Return how we should legalize values of this type, either 168 /// it is already legal (return 'Legal') or we need to promote it to a larger 169 /// type (return 'Promote'), or we need to expand it into multiple registers 170 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 171 LegalizeAction getTypeAction(MVT::ValueType VT) const { 172 return ValueTypeActions.getTypeAction(VT); 173 } 174 175 /// getTypeToTransformTo - For types supported by the target, this is an 176 /// identity function. For types that must be promoted to larger types, this 177 /// returns the larger type to promote to. For integer types that are larger 178 /// than the largest integer register, this contains one step in the expansion 179 /// to get to the smaller register. For illegal floating point types, this 180 /// returns the integer type to transform to. 181 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 182 if (MVT::isExtendedVT(VT)) 183 return MVT::getVectorType(MVT::getVectorElementType(VT), 184 MVT::getVectorNumElements(VT) / 2); 185 186 return TransformToType[VT]; 187 } 188 189 /// getTypeToExpandTo - For types supported by the target, this is an 190 /// identity function. For types that must be expanded (i.e. integer types 191 /// that are larger than the largest integer register or illegal floating 192 /// point types), this returns the largest legal type it will be expanded to. 193 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 194 assert(!MVT::isExtendedVT(VT)); 195 while (true) { 196 switch (getTypeAction(VT)) { 197 case Legal: 198 return VT; 199 case Expand: 200 VT = getTypeToTransformTo(VT); 201 break; 202 default: 203 assert(false && "Type is not legal nor is it to be expanded!"); 204 return VT; 205 } 206 } 207 return VT; 208 } 209 210 /// getVectorTypeBreakdown - Vector types are broken down into some number of 211 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 212 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 213 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 214 /// 215 /// This method returns the number of registers needed, and the VT for each 216 /// register. It also returns the VT and quantity of the intermediate values 217 /// before they are promoted/expanded. 218 /// 219 unsigned getVectorTypeBreakdown(MVT::ValueType VT, 220 MVT::ValueType &IntermediateVT, 221 unsigned &NumIntermediates, 222 MVT::ValueType &RegisterVT) const; 223 224 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 225 legal_fpimm_iterator legal_fpimm_begin() const { 226 return LegalFPImmediates.begin(); 227 } 228 legal_fpimm_iterator legal_fpimm_end() const { 229 return LegalFPImmediates.end(); 230 } 231 232 /// isShuffleMaskLegal - Targets can use this to indicate that they only 233 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 234 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 235 /// are assumed to be legal. 236 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 237 return true; 238 } 239 240 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 241 /// used by Targets can use this to indicate if there is a suitable 242 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 243 /// pool entry. 244 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 245 MVT::ValueType EVT, 246 SelectionDAG &DAG) const { 247 return false; 248 } 249 250 /// getOperationAction - Return how this operation should be treated: either 251 /// it is legal, needs to be promoted to a larger size, needs to be 252 /// expanded to some other code sequence, or the target has a custom expander 253 /// for it. 254 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 255 if (MVT::isExtendedVT(VT)) return Expand; 256 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 257 } 258 259 /// isOperationLegal - Return true if the specified operation is legal on this 260 /// target. 261 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 262 return getOperationAction(Op, VT) == Legal || 263 getOperationAction(Op, VT) == Custom; 264 } 265 266 /// getLoadXAction - Return how this load with extension should be treated: 267 /// either it is legal, needs to be promoted to a larger size, needs to be 268 /// expanded to some other code sequence, or the target has a custom expander 269 /// for it. 270 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 271 if (MVT::isExtendedVT(VT)) return Expand; 272 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); 273 } 274 275 /// isLoadXLegal - Return true if the specified load with extension is legal 276 /// on this target. 277 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 278 return getLoadXAction(LType, VT) == Legal || 279 getLoadXAction(LType, VT) == Custom; 280 } 281 282 /// getStoreXAction - Return how this store with truncation should be treated: 283 /// either it is legal, needs to be promoted to a larger size, needs to be 284 /// expanded to some other code sequence, or the target has a custom expander 285 /// for it. 286 LegalizeAction getStoreXAction(MVT::ValueType VT) const { 287 if (MVT::isExtendedVT(VT)) return Expand; 288 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3); 289 } 290 291 /// isStoreXLegal - Return true if the specified store with truncation is 292 /// legal on this target. 293 bool isStoreXLegal(MVT::ValueType VT) const { 294 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom; 295 } 296 297 /// getIndexedLoadAction - Return how the indexed load should be treated: 298 /// either it is legal, needs to be promoted to a larger size, needs to be 299 /// expanded to some other code sequence, or the target has a custom expander 300 /// for it. 301 LegalizeAction 302 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 303 if (MVT::isExtendedVT(VT)) return Expand; 304 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); 305 } 306 307 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 308 /// on this target. 309 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 310 return getIndexedLoadAction(IdxMode, VT) == Legal || 311 getIndexedLoadAction(IdxMode, VT) == Custom; 312 } 313 314 /// getIndexedStoreAction - Return how the indexed store should be treated: 315 /// either it is legal, needs to be promoted to a larger size, needs to be 316 /// expanded to some other code sequence, or the target has a custom expander 317 /// for it. 318 LegalizeAction 319 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 320 if (MVT::isExtendedVT(VT)) return Expand; 321 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); 322 } 323 324 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 325 /// on this target. 326 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 327 return getIndexedStoreAction(IdxMode, VT) == Legal || 328 getIndexedStoreAction(IdxMode, VT) == Custom; 329 } 330 331 /// getConvertAction - Return how the conversion should be treated: 332 /// either it is legal, needs to be promoted to a larger size, needs to be 333 /// expanded to some other code sequence, or the target has a custom expander 334 /// for it. 335 LegalizeAction 336 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 337 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 && 338 "Table isn't big enough!"); 339 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3); 340 } 341 342 /// isConvertLegal - Return true if the specified conversion is legal 343 /// on this target. 344 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 345 return getConvertAction(FromVT, ToVT) == Legal || 346 getConvertAction(FromVT, ToVT) == Custom; 347 } 348 349 /// getTypeToPromoteTo - If the action for this operation is to promote, this 350 /// method returns the ValueType to promote to. 351 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 352 assert(getOperationAction(Op, VT) == Promote && 353 "This operation isn't promoted!"); 354 355 // See if this has an explicit type specified. 356 std::map<std::pair<unsigned, MVT::ValueType>, 357 MVT::ValueType>::const_iterator PTTI = 358 PromoteToType.find(std::make_pair(Op, VT)); 359 if (PTTI != PromoteToType.end()) return PTTI->second; 360 361 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 362 "Cannot autopromote this type, add it with AddPromotedToType."); 363 364 MVT::ValueType NVT = VT; 365 do { 366 NVT = (MVT::ValueType)(NVT+1); 367 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 368 "Didn't find type to promote to!"); 369 } while (!isTypeLegal(NVT) || 370 getOperationAction(Op, NVT) == Promote); 371 return NVT; 372 } 373 374 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 375 /// This is fixed by the LLVM operations except for the pointer size. If 376 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 377 /// counterpart (e.g. structs), otherwise it will assert. 378 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { 379 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); 380 return VT == MVT::iPTR ? PointerTy : VT; 381 } 382 383 /// getRegisterType - Return the type of registers that this ValueType will 384 /// eventually require. 385 MVT::ValueType getRegisterType(MVT::ValueType VT) const { 386 if (!MVT::isExtendedVT(VT)) 387 return RegisterTypeForVT[VT]; 388 389 MVT::ValueType VT1, RegisterVT; 390 unsigned NumIntermediates; 391 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 392 return RegisterVT; 393 } 394 395 /// getNumRegisters - Return the number of registers that this ValueType will 396 /// eventually require. This is one for any types promoted to live in larger 397 /// registers, but may be more than one for types (like i64) that are split 398 /// into pieces. 399 unsigned getNumRegisters(MVT::ValueType VT) const { 400 if (!MVT::isExtendedVT(VT)) 401 return NumRegistersForVT[VT]; 402 403 MVT::ValueType VT1, VT2; 404 unsigned NumIntermediates; 405 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 406 } 407 408 /// hasTargetDAGCombine - If true, the target has custom DAG combine 409 /// transformations that it can perform for the specified node. 410 bool hasTargetDAGCombine(ISD::NodeType NT) const { 411 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 412 } 413 414 /// This function returns the maximum number of store operations permitted 415 /// to replace a call to llvm.memset. The value is set by the target at the 416 /// performance threshold for such a replacement. 417 /// @brief Get maximum # of store operations permitted for llvm.memset 418 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 419 420 /// This function returns the maximum number of store operations permitted 421 /// to replace a call to llvm.memcpy. The value is set by the target at the 422 /// performance threshold for such a replacement. 423 /// @brief Get maximum # of store operations permitted for llvm.memcpy 424 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 425 426 /// This function returns the maximum number of store operations permitted 427 /// to replace a call to llvm.memmove. The value is set by the target at the 428 /// performance threshold for such a replacement. 429 /// @brief Get maximum # of store operations permitted for llvm.memmove 430 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 431 432 /// This function returns true if the target allows unaligned memory accesses. 433 /// This is used, for example, in situations where an array copy/move/set is 434 /// converted to a sequence of store operations. It's use helps to ensure that 435 /// such replacements don't generate code that causes an alignment error 436 /// (trap) on the target machine. 437 /// @brief Determine if the target supports unaligned memory accesses. 438 bool allowsUnalignedMemoryAccesses() const { 439 return allowUnalignedMemoryAccesses; 440 } 441 442 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 443 /// to implement llvm.setjmp. 444 bool usesUnderscoreSetJmp() const { 445 return UseUnderscoreSetJmp; 446 } 447 448 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 449 /// to implement llvm.longjmp. 450 bool usesUnderscoreLongJmp() const { 451 return UseUnderscoreLongJmp; 452 } 453 454 /// getStackPointerRegisterToSaveRestore - If a physical register, this 455 /// specifies the register that llvm.savestack/llvm.restorestack should save 456 /// and restore. 457 unsigned getStackPointerRegisterToSaveRestore() const { 458 return StackPointerRegisterToSaveRestore; 459 } 460 461 /// getExceptionAddressRegister - If a physical register, this returns 462 /// the register that receives the exception address on entry to a landing 463 /// pad. 464 unsigned getExceptionAddressRegister() const { 465 return ExceptionPointerRegister; 466 } 467 468 /// getExceptionSelectorRegister - If a physical register, this returns 469 /// the register that receives the exception typeid on entry to a landing 470 /// pad. 471 unsigned getExceptionSelectorRegister() const { 472 return ExceptionSelectorRegister; 473 } 474 475 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 476 /// set, the default is 200) 477 unsigned getJumpBufSize() const { 478 return JumpBufSize; 479 } 480 481 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 482 /// (if never set, the default is 0) 483 unsigned getJumpBufAlignment() const { 484 return JumpBufAlignment; 485 } 486 487 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 488 /// limit. Any block whose size is greater should not be predicated. 489 virtual unsigned getIfCvtBlockSizeLimit() const { 490 return IfCvtBlockSizeLimit; 491 } 492 493 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 494 /// block to be considered for duplication. Any block whose size is greater 495 /// should not be duplicated to facilitate its predication. 496 virtual unsigned getIfCvtDupBlockSizeLimit() const { 497 return IfCvtDupBlockSizeLimit; 498 } 499 500 /// getPreIndexedAddressParts - returns true by value, base pointer and 501 /// offset pointer and addressing mode by reference if the node's address 502 /// can be legally represented as pre-indexed load / store address. 503 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 504 SDOperand &Offset, 505 ISD::MemIndexedMode &AM, 506 SelectionDAG &DAG) { 507 return false; 508 } 509 510 /// getPostIndexedAddressParts - returns true by value, base pointer and 511 /// offset pointer and addressing mode by reference if this node can be 512 /// combined with a load / store to form a post-indexed load / store. 513 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 514 SDOperand &Base, SDOperand &Offset, 515 ISD::MemIndexedMode &AM, 516 SelectionDAG &DAG) { 517 return false; 518 } 519 520 //===--------------------------------------------------------------------===// 521 // TargetLowering Optimization Methods 522 // 523 524 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 525 /// SDOperands for returning information from TargetLowering to its clients 526 /// that want to combine 527 struct TargetLoweringOpt { 528 SelectionDAG &DAG; 529 SDOperand Old; 530 SDOperand New; 531 532 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 533 534 bool CombineTo(SDOperand O, SDOperand N) { 535 Old = O; 536 New = N; 537 return true; 538 } 539 540 /// ShrinkDemandedConstant - Check to see if the specified operand of the 541 /// specified instruction is a constant integer. If so, check to see if there 542 /// are any bits set in the constant that are not demanded. If so, shrink the 543 /// constant and return true. 544 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 545 }; 546 547 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 548 /// DemandedMask bits of the result of Op are ever used downstream. If we can 549 /// use this information to simplify Op, create a new simplified DAG node and 550 /// return true, returning the original and new nodes in Old and New. 551 /// Otherwise, analyze the expression and return a mask of KnownOne and 552 /// KnownZero bits for the expression (used to simplify the caller). 553 /// The KnownZero/One bits may only be accurate for those bits in the 554 /// DemandedMask. 555 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 556 uint64_t &KnownZero, uint64_t &KnownOne, 557 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 558 559 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 560 /// Mask are known to be either zero or one and return them in the 561 /// KnownZero/KnownOne bitsets. 562 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 563 uint64_t Mask, 564 uint64_t &KnownZero, 565 uint64_t &KnownOne, 566 const SelectionDAG &DAG, 567 unsigned Depth = 0) const; 568 569 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 570 /// targets that want to expose additional information about sign bits to the 571 /// DAG Combiner. 572 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 573 unsigned Depth = 0) const; 574 575 struct DAGCombinerInfo { 576 void *DC; // The DAG Combiner object. 577 bool BeforeLegalize; 578 bool CalledByLegalizer; 579 public: 580 SelectionDAG &DAG; 581 582 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 583 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 584 585 bool isBeforeLegalize() const { return BeforeLegalize; } 586 bool isCalledByLegalizer() const { return CalledByLegalizer; } 587 588 void AddToWorklist(SDNode *N); 589 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 590 SDOperand CombineTo(SDNode *N, SDOperand Res); 591 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 592 }; 593 594 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 595 /// and cc. If it is unable to simplify it, return a null SDOperand. 596 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 597 ISD::CondCode Cond, bool foldBooleans, 598 DAGCombinerInfo &DCI) const; 599 600 /// PerformDAGCombine - This method will be invoked for all target nodes and 601 /// for any target-independent nodes that the target has registered with 602 /// invoke it for. 603 /// 604 /// The semantics are as follows: 605 /// Return Value: 606 /// SDOperand.Val == 0 - No change was made 607 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 608 /// otherwise - N should be replaced by the returned Operand. 609 /// 610 /// In addition, methods provided by DAGCombinerInfo may be used to perform 611 /// more complex transformations. 612 /// 613 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 614 615 //===--------------------------------------------------------------------===// 616 // TargetLowering Configuration Methods - These methods should be invoked by 617 // the derived class constructor to configure this object for the target. 618 // 619 620protected: 621 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 622 /// GOT for PC-relative code. 623 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 624 625 /// setShiftAmountType - Describe the type that should be used for shift 626 /// amounts. This type defaults to the pointer type. 627 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 628 629 /// setSetCCResultType - Describe the type that shoudl be used as the result 630 /// of a setcc operation. This defaults to the pointer type. 631 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 632 633 /// setSetCCResultContents - Specify how the target extends the result of a 634 /// setcc operation in a register. 635 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 636 637 /// setSchedulingPreference - Specify the target scheduling preference. 638 void setSchedulingPreference(SchedPreference Pref) { 639 SchedPreferenceInfo = Pref; 640 } 641 642 /// setShiftAmountFlavor - Describe how the target handles out of range shift 643 /// amounts. 644 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 645 ShiftAmtHandling = OORSA; 646 } 647 648 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 649 /// use _setjmp to implement llvm.setjmp or the non _ version. 650 /// Defaults to false. 651 void setUseUnderscoreSetJmp(bool Val) { 652 UseUnderscoreSetJmp = Val; 653 } 654 655 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 656 /// use _longjmp to implement llvm.longjmp or the non _ version. 657 /// Defaults to false. 658 void setUseUnderscoreLongJmp(bool Val) { 659 UseUnderscoreLongJmp = Val; 660 } 661 662 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 663 /// specifies the register that llvm.savestack/llvm.restorestack should save 664 /// and restore. 665 void setStackPointerRegisterToSaveRestore(unsigned R) { 666 StackPointerRegisterToSaveRestore = R; 667 } 668 669 /// setExceptionPointerRegister - If set to a physical register, this sets 670 /// the register that receives the exception address on entry to a landing 671 /// pad. 672 void setExceptionPointerRegister(unsigned R) { 673 ExceptionPointerRegister = R; 674 } 675 676 /// setExceptionSelectorRegister - If set to a physical register, this sets 677 /// the register that receives the exception typeid on entry to a landing 678 /// pad. 679 void setExceptionSelectorRegister(unsigned R) { 680 ExceptionSelectorRegister = R; 681 } 682 683 /// SelectIsExpensive - Tells the code generator not to expand operations 684 /// into sequences that use the select operations if possible. 685 void setSelectIsExpensive() { SelectIsExpensive = true; } 686 687 /// setIntDivIsCheap - Tells the code generator that integer divide is 688 /// expensive, and if possible, should be replaced by an alternate sequence 689 /// of instructions not containing an integer divide. 690 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 691 692 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 693 /// srl/add/sra for a signed divide by power of two, and let the target handle 694 /// it. 695 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 696 697 /// addRegisterClass - Add the specified register class as an available 698 /// regclass for the specified value type. This indicates the selector can 699 /// handle values of that class natively. 700 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 701 assert(!MVT::isExtendedVT(VT)); 702 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 703 RegClassForVT[VT] = RC; 704 } 705 706 /// computeRegisterProperties - Once all of the register classes are added, 707 /// this allows us to compute derived properties we expose. 708 void computeRegisterProperties(); 709 710 /// setOperationAction - Indicate that the specified operation does not work 711 /// with the specified type and indicate what to do about it. 712 void setOperationAction(unsigned Op, MVT::ValueType VT, 713 LegalizeAction Action) { 714 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 715 "Table isn't big enough!"); 716 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 717 OpActions[Op] |= (uint64_t)Action << VT*2; 718 } 719 720 /// setLoadXAction - Indicate that the specified load with extension does not 721 /// work with the with specified type and indicate what to do about it. 722 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 723 LegalizeAction Action) { 724 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) && 725 "Table isn't big enough!"); 726 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 727 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 728 } 729 730 /// setStoreXAction - Indicate that the specified store with truncation does 731 /// not work with the with specified type and indicate what to do about it. 732 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) { 733 assert(VT < 32 && "Table isn't big enough!"); 734 StoreXActions &= ~(uint64_t(3UL) << VT*2); 735 StoreXActions |= (uint64_t)Action << VT*2; 736 } 737 738 /// setIndexedLoadAction - Indicate that the specified indexed load does or 739 /// does not work with the with specified type and indicate what to do abort 740 /// it. NOTE: All indexed mode loads are initialized to Expand in 741 /// TargetLowering.cpp 742 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 743 LegalizeAction Action) { 744 assert(VT < 32 && IdxMode < 745 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) && 746 "Table isn't big enough!"); 747 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 748 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 749 } 750 751 /// setIndexedStoreAction - Indicate that the specified indexed store does or 752 /// does not work with the with specified type and indicate what to do about 753 /// it. NOTE: All indexed mode stores are initialized to Expand in 754 /// TargetLowering.cpp 755 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 756 LegalizeAction Action) { 757 assert(VT < 32 && IdxMode < 758 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) && 759 "Table isn't big enough!"); 760 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 761 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 762 } 763 764 /// setConvertAction - Indicate that the specified conversion does or does 765 /// not work with the with specified type and indicate what to do about it. 766 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT, 767 LegalizeAction Action) { 768 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 && 769 "Table isn't big enough!"); 770 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2); 771 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2; 772 } 773 774 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 775 /// promotion code defaults to trying a larger integer/fp until it can find 776 /// one that works. If that default is insufficient, this method can be used 777 /// by the target to override the default. 778 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 779 MVT::ValueType DestVT) { 780 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 781 } 782 783 /// addLegalFPImmediate - Indicate that this target can instruction select 784 /// the specified FP immediate natively. 785 void addLegalFPImmediate(const APFloat& Imm) { 786 // Incoming constants are expected to be double. We also add 787 // the float version. It is expected that all constants are exactly 788 // representable as floats. 789 assert(&Imm.getSemantics() == &APFloat::IEEEdouble); 790 APFloat Immf = APFloat(Imm); 791 // Rounding mode is not supposed to matter here... 792 if (Immf.convert(APFloat::IEEEsingle, APFloat::rmNearestTiesToEven) != 793 APFloat::opOK) 794 assert(0); 795 LegalFPImmediates.push_back(Imm); 796 LegalFPImmediates.push_back(Immf); 797 } 798 799 /// setTargetDAGCombine - Targets should invoke this method for each target 800 /// independent node that they want to provide a custom DAG combiner for by 801 /// implementing the PerformDAGCombine virtual method. 802 void setTargetDAGCombine(ISD::NodeType NT) { 803 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 804 } 805 806 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 807 /// bytes); default is 200 808 void setJumpBufSize(unsigned Size) { 809 JumpBufSize = Size; 810 } 811 812 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 813 /// alignment (in bytes); default is 0 814 void setJumpBufAlignment(unsigned Align) { 815 JumpBufAlignment = Align; 816 } 817 818 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 819 /// limit (in number of instructions); default is 2. 820 void setIfCvtBlockSizeLimit(unsigned Limit) { 821 IfCvtBlockSizeLimit = Limit; 822 } 823 824 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 825 /// of instructions) to be considered for code duplication during 826 /// if-conversion; default is 2. 827 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 828 IfCvtDupBlockSizeLimit = Limit; 829 } 830 831public: 832 833 //===--------------------------------------------------------------------===// 834 // Lowering methods - These methods must be implemented by targets so that 835 // the SelectionDAGLowering code knows how to lower these. 836 // 837 838 /// LowerArguments - This hook must be implemented to indicate how we should 839 /// lower the arguments for the specified function, into the specified DAG. 840 virtual std::vector<SDOperand> 841 LowerArguments(Function &F, SelectionDAG &DAG); 842 843 /// LowerCallTo - This hook lowers an abstract call to a function into an 844 /// actual call. This returns a pair of operands. The first element is the 845 /// return value for the function (if RetTy is not VoidTy). The second 846 /// element is the outgoing token chain. 847 struct ArgListEntry { 848 SDOperand Node; 849 const Type* Ty; 850 bool isSExt; 851 bool isZExt; 852 bool isInReg; 853 bool isSRet; 854 bool isNest; 855 bool isByVal; 856 857 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 858 isSRet(false), isNest(false), isByVal(false) { } 859 }; 860 typedef std::vector<ArgListEntry> ArgListTy; 861 virtual std::pair<SDOperand, SDOperand> 862 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 863 bool isVarArg, unsigned CallingConv, bool isTailCall, 864 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 865 866 /// LowerOperation - This callback is invoked for operations that are 867 /// unsupported by the target, which are registered to use 'custom' lowering, 868 /// and whose defined values are all legal. 869 /// If the target has no operations that require custom lowering, it need not 870 /// implement this. The default implementation of this aborts. 871 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 872 873 /// CustomPromoteOperation - This callback is invoked for operations that are 874 /// unsupported by the target, are registered to use 'custom' lowering, and 875 /// whose type needs to be promoted. 876 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 877 878 /// getTargetNodeName() - This method returns the name of a target specific 879 /// DAG node. 880 virtual const char *getTargetNodeName(unsigned Opcode) const; 881 882 //===--------------------------------------------------------------------===// 883 // Inline Asm Support hooks 884 // 885 886 enum ConstraintType { 887 C_Register, // Constraint represents a single register. 888 C_RegisterClass, // Constraint represents one or more registers. 889 C_Memory, // Memory constraint. 890 C_Other, // Something else. 891 C_Unknown // Unsupported constraint. 892 }; 893 894 /// getConstraintType - Given a constraint, return the type of constraint it 895 /// is for this target. 896 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 897 898 899 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 900 /// return a list of registers that can be used to satisfy the constraint. 901 /// This should only be used for C_RegisterClass constraints. 902 virtual std::vector<unsigned> 903 getRegClassForInlineAsmConstraint(const std::string &Constraint, 904 MVT::ValueType VT) const; 905 906 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 907 /// {edx}), return the register number and the register class for the 908 /// register. 909 /// 910 /// Given a register class constraint, like 'r', if this corresponds directly 911 /// to an LLVM register class, return a register of 0 and the register class 912 /// pointer. 913 /// 914 /// This should only be used for C_Register constraints. On error, 915 /// this returns a register number of 0 and a null register class pointer.. 916 virtual std::pair<unsigned, const TargetRegisterClass*> 917 getRegForInlineAsmConstraint(const std::string &Constraint, 918 MVT::ValueType VT) const; 919 920 921 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 922 /// vector. If it is invalid, don't add anything to Ops. 923 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter, 924 std::vector<SDOperand> &Ops, 925 SelectionDAG &DAG); 926 927 //===--------------------------------------------------------------------===// 928 // Scheduler hooks 929 // 930 931 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 932 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 933 // instructions are special in various ways, which require special support to 934 // insert. The specified MachineInstr is created but not inserted into any 935 // basic blocks, and the scheduler passes ownership of it to this method. 936 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 937 MachineBasicBlock *MBB); 938 939 //===--------------------------------------------------------------------===// 940 // Addressing mode description hooks (used by LSR etc). 941 // 942 943 /// AddrMode - This represents an addressing mode of: 944 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 945 /// If BaseGV is null, there is no BaseGV. 946 /// If BaseOffs is zero, there is no base offset. 947 /// If HasBaseReg is false, there is no base register. 948 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 949 /// no scale. 950 /// 951 struct AddrMode { 952 GlobalValue *BaseGV; 953 int64_t BaseOffs; 954 bool HasBaseReg; 955 int64_t Scale; 956 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 957 }; 958 959 /// isLegalAddressingMode - Return true if the addressing mode represented by 960 /// AM is legal for this target, for a load/store of the specified type. 961 /// TODO: Handle pre/postinc as well. 962 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 963 964 //===--------------------------------------------------------------------===// 965 // Div utility functions 966 // 967 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 968 std::vector<SDNode*>* Created) const; 969 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 970 std::vector<SDNode*>* Created) const; 971 972 973 //===--------------------------------------------------------------------===// 974 // Runtime Library hooks 975 // 976 977 /// setLibcallName - Rename the default libcall routine name for the specified 978 /// libcall. 979 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 980 LibcallRoutineNames[Call] = Name; 981 } 982 983 /// getLibcallName - Get the libcall routine name for the specified libcall. 984 /// 985 const char *getLibcallName(RTLIB::Libcall Call) const { 986 return LibcallRoutineNames[Call]; 987 } 988 989 /// setCmpLibcallCC - Override the default CondCode to be used to test the 990 /// result of the comparison libcall against zero. 991 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 992 CmpLibcallCCs[Call] = CC; 993 } 994 995 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 996 /// the comparison libcall against zero. 997 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 998 return CmpLibcallCCs[Call]; 999 } 1000 1001private: 1002 TargetMachine &TM; 1003 const TargetData *TD; 1004 1005 /// IsLittleEndian - True if this is a little endian target. 1006 /// 1007 bool IsLittleEndian; 1008 1009 /// PointerTy - The type to use for pointers, usually i32 or i64. 1010 /// 1011 MVT::ValueType PointerTy; 1012 1013 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1014 /// 1015 bool UsesGlobalOffsetTable; 1016 1017 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1018 /// PointerTy is. 1019 MVT::ValueType ShiftAmountTy; 1020 1021 OutOfRangeShiftAmount ShiftAmtHandling; 1022 1023 /// SelectIsExpensive - Tells the code generator not to expand operations 1024 /// into sequences that use the select operations if possible. 1025 bool SelectIsExpensive; 1026 1027 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1028 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1029 /// a real cost model is in place. If we ever optimize for size, this will be 1030 /// set to true unconditionally. 1031 bool IntDivIsCheap; 1032 1033 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1034 /// srl/add/sra for a signed divide by power of two, and let the target handle 1035 /// it. 1036 bool Pow2DivIsCheap; 1037 1038 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 1039 /// PointerTy. 1040 MVT::ValueType SetCCResultTy; 1041 1042 /// SetCCResultContents - Information about the contents of the high-bits in 1043 /// the result of a setcc comparison operation. 1044 SetCCResultValue SetCCResultContents; 1045 1046 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1047 /// total cycles or lowest register usage. 1048 SchedPreference SchedPreferenceInfo; 1049 1050 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1051 /// llvm.setjmp. Defaults to false. 1052 bool UseUnderscoreSetJmp; 1053 1054 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1055 /// llvm.longjmp. Defaults to false. 1056 bool UseUnderscoreLongJmp; 1057 1058 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1059 unsigned JumpBufSize; 1060 1061 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1062 /// buffers 1063 unsigned JumpBufAlignment; 1064 1065 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1066 /// if-converted. 1067 unsigned IfCvtBlockSizeLimit; 1068 1069 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1070 /// duplicated during if-conversion. 1071 unsigned IfCvtDupBlockSizeLimit; 1072 1073 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1074 /// specifies the register that llvm.savestack/llvm.restorestack should save 1075 /// and restore. 1076 unsigned StackPointerRegisterToSaveRestore; 1077 1078 /// ExceptionPointerRegister - If set to a physical register, this specifies 1079 /// the register that receives the exception address on entry to a landing 1080 /// pad. 1081 unsigned ExceptionPointerRegister; 1082 1083 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1084 /// the register that receives the exception typeid on entry to a landing 1085 /// pad. 1086 unsigned ExceptionSelectorRegister; 1087 1088 /// RegClassForVT - This indicates the default register class to use for 1089 /// each ValueType the target supports natively. 1090 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1091 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1092 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1093 1094 /// TransformToType - For any value types we are promoting or expanding, this 1095 /// contains the value type that we are changing to. For Expanded types, this 1096 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1097 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1098 /// by the system, this holds the same type (e.g. i32 -> i32). 1099 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1100 1101 /// OpActions - For each operation and each value type, keep a LegalizeAction 1102 /// that indicates how instruction selection should deal with the operation. 1103 /// Most operations are Legal (aka, supported natively by the target), but 1104 /// operations that are not should be described. Note that operations on 1105 /// non-legal value types are not described here. 1106 uint64_t OpActions[156]; 1107 1108 /// LoadXActions - For each load of load extension type and each value type, 1109 /// keep a LegalizeAction that indicates how instruction selection should deal 1110 /// with the load. 1111 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1112 1113 /// StoreXActions - For each store with truncation of each value type, keep a 1114 /// LegalizeAction that indicates how instruction selection should deal with 1115 /// the store. 1116 uint64_t StoreXActions; 1117 1118 /// IndexedModeActions - For each indexed mode and each value type, keep a 1119 /// pair of LegalizeAction that indicates how instruction selection should 1120 /// deal with the load / store. 1121 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1122 1123 /// ConvertActions - For each conversion from source type to destination type, 1124 /// keep a LegalizeAction that indicates how instruction selection should 1125 /// deal with the conversion. 1126 /// Currently, this is used only for floating->floating conversions 1127 /// (FP_EXTEND and FP_ROUND). 1128 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1129 1130 ValueTypeActionImpl ValueTypeActions; 1131 1132 std::vector<APFloat> LegalFPImmediates; 1133 1134 std::vector<std::pair<MVT::ValueType, 1135 TargetRegisterClass*> > AvailableRegClasses; 1136 1137 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1138 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1139 /// which sets a bit in this array. 1140 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1141 1142 /// PromoteToType - For operations that must be promoted to a specific type, 1143 /// this holds the destination type. This map should be sparse, so don't hold 1144 /// it as an array. 1145 /// 1146 /// Targets add entries to this map with AddPromotedToType(..), clients access 1147 /// this with getTypeToPromoteTo(..). 1148 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1149 1150 /// LibcallRoutineNames - Stores the name each libcall. 1151 /// 1152 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1153 1154 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1155 /// of each of the comparison libcall against zero. 1156 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1157 1158protected: 1159 /// When lowering %llvm.memset this field specifies the maximum number of 1160 /// store operations that may be substituted for the call to memset. Targets 1161 /// must set this value based on the cost threshold for that target. Targets 1162 /// should assume that the memset will be done using as many of the largest 1163 /// store operations first, followed by smaller ones, if necessary, per 1164 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1165 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1166 /// store. This only applies to setting a constant array of a constant size. 1167 /// @brief Specify maximum number of store instructions per memset call. 1168 unsigned maxStoresPerMemset; 1169 1170 /// When lowering %llvm.memcpy this field specifies the maximum number of 1171 /// store operations that may be substituted for a call to memcpy. Targets 1172 /// must set this value based on the cost threshold for that target. Targets 1173 /// should assume that the memcpy will be done using as many of the largest 1174 /// store operations first, followed by smaller ones, if necessary, per 1175 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1176 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1177 /// and one 1-byte store. This only applies to copying a constant array of 1178 /// constant size. 1179 /// @brief Specify maximum bytes of store instructions per memcpy call. 1180 unsigned maxStoresPerMemcpy; 1181 1182 /// When lowering %llvm.memmove this field specifies the maximum number of 1183 /// store instructions that may be substituted for a call to memmove. Targets 1184 /// must set this value based on the cost threshold for that target. Targets 1185 /// should assume that the memmove will be done using as many of the largest 1186 /// store operations first, followed by smaller ones, if necessary, per 1187 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1188 /// with 8-bit alignment would result in nine 1-byte stores. This only 1189 /// applies to copying a constant array of constant size. 1190 /// @brief Specify maximum bytes of store instructions per memmove call. 1191 unsigned maxStoresPerMemmove; 1192 1193 /// This field specifies whether the target machine permits unaligned memory 1194 /// accesses. This is used, for example, to determine the size of store 1195 /// operations when copying small arrays and other similar tasks. 1196 /// @brief Indicate whether the target permits unaligned memory accesses. 1197 bool allowUnalignedMemoryAccesses; 1198}; 1199} // end llvm namespace 1200 1201#endif 1202