TargetLowering.h revision f0757b0edc1ef3d1998485d3f74cadaa3f7180a0
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/CodeGen/SelectionDAGNodes.h" 28#include "llvm/CodeGen/RuntimeLibcalls.h" 29#include "llvm/ADT/APFloat.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallSet.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/STLExtras.h" 34#include "llvm/Support/DebugLoc.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class AllocaInst; 42 class CallInst; 43 class Function; 44 class FastISel; 45 class MachineBasicBlock; 46 class MachineFunction; 47 class MachineFrameInfo; 48 class MachineInstr; 49 class MachineJumpTableInfo; 50 class MCContext; 51 class MCExpr; 52 class SDNode; 53 class SDValue; 54 class SelectionDAG; 55 class TargetData; 56 class TargetMachine; 57 class TargetRegisterClass; 58 class TargetSubtarget; 59 class TargetLoweringObjectFile; 60 class Value; 61 62 // FIXME: should this be here? 63 namespace TLSModel { 64 enum Model { 65 GeneralDynamic, 66 LocalDynamic, 67 InitialExec, 68 LocalExec 69 }; 70 } 71 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 72 73 74//===----------------------------------------------------------------------===// 75/// TargetLowering - This class defines information used to lower LLVM code to 76/// legal SelectionDAG operators that the target instruction selector can accept 77/// natively. 78/// 79/// This class also defines callbacks that targets must implement to lower 80/// target-specific constructs to SelectionDAG operators. 81/// 82class TargetLowering { 83 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 84 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 85public: 86 /// LegalizeAction - This enum indicates whether operations are valid for a 87 /// target, and if not, what action should be used to make them valid. 88 enum LegalizeAction { 89 Legal, // The target natively supports this operation. 90 Promote, // This operation should be executed in a larger type. 91 Expand, // Try to expand this to other ops, otherwise use a libcall. 92 Custom // Use the LowerOperation hook to implement custom lowering. 93 }; 94 95 enum BooleanContent { // How the target represents true/false values. 96 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 97 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 98 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 99 }; 100 101 enum SchedPreference { 102 SchedulingForLatency, // Scheduling for shortest total latency. 103 SchedulingForRegPressure // Scheduling for lowest register pressure. 104 }; 105 106 /// NOTE: The constructor takes ownership of TLOF. 107 explicit TargetLowering(const TargetMachine &TM, 108 const TargetLoweringObjectFile *TLOF); 109 virtual ~TargetLowering(); 110 111 const TargetMachine &getTargetMachine() const { return TM; } 112 const TargetData *getTargetData() const { return TD; } 113 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 114 115 bool isBigEndian() const { return !IsLittleEndian; } 116 bool isLittleEndian() const { return IsLittleEndian; } 117 MVT getPointerTy() const { return PointerTy; } 118 MVT getShiftAmountTy() const { return ShiftAmountTy; } 119 120 /// isSelectExpensive - Return true if the select operation is expensive for 121 /// this target. 122 bool isSelectExpensive() const { return SelectIsExpensive; } 123 124 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 125 /// a sequence of several shifts, adds, and multiplies for this target. 126 bool isIntDivCheap() const { return IntDivIsCheap; } 127 128 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 129 /// srl/add/sra. 130 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 131 132 /// getSetCCResultType - Return the ValueType of the result of SETCC 133 /// operations. Also used to obtain the target's preferred type for 134 /// the condition operand of SELECT and BRCOND nodes. In the case of 135 /// BRCOND the argument passed is MVT::Other since there are no other 136 /// operands to get a type hint from. 137 virtual 138 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 139 140 /// getCmpLibcallReturnType - Return the ValueType for comparison 141 /// libcalls. Comparions libcalls include floating point comparion calls, 142 /// and Ordered/Unordered check calls on floating point numbers. 143 virtual 144 MVT::SimpleValueType getCmpLibcallReturnType() const; 145 146 /// getBooleanContents - For targets without i1 registers, this gives the 147 /// nature of the high-bits of boolean values held in types wider than i1. 148 /// "Boolean values" are special true/false values produced by nodes like 149 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 150 /// Not to be confused with general values promoted from i1. 151 BooleanContent getBooleanContents() const { return BooleanContents;} 152 153 /// getSchedulingPreference - Return target scheduling preference. 154 SchedPreference getSchedulingPreference() const { 155 return SchedPreferenceInfo; 156 } 157 158 /// getRegClassFor - Return the register class that should be used for the 159 /// specified value type. This may only be called on legal types. 160 TargetRegisterClass *getRegClassFor(EVT VT) const { 161 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 162 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 163 assert(RC && "This value type is not natively supported!"); 164 return RC; 165 } 166 167 /// isTypeLegal - Return true if the target has native support for the 168 /// specified value type. This means that it has a register that directly 169 /// holds it without promotions or expansions. 170 bool isTypeLegal(EVT VT) const { 171 assert(!VT.isSimple() || 172 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 173 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 174 } 175 176 /// isTypeSynthesizable - Return true if it's OK for the compiler to create 177 /// new operations of this type. All Legal types are synthesizable except 178 /// MMX vector types on X86. Non-Legal types are not synthesizable. 179 bool isTypeSynthesizable(EVT VT) const { 180 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy]; 181 } 182 183 class ValueTypeActionImpl { 184 /// ValueTypeActions - This is a bitvector that contains two bits for each 185 /// value type, where the two bits correspond to the LegalizeAction enum. 186 /// This can be queried with "getTypeAction(VT)". 187 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2 188 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2]; 189 public: 190 ValueTypeActionImpl() { 191 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 192 } 193 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 194 if (VT.isExtended()) { 195 if (VT.isVector()) { 196 return VT.isPow2VectorType() ? Expand : Promote; 197 } 198 if (VT.isInteger()) 199 // First promote to a power-of-two size, then expand if necessary. 200 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote; 201 assert(0 && "Unsupported extended type!"); 202 return Legal; 203 } 204 unsigned I = VT.getSimpleVT().SimpleTy; 205 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 206 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 207 } 208 void setTypeAction(EVT VT, LegalizeAction Action) { 209 unsigned I = VT.getSimpleVT().SimpleTy; 210 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 211 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 212 } 213 }; 214 215 const ValueTypeActionImpl &getValueTypeActions() const { 216 return ValueTypeActions; 217 } 218 219 /// getTypeAction - Return how we should legalize values of this type, either 220 /// it is already legal (return 'Legal') or we need to promote it to a larger 221 /// type (return 'Promote'), or we need to expand it into multiple registers 222 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 223 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 224 return ValueTypeActions.getTypeAction(Context, VT); 225 } 226 227 /// getTypeToTransformTo - For types supported by the target, this is an 228 /// identity function. For types that must be promoted to larger types, this 229 /// returns the larger type to promote to. For integer types that are larger 230 /// than the largest integer register, this contains one step in the expansion 231 /// to get to the smaller register. For illegal floating point types, this 232 /// returns the integer type to transform to. 233 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 234 if (VT.isSimple()) { 235 assert((unsigned)VT.getSimpleVT().SimpleTy < 236 array_lengthof(TransformToType)); 237 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 238 assert(getTypeAction(Context, NVT) != Promote && 239 "Promote may not follow Expand or Promote"); 240 return NVT; 241 } 242 243 if (VT.isVector()) { 244 EVT NVT = VT.getPow2VectorType(Context); 245 if (NVT == VT) { 246 // Vector length is a power of 2 - split to half the size. 247 unsigned NumElts = VT.getVectorNumElements(); 248 EVT EltVT = VT.getVectorElementType(); 249 return (NumElts == 1) ? 250 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 251 } 252 // Promote to a power of two size, avoiding multi-step promotion. 253 return getTypeAction(Context, NVT) == Promote ? 254 getTypeToTransformTo(Context, NVT) : NVT; 255 } else if (VT.isInteger()) { 256 EVT NVT = VT.getRoundIntegerType(Context); 257 if (NVT == VT) 258 // Size is a power of two - expand to half the size. 259 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 260 else 261 // Promote to a power of two size, avoiding multi-step promotion. 262 return getTypeAction(Context, NVT) == Promote ? 263 getTypeToTransformTo(Context, NVT) : NVT; 264 } 265 assert(0 && "Unsupported extended type!"); 266 return MVT(MVT::Other); // Not reached 267 } 268 269 /// getTypeToExpandTo - For types supported by the target, this is an 270 /// identity function. For types that must be expanded (i.e. integer types 271 /// that are larger than the largest integer register or illegal floating 272 /// point types), this returns the largest legal type it will be expanded to. 273 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 274 assert(!VT.isVector()); 275 while (true) { 276 switch (getTypeAction(Context, VT)) { 277 case Legal: 278 return VT; 279 case Expand: 280 VT = getTypeToTransformTo(Context, VT); 281 break; 282 default: 283 assert(false && "Type is not legal nor is it to be expanded!"); 284 return VT; 285 } 286 } 287 return VT; 288 } 289 290 /// getVectorTypeBreakdown - Vector types are broken down into some number of 291 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 292 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 293 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 294 /// 295 /// This method returns the number of registers needed, and the VT for each 296 /// register. It also returns the VT and quantity of the intermediate values 297 /// before they are promoted/expanded. 298 /// 299 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 300 EVT &IntermediateVT, 301 unsigned &NumIntermediates, 302 EVT &RegisterVT) const; 303 304 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 305 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 306 /// this is the case, it returns true and store the intrinsic 307 /// information into the IntrinsicInfo that was passed to the function. 308 struct IntrinsicInfo { 309 unsigned opc; // target opcode 310 EVT memVT; // memory VT 311 const Value* ptrVal; // value representing memory location 312 int offset; // offset off of ptrVal 313 unsigned align; // alignment 314 bool vol; // is volatile? 315 bool readMem; // reads memory? 316 bool writeMem; // writes memory? 317 }; 318 319 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 320 const CallInst &I, unsigned Intrinsic) const { 321 return false; 322 } 323 324 /// isFPImmLegal - Returns true if the target can instruction select the 325 /// specified FP immediate natively. If false, the legalizer will materialize 326 /// the FP immediate as a load from a constant pool. 327 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 328 return false; 329 } 330 331 /// isShuffleMaskLegal - Targets can use this to indicate that they only 332 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 333 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 334 /// are assumed to be legal. 335 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 336 EVT VT) const { 337 return true; 338 } 339 340 /// canOpTrap - Returns true if the operation can trap for the value type. 341 /// VT must be a legal type. By default, we optimistically assume most 342 /// operations don't trap except for divide and remainder. 343 virtual bool canOpTrap(unsigned Op, EVT VT) const; 344 345 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 346 /// used by Targets can use this to indicate if there is a suitable 347 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 348 /// pool entry. 349 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 350 EVT VT) const { 351 return false; 352 } 353 354 /// getOperationAction - Return how this operation should be treated: either 355 /// it is legal, needs to be promoted to a larger size, needs to be 356 /// expanded to some other code sequence, or the target has a custom expander 357 /// for it. 358 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 359 if (VT.isExtended()) return Expand; 360 assert(Op < array_lengthof(OpActions[0]) && 361 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 && 362 "Table isn't big enough!"); 363 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 364 unsigned J = I & 31; 365 I = I >> 5; 366 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3); 367 } 368 369 /// isOperationLegalOrCustom - Return true if the specified operation is 370 /// legal on this target or can be made legal with custom lowering. This 371 /// is used to help guide high-level lowering decisions. 372 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 373 return (VT == MVT::Other || isTypeLegal(VT)) && 374 (getOperationAction(Op, VT) == Legal || 375 getOperationAction(Op, VT) == Custom); 376 } 377 378 /// isOperationLegal - Return true if the specified operation is legal on this 379 /// target. 380 bool isOperationLegal(unsigned Op, EVT VT) const { 381 return (VT == MVT::Other || isTypeLegal(VT)) && 382 getOperationAction(Op, VT) == Legal; 383 } 384 385 /// getLoadExtAction - Return how this load with extension should be treated: 386 /// either it is legal, needs to be promoted to a larger size, needs to be 387 /// expanded to some other code sequence, or the target has a custom expander 388 /// for it. 389 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const { 390 assert(LType < array_lengthof(LoadExtActions) && 391 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 && 392 "Table isn't big enough!"); 393 return (LegalizeAction)((LoadExtActions[LType] >> 394 (2*VT.getSimpleVT().SimpleTy)) & 3); 395 } 396 397 /// isLoadExtLegal - Return true if the specified load with extension is legal 398 /// on this target. 399 bool isLoadExtLegal(unsigned LType, EVT VT) const { 400 return VT.isSimple() && 401 (getLoadExtAction(LType, VT) == Legal || 402 getLoadExtAction(LType, VT) == Custom); 403 } 404 405 /// getTruncStoreAction - Return how this store with truncation should be 406 /// treated: either it is legal, needs to be promoted to a larger size, needs 407 /// to be expanded to some other code sequence, or the target has a custom 408 /// expander for it. 409 LegalizeAction getTruncStoreAction(EVT ValVT, 410 EVT MemVT) const { 411 assert((unsigned)ValVT.getSimpleVT().SimpleTy < 412 array_lengthof(TruncStoreActions) && 413 (unsigned)MemVT.getSimpleVT().SimpleTy < 414 sizeof(TruncStoreActions[0])*4 && 415 "Table isn't big enough!"); 416 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >> 417 (2*MemVT.getSimpleVT().SimpleTy)) & 3); 418 } 419 420 /// isTruncStoreLegal - Return true if the specified store with truncation is 421 /// legal on this target. 422 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 423 return isTypeLegal(ValVT) && MemVT.isSimple() && 424 (getTruncStoreAction(ValVT, MemVT) == Legal || 425 getTruncStoreAction(ValVT, MemVT) == Custom); 426 } 427 428 /// getIndexedLoadAction - Return how the indexed load should be treated: 429 /// either it is legal, needs to be promoted to a larger size, needs to be 430 /// expanded to some other code sequence, or the target has a custom expander 431 /// for it. 432 LegalizeAction 433 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 434 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) && 435 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 436 "Table isn't big enough!"); 437 return (LegalizeAction)((IndexedModeActions[ 438 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode])); 439 } 440 441 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 442 /// on this target. 443 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 444 return VT.isSimple() && 445 (getIndexedLoadAction(IdxMode, VT) == Legal || 446 getIndexedLoadAction(IdxMode, VT) == Custom); 447 } 448 449 /// getIndexedStoreAction - Return how the indexed store should be treated: 450 /// either it is legal, needs to be promoted to a larger size, needs to be 451 /// expanded to some other code sequence, or the target has a custom expander 452 /// for it. 453 LegalizeAction 454 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 455 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) && 456 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 457 "Table isn't big enough!"); 458 return (LegalizeAction)((IndexedModeActions[ 459 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode])); 460 } 461 462 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 463 /// on this target. 464 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 465 return VT.isSimple() && 466 (getIndexedStoreAction(IdxMode, VT) == Legal || 467 getIndexedStoreAction(IdxMode, VT) == Custom); 468 } 469 470 /// getCondCodeAction - Return how the condition code should be treated: 471 /// either it is legal, needs to be expanded to some other code sequence, 472 /// or the target has a custom expander for it. 473 LegalizeAction 474 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 475 assert((unsigned)CC < array_lengthof(CondCodeActions) && 476 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 477 "Table isn't big enough!"); 478 LegalizeAction Action = (LegalizeAction) 479 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 480 assert(Action != Promote && "Can't promote condition code!"); 481 return Action; 482 } 483 484 /// isCondCodeLegal - Return true if the specified condition code is legal 485 /// on this target. 486 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 487 return getCondCodeAction(CC, VT) == Legal || 488 getCondCodeAction(CC, VT) == Custom; 489 } 490 491 492 /// getTypeToPromoteTo - If the action for this operation is to promote, this 493 /// method returns the ValueType to promote to. 494 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 495 assert(getOperationAction(Op, VT) == Promote && 496 "This operation isn't promoted!"); 497 498 // See if this has an explicit type specified. 499 std::map<std::pair<unsigned, MVT::SimpleValueType>, 500 MVT::SimpleValueType>::const_iterator PTTI = 501 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 502 if (PTTI != PromoteToType.end()) return PTTI->second; 503 504 assert((VT.isInteger() || VT.isFloatingPoint()) && 505 "Cannot autopromote this type, add it with AddPromotedToType."); 506 507 EVT NVT = VT; 508 do { 509 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 510 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 511 "Didn't find type to promote to!"); 512 } while (!isTypeLegal(NVT) || 513 getOperationAction(Op, NVT) == Promote); 514 return NVT; 515 } 516 517 /// getValueType - Return the EVT corresponding to this LLVM type. 518 /// This is fixed by the LLVM operations except for the pointer size. If 519 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 520 /// counterpart (e.g. structs), otherwise it will assert. 521 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 522 EVT VT = EVT::getEVT(Ty, AllowUnknown); 523 return VT == MVT::iPTR ? PointerTy : VT; 524 } 525 526 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 527 /// function arguments in the caller parameter area. This is the actual 528 /// alignment, not its logarithm. 529 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 530 531 /// getRegisterType - Return the type of registers that this ValueType will 532 /// eventually require. 533 EVT getRegisterType(MVT VT) const { 534 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 535 return RegisterTypeForVT[VT.SimpleTy]; 536 } 537 538 /// getRegisterType - Return the type of registers that this ValueType will 539 /// eventually require. 540 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 541 if (VT.isSimple()) { 542 assert((unsigned)VT.getSimpleVT().SimpleTy < 543 array_lengthof(RegisterTypeForVT)); 544 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 545 } 546 if (VT.isVector()) { 547 EVT VT1, RegisterVT; 548 unsigned NumIntermediates; 549 (void)getVectorTypeBreakdown(Context, VT, VT1, 550 NumIntermediates, RegisterVT); 551 return RegisterVT; 552 } 553 if (VT.isInteger()) { 554 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 555 } 556 assert(0 && "Unsupported extended type!"); 557 return EVT(MVT::Other); // Not reached 558 } 559 560 /// getNumRegisters - Return the number of registers that this ValueType will 561 /// eventually require. This is one for any types promoted to live in larger 562 /// registers, but may be more than one for types (like i64) that are split 563 /// into pieces. For types like i140, which are first promoted then expanded, 564 /// it is the number of registers needed to hold all the bits of the original 565 /// type. For an i140 on a 32 bit machine this means 5 registers. 566 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 567 if (VT.isSimple()) { 568 assert((unsigned)VT.getSimpleVT().SimpleTy < 569 array_lengthof(NumRegistersForVT)); 570 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 571 } 572 if (VT.isVector()) { 573 EVT VT1, VT2; 574 unsigned NumIntermediates; 575 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 576 } 577 if (VT.isInteger()) { 578 unsigned BitWidth = VT.getSizeInBits(); 579 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 580 return (BitWidth + RegWidth - 1) / RegWidth; 581 } 582 assert(0 && "Unsupported extended type!"); 583 return 0; // Not reached 584 } 585 586 /// ShouldShrinkFPConstant - If true, then instruction selection should 587 /// seek to shrink the FP constant of the specified type to a smaller type 588 /// in order to save space and / or reduce runtime. 589 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 590 591 /// hasTargetDAGCombine - If true, the target has custom DAG combine 592 /// transformations that it can perform for the specified node. 593 bool hasTargetDAGCombine(ISD::NodeType NT) const { 594 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 595 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 596 } 597 598 /// This function returns the maximum number of store operations permitted 599 /// to replace a call to llvm.memset. The value is set by the target at the 600 /// performance threshold for such a replacement. 601 /// @brief Get maximum # of store operations permitted for llvm.memset 602 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 603 604 /// This function returns the maximum number of store operations permitted 605 /// to replace a call to llvm.memcpy. The value is set by the target at the 606 /// performance threshold for such a replacement. 607 /// @brief Get maximum # of store operations permitted for llvm.memcpy 608 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 609 610 /// This function returns the maximum number of store operations permitted 611 /// to replace a call to llvm.memmove. The value is set by the target at the 612 /// performance threshold for such a replacement. 613 /// @brief Get maximum # of store operations permitted for llvm.memmove 614 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 615 616 /// This function returns true if the target allows unaligned memory accesses. 617 /// of the specified type. This is used, for example, in situations where an 618 /// array copy/move/set is converted to a sequence of store operations. It's 619 /// use helps to ensure that such replacements don't generate code that causes 620 /// an alignment error (trap) on the target machine. 621 /// @brief Determine if the target supports unaligned memory accesses. 622 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 623 return false; 624 } 625 626 /// This function returns true if the target would benefit from code placement 627 /// optimization. 628 /// @brief Determine if the target should perform code placement optimization. 629 bool shouldOptimizeCodePlacement() const { 630 return benefitFromCodePlacementOpt; 631 } 632 633 /// getOptimalMemOpType - Returns the target specific optimal type for load 634 /// and store operations as a result of memset, memcpy, and memmove 635 /// lowering. If DstAlign is zero that means it's safe to destination 636 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 637 /// means there isn't a need to check it against alignment requirement, 638 /// probably because the source does not need to be loaded. If 639 /// 'NonScalarIntSafe' is true, that means it's safe to return a 640 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 641 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 642 /// constant so it does not need to be loaded. 643 /// It returns EVT::Other if the type should be determined using generic 644 /// target-independent logic. 645 virtual EVT getOptimalMemOpType(uint64_t Size, 646 unsigned DstAlign, unsigned SrcAlign, 647 bool NonScalarIntSafe, bool MemcpyStrSrc, 648 MachineFunction &MF) const { 649 return MVT::Other; 650 } 651 652 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 653 /// to implement llvm.setjmp. 654 bool usesUnderscoreSetJmp() const { 655 return UseUnderscoreSetJmp; 656 } 657 658 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 659 /// to implement llvm.longjmp. 660 bool usesUnderscoreLongJmp() const { 661 return UseUnderscoreLongJmp; 662 } 663 664 /// getStackPointerRegisterToSaveRestore - If a physical register, this 665 /// specifies the register that llvm.savestack/llvm.restorestack should save 666 /// and restore. 667 unsigned getStackPointerRegisterToSaveRestore() const { 668 return StackPointerRegisterToSaveRestore; 669 } 670 671 /// getExceptionAddressRegister - If a physical register, this returns 672 /// the register that receives the exception address on entry to a landing 673 /// pad. 674 unsigned getExceptionAddressRegister() const { 675 return ExceptionPointerRegister; 676 } 677 678 /// getExceptionSelectorRegister - If a physical register, this returns 679 /// the register that receives the exception typeid on entry to a landing 680 /// pad. 681 unsigned getExceptionSelectorRegister() const { 682 return ExceptionSelectorRegister; 683 } 684 685 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 686 /// set, the default is 200) 687 unsigned getJumpBufSize() const { 688 return JumpBufSize; 689 } 690 691 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 692 /// (if never set, the default is 0) 693 unsigned getJumpBufAlignment() const { 694 return JumpBufAlignment; 695 } 696 697 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 698 /// limit. Any block whose size is greater should not be predicated. 699 unsigned getIfCvtBlockSizeLimit() const { 700 return IfCvtBlockSizeLimit; 701 } 702 703 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 704 /// block to be considered for duplication. Any block whose size is greater 705 /// should not be duplicated to facilitate its predication. 706 unsigned getIfCvtDupBlockSizeLimit() const { 707 return IfCvtDupBlockSizeLimit; 708 } 709 710 /// getPrefLoopAlignment - return the preferred loop alignment. 711 /// 712 unsigned getPrefLoopAlignment() const { 713 return PrefLoopAlignment; 714 } 715 716 /// getPreIndexedAddressParts - returns true by value, base pointer and 717 /// offset pointer and addressing mode by reference if the node's address 718 /// can be legally represented as pre-indexed load / store address. 719 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 720 SDValue &Offset, 721 ISD::MemIndexedMode &AM, 722 SelectionDAG &DAG) const { 723 return false; 724 } 725 726 /// getPostIndexedAddressParts - returns true by value, base pointer and 727 /// offset pointer and addressing mode by reference if this node can be 728 /// combined with a load / store to form a post-indexed load / store. 729 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 730 SDValue &Base, SDValue &Offset, 731 ISD::MemIndexedMode &AM, 732 SelectionDAG &DAG) const { 733 return false; 734 } 735 736 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 737 /// current function. The returned value is a member of the 738 /// MachineJumpTableInfo::JTEntryKind enum. 739 virtual unsigned getJumpTableEncoding() const; 740 741 virtual const MCExpr * 742 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 743 const MachineBasicBlock *MBB, unsigned uid, 744 MCContext &Ctx) const { 745 assert(0 && "Need to implement this hook if target has custom JTIs"); 746 return 0; 747 } 748 749 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 750 /// jumptable. 751 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 752 SelectionDAG &DAG) const; 753 754 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 755 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 756 /// MCExpr. 757 virtual const MCExpr * 758 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 759 unsigned JTI, MCContext &Ctx) const; 760 761 /// isOffsetFoldingLegal - Return true if folding a constant offset 762 /// with the given GlobalAddress is legal. It is frequently not legal in 763 /// PIC relocation models. 764 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 765 766 /// getFunctionAlignment - Return the Log2 alignment of this function. 767 virtual unsigned getFunctionAlignment(const Function *) const = 0; 768 769 //===--------------------------------------------------------------------===// 770 // TargetLowering Optimization Methods 771 // 772 773 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 774 /// SDValues for returning information from TargetLowering to its clients 775 /// that want to combine 776 struct TargetLoweringOpt { 777 SelectionDAG &DAG; 778 bool LegalTys; 779 bool LegalOps; 780 bool ShrinkOps; 781 SDValue Old; 782 SDValue New; 783 784 explicit TargetLoweringOpt(SelectionDAG &InDAG, 785 bool LT, bool LO, 786 bool Shrink = false) : 787 DAG(InDAG), LegalTys(LT), LegalOps(LO), ShrinkOps(Shrink) {} 788 789 bool LegalTypes() const { return LegalTys; } 790 bool LegalOperations() const { return LegalOps; } 791 792 bool CombineTo(SDValue O, SDValue N) { 793 Old = O; 794 New = N; 795 return true; 796 } 797 798 /// ShrinkDemandedConstant - Check to see if the specified operand of the 799 /// specified instruction is a constant integer. If so, check to see if 800 /// there are any bits set in the constant that are not demanded. If so, 801 /// shrink the constant and return true. 802 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 803 804 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 805 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 806 /// cast, but it could be generalized for targets with other types of 807 /// implicit widening casts. 808 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 809 DebugLoc dl); 810 }; 811 812 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 813 /// DemandedMask bits of the result of Op are ever used downstream. If we can 814 /// use this information to simplify Op, create a new simplified DAG node and 815 /// return true, returning the original and new nodes in Old and New. 816 /// Otherwise, analyze the expression and return a mask of KnownOne and 817 /// KnownZero bits for the expression (used to simplify the caller). 818 /// The KnownZero/One bits may only be accurate for those bits in the 819 /// DemandedMask. 820 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 821 APInt &KnownZero, APInt &KnownOne, 822 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 823 824 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 825 /// Mask are known to be either zero or one and return them in the 826 /// KnownZero/KnownOne bitsets. 827 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 828 const APInt &Mask, 829 APInt &KnownZero, 830 APInt &KnownOne, 831 const SelectionDAG &DAG, 832 unsigned Depth = 0) const; 833 834 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 835 /// targets that want to expose additional information about sign bits to the 836 /// DAG Combiner. 837 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 838 unsigned Depth = 0) const; 839 840 struct DAGCombinerInfo { 841 void *DC; // The DAG Combiner object. 842 bool BeforeLegalize; 843 bool BeforeLegalizeOps; 844 bool CalledByLegalizer; 845 public: 846 SelectionDAG &DAG; 847 848 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 849 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 850 CalledByLegalizer(cl), DAG(dag) {} 851 852 bool isBeforeLegalize() const { return BeforeLegalize; } 853 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 854 bool isCalledByLegalizer() const { return CalledByLegalizer; } 855 856 void AddToWorklist(SDNode *N); 857 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 858 bool AddTo = true); 859 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 860 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 861 862 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 863 }; 864 865 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 866 /// and cc. If it is unable to simplify it, return a null SDValue. 867 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 868 ISD::CondCode Cond, bool foldBooleans, 869 DAGCombinerInfo &DCI, DebugLoc dl) const; 870 871 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 872 /// node is a GlobalAddress + offset. 873 virtual bool 874 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 875 876 /// PerformDAGCombine - This method will be invoked for all target nodes and 877 /// for any target-independent nodes that the target has registered with 878 /// invoke it for. 879 /// 880 /// The semantics are as follows: 881 /// Return Value: 882 /// SDValue.Val == 0 - No change was made 883 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 884 /// otherwise - N should be replaced by the returned Operand. 885 /// 886 /// In addition, methods provided by DAGCombinerInfo may be used to perform 887 /// more complex transformations. 888 /// 889 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 890 891 /// isTypeDesirableForOp - Return true if the target has native support for 892 /// the specified value type and it is 'desirable' to use the type for the 893 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 894 /// instruction encodings are longer and some i16 instructions are slow. 895 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const { 896 // By default, assume all legal types are desirable. 897 return isTypeLegal(VT); 898 } 899 900 /// IsDesirableToPromoteOp - This method query the target whether it is 901 /// beneficial for dag combiner to promote the specified node. If true, it 902 /// should return the desired promotion type by reference. 903 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 904 return false; 905 } 906 907 //===--------------------------------------------------------------------===// 908 // TargetLowering Configuration Methods - These methods should be invoked by 909 // the derived class constructor to configure this object for the target. 910 // 911 912protected: 913 /// setShiftAmountType - Describe the type that should be used for shift 914 /// amounts. This type defaults to the pointer type. 915 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 916 917 /// setBooleanContents - Specify how the target extends the result of a 918 /// boolean value from i1 to a wider type. See getBooleanContents. 919 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 920 921 /// setSchedulingPreference - Specify the target scheduling preference. 922 void setSchedulingPreference(SchedPreference Pref) { 923 SchedPreferenceInfo = Pref; 924 } 925 926 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 927 /// use _setjmp to implement llvm.setjmp or the non _ version. 928 /// Defaults to false. 929 void setUseUnderscoreSetJmp(bool Val) { 930 UseUnderscoreSetJmp = Val; 931 } 932 933 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 934 /// use _longjmp to implement llvm.longjmp or the non _ version. 935 /// Defaults to false. 936 void setUseUnderscoreLongJmp(bool Val) { 937 UseUnderscoreLongJmp = Val; 938 } 939 940 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 941 /// specifies the register that llvm.savestack/llvm.restorestack should save 942 /// and restore. 943 void setStackPointerRegisterToSaveRestore(unsigned R) { 944 StackPointerRegisterToSaveRestore = R; 945 } 946 947 /// setExceptionPointerRegister - If set to a physical register, this sets 948 /// the register that receives the exception address on entry to a landing 949 /// pad. 950 void setExceptionPointerRegister(unsigned R) { 951 ExceptionPointerRegister = R; 952 } 953 954 /// setExceptionSelectorRegister - If set to a physical register, this sets 955 /// the register that receives the exception typeid on entry to a landing 956 /// pad. 957 void setExceptionSelectorRegister(unsigned R) { 958 ExceptionSelectorRegister = R; 959 } 960 961 /// SelectIsExpensive - Tells the code generator not to expand operations 962 /// into sequences that use the select operations if possible. 963 void setSelectIsExpensive() { SelectIsExpensive = true; } 964 965 /// setIntDivIsCheap - Tells the code generator that integer divide is 966 /// expensive, and if possible, should be replaced by an alternate sequence 967 /// of instructions not containing an integer divide. 968 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 969 970 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 971 /// srl/add/sra for a signed divide by power of two, and let the target handle 972 /// it. 973 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 974 975 /// addRegisterClass - Add the specified register class as an available 976 /// regclass for the specified value type. This indicates the selector can 977 /// handle values of that class natively. 978 void addRegisterClass(EVT VT, TargetRegisterClass *RC, 979 bool isSynthesizable = true) { 980 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 981 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 982 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 983 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable; 984 } 985 986 /// computeRegisterProperties - Once all of the register classes are added, 987 /// this allows us to compute derived properties we expose. 988 void computeRegisterProperties(); 989 990 /// setOperationAction - Indicate that the specified operation does not work 991 /// with the specified type and indicate what to do about it. 992 void setOperationAction(unsigned Op, MVT VT, 993 LegalizeAction Action) { 994 unsigned I = (unsigned)VT.SimpleTy; 995 unsigned J = I & 31; 996 I = I >> 5; 997 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2)); 998 OpActions[I][Op] |= (uint64_t)Action << (J*2); 999 } 1000 1001 /// setLoadExtAction - Indicate that the specified load with extension does 1002 /// not work with the specified type and indicate what to do about it. 1003 void setLoadExtAction(unsigned ExtType, MVT VT, 1004 LegalizeAction Action) { 1005 assert((unsigned)VT.SimpleTy*2 < 63 && 1006 ExtType < array_lengthof(LoadExtActions) && 1007 "Table isn't big enough!"); 1008 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1009 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2; 1010 } 1011 1012 /// setTruncStoreAction - Indicate that the specified truncating store does 1013 /// not work with the specified type and indicate what to do about it. 1014 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1015 LegalizeAction Action) { 1016 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) && 1017 (unsigned)MemVT.SimpleTy*2 < 63 && 1018 "Table isn't big enough!"); 1019 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2); 1020 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2; 1021 } 1022 1023 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1024 /// does not work with the specified type and indicate what to do abort 1025 /// it. NOTE: All indexed mode loads are initialized to Expand in 1026 /// TargetLowering.cpp 1027 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1028 LegalizeAction Action) { 1029 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1030 IdxMode < array_lengthof(IndexedModeActions[0][0]) && 1031 "Table isn't big enough!"); 1032 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action; 1033 } 1034 1035 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1036 /// does not work with the specified type and indicate what to do about 1037 /// it. NOTE: All indexed mode stores are initialized to Expand in 1038 /// TargetLowering.cpp 1039 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1040 LegalizeAction Action) { 1041 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1042 IdxMode < array_lengthof(IndexedModeActions[0][1] ) && 1043 "Table isn't big enough!"); 1044 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action; 1045 } 1046 1047 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1048 /// supported on the target and indicate what to do about it. 1049 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1050 LegalizeAction Action) { 1051 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1052 (unsigned)CC < array_lengthof(CondCodeActions) && 1053 "Table isn't big enough!"); 1054 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1055 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1056 } 1057 1058 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1059 /// promotion code defaults to trying a larger integer/fp until it can find 1060 /// one that works. If that default is insufficient, this method can be used 1061 /// by the target to override the default. 1062 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1063 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1064 } 1065 1066 /// setTargetDAGCombine - Targets should invoke this method for each target 1067 /// independent node that they want to provide a custom DAG combiner for by 1068 /// implementing the PerformDAGCombine virtual method. 1069 void setTargetDAGCombine(ISD::NodeType NT) { 1070 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1071 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1072 } 1073 1074 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1075 /// bytes); default is 200 1076 void setJumpBufSize(unsigned Size) { 1077 JumpBufSize = Size; 1078 } 1079 1080 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1081 /// alignment (in bytes); default is 0 1082 void setJumpBufAlignment(unsigned Align) { 1083 JumpBufAlignment = Align; 1084 } 1085 1086 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1087 /// limit (in number of instructions); default is 2. 1088 void setIfCvtBlockSizeLimit(unsigned Limit) { 1089 IfCvtBlockSizeLimit = Limit; 1090 } 1091 1092 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1093 /// of instructions) to be considered for code duplication during 1094 /// if-conversion; default is 2. 1095 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1096 IfCvtDupBlockSizeLimit = Limit; 1097 } 1098 1099 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1100 /// alignment is zero, it means the target does not care about loop alignment. 1101 void setPrefLoopAlignment(unsigned Align) { 1102 PrefLoopAlignment = Align; 1103 } 1104 1105public: 1106 1107 virtual const TargetSubtarget *getSubtarget() const { 1108 assert(0 && "Not Implemented"); 1109 return NULL; // this is here to silence compiler errors 1110 } 1111 1112 //===--------------------------------------------------------------------===// 1113 // Lowering methods - These methods must be implemented by targets so that 1114 // the SelectionDAGLowering code knows how to lower these. 1115 // 1116 1117 /// LowerFormalArguments - This hook must be implemented to lower the 1118 /// incoming (formal) arguments, described by the Ins array, into the 1119 /// specified DAG. The implementation should fill in the InVals array 1120 /// with legal-type argument values, and return the resulting token 1121 /// chain value. 1122 /// 1123 virtual SDValue 1124 LowerFormalArguments(SDValue Chain, 1125 CallingConv::ID CallConv, bool isVarArg, 1126 const SmallVectorImpl<ISD::InputArg> &Ins, 1127 DebugLoc dl, SelectionDAG &DAG, 1128 SmallVectorImpl<SDValue> &InVals) const { 1129 assert(0 && "Not Implemented"); 1130 return SDValue(); // this is here to silence compiler errors 1131 } 1132 1133 /// LowerCallTo - This function lowers an abstract call to a function into an 1134 /// actual call. This returns a pair of operands. The first element is the 1135 /// return value for the function (if RetTy is not VoidTy). The second 1136 /// element is the outgoing token chain. It calls LowerCall to do the actual 1137 /// lowering. 1138 struct ArgListEntry { 1139 SDValue Node; 1140 const Type* Ty; 1141 bool isSExt : 1; 1142 bool isZExt : 1; 1143 bool isInReg : 1; 1144 bool isSRet : 1; 1145 bool isNest : 1; 1146 bool isByVal : 1; 1147 uint16_t Alignment; 1148 1149 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1150 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1151 }; 1152 typedef std::vector<ArgListEntry> ArgListTy; 1153 std::pair<SDValue, SDValue> 1154 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1155 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1156 CallingConv::ID CallConv, bool isTailCall, 1157 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1158 SelectionDAG &DAG, DebugLoc dl) const; 1159 1160 /// LowerCall - This hook must be implemented to lower calls into the 1161 /// the specified DAG. The outgoing arguments to the call are described 1162 /// by the Outs array, and the values to be returned by the call are 1163 /// described by the Ins array. The implementation should fill in the 1164 /// InVals array with legal-type return values from the call, and return 1165 /// the resulting token chain value. 1166 virtual SDValue 1167 LowerCall(SDValue Chain, SDValue Callee, 1168 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 1169 const SmallVectorImpl<ISD::OutputArg> &Outs, 1170 const SmallVectorImpl<ISD::InputArg> &Ins, 1171 DebugLoc dl, SelectionDAG &DAG, 1172 SmallVectorImpl<SDValue> &InVals) const { 1173 assert(0 && "Not Implemented"); 1174 return SDValue(); // this is here to silence compiler errors 1175 } 1176 1177 /// CanLowerReturn - This hook should be implemented to check whether the 1178 /// return values described by the Outs array can fit into the return 1179 /// registers. If false is returned, an sret-demotion is performed. 1180 /// 1181 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1182 const SmallVectorImpl<EVT> &OutTys, 1183 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1184 SelectionDAG &DAG) const 1185 { 1186 // Return true by default to get preexisting behavior. 1187 return true; 1188 } 1189 1190 /// LowerReturn - This hook must be implemented to lower outgoing 1191 /// return values, described by the Outs array, into the specified 1192 /// DAG. The implementation should return the resulting token chain 1193 /// value. 1194 /// 1195 virtual SDValue 1196 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1197 const SmallVectorImpl<ISD::OutputArg> &Outs, 1198 DebugLoc dl, SelectionDAG &DAG) const { 1199 assert(0 && "Not Implemented"); 1200 return SDValue(); // this is here to silence compiler errors 1201 } 1202 1203 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1204 /// memcpy. This can be used by targets to provide code sequences for cases 1205 /// that don't fit the target's parameters for simple loads/stores and can be 1206 /// more efficient than using a library call. This function can return a null 1207 /// SDValue if the target declines to use custom code and a different 1208 /// lowering strategy should be used. 1209 /// 1210 /// If AlwaysInline is true, the size is constant and the target should not 1211 /// emit any calls and is strongly encouraged to attempt to emit inline code 1212 /// even if it is beyond the usual threshold because this intrinsic is being 1213 /// expanded in a place where calls are not feasible (e.g. within the prologue 1214 /// for another call). If the target chooses to decline an AlwaysInline 1215 /// request here, legalize will resort to using simple loads and stores. 1216 virtual SDValue 1217 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1218 SDValue Chain, 1219 SDValue Op1, SDValue Op2, 1220 SDValue Op3, unsigned Align, bool isVolatile, 1221 bool AlwaysInline, 1222 const Value *DstSV, uint64_t DstOff, 1223 const Value *SrcSV, uint64_t SrcOff) const { 1224 return SDValue(); 1225 } 1226 1227 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1228 /// memmove. This can be used by targets to provide code sequences for cases 1229 /// that don't fit the target's parameters for simple loads/stores and can be 1230 /// more efficient than using a library call. This function can return a null 1231 /// SDValue if the target declines to use custom code and a different 1232 /// lowering strategy should be used. 1233 virtual SDValue 1234 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1235 SDValue Chain, 1236 SDValue Op1, SDValue Op2, 1237 SDValue Op3, unsigned Align, bool isVolatile, 1238 const Value *DstSV, uint64_t DstOff, 1239 const Value *SrcSV, uint64_t SrcOff) const { 1240 return SDValue(); 1241 } 1242 1243 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1244 /// memset. This can be used by targets to provide code sequences for cases 1245 /// that don't fit the target's parameters for simple stores and can be more 1246 /// efficient than using a library call. This function can return a null 1247 /// SDValue if the target declines to use custom code and a different 1248 /// lowering strategy should be used. 1249 virtual SDValue 1250 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1251 SDValue Chain, 1252 SDValue Op1, SDValue Op2, 1253 SDValue Op3, unsigned Align, bool isVolatile, 1254 const Value *DstSV, uint64_t DstOff) const { 1255 return SDValue(); 1256 } 1257 1258 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1259 /// to legalize nodes with an illegal operand type but legal result types. 1260 /// It replaces the LowerOperation callback in the type Legalizer. 1261 /// The reason we can not do away with LowerOperation entirely is that 1262 /// LegalizeDAG isn't yet ready to use this callback. 1263 /// TODO: Consider merging with ReplaceNodeResults. 1264 1265 /// The target places new result values for the node in Results (their number 1266 /// and types must exactly match those of the original return values of 1267 /// the node), or leaves Results empty, which indicates that the node is not 1268 /// to be custom lowered after all. 1269 /// The default implementation calls LowerOperation. 1270 virtual void LowerOperationWrapper(SDNode *N, 1271 SmallVectorImpl<SDValue> &Results, 1272 SelectionDAG &DAG) const; 1273 1274 /// LowerOperation - This callback is invoked for operations that are 1275 /// unsupported by the target, which are registered to use 'custom' lowering, 1276 /// and whose defined values are all legal. 1277 /// If the target has no operations that require custom lowering, it need not 1278 /// implement this. The default implementation of this aborts. 1279 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1280 1281 /// ReplaceNodeResults - This callback is invoked when a node result type is 1282 /// illegal for the target, and the operation was registered to use 'custom' 1283 /// lowering for that result type. The target places new result values for 1284 /// the node in Results (their number and types must exactly match those of 1285 /// the original return values of the node), or leaves Results empty, which 1286 /// indicates that the node is not to be custom lowered after all. 1287 /// 1288 /// If the target has no operations that require custom lowering, it need not 1289 /// implement this. The default implementation aborts. 1290 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1291 SelectionDAG &DAG) const { 1292 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1293 } 1294 1295 /// getTargetNodeName() - This method returns the name of a target specific 1296 /// DAG node. 1297 virtual const char *getTargetNodeName(unsigned Opcode) const; 1298 1299 /// createFastISel - This method returns a target specific FastISel object, 1300 /// or null if the target does not support "fast" ISel. 1301 virtual FastISel * 1302 createFastISel(MachineFunction &, 1303 DenseMap<const Value *, unsigned> &, 1304 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1305 DenseMap<const AllocaInst *, int> & 1306#ifndef NDEBUG 1307 , SmallSet<const Instruction *, 8> &CatchInfoLost 1308#endif 1309 ) const { 1310 return 0; 1311 } 1312 1313 //===--------------------------------------------------------------------===// 1314 // Inline Asm Support hooks 1315 // 1316 1317 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1318 /// call to be explicit llvm code if it wants to. This is useful for 1319 /// turning simple inline asms into LLVM intrinsics, which gives the 1320 /// compiler more information about the behavior of the code. 1321 virtual bool ExpandInlineAsm(CallInst *CI) const { 1322 return false; 1323 } 1324 1325 enum ConstraintType { 1326 C_Register, // Constraint represents specific register(s). 1327 C_RegisterClass, // Constraint represents any of register(s) in class. 1328 C_Memory, // Memory constraint. 1329 C_Other, // Something else. 1330 C_Unknown // Unsupported constraint. 1331 }; 1332 1333 /// AsmOperandInfo - This contains information for each constraint that we are 1334 /// lowering. 1335 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1336 /// ConstraintCode - This contains the actual string for the code, like "m". 1337 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1338 /// most closely matches the operand. 1339 std::string ConstraintCode; 1340 1341 /// ConstraintType - Information about the constraint code, e.g. Register, 1342 /// RegisterClass, Memory, Other, Unknown. 1343 TargetLowering::ConstraintType ConstraintType; 1344 1345 /// CallOperandval - If this is the result output operand or a 1346 /// clobber, this is null, otherwise it is the incoming operand to the 1347 /// CallInst. This gets modified as the asm is processed. 1348 Value *CallOperandVal; 1349 1350 /// ConstraintVT - The ValueType for the operand value. 1351 EVT ConstraintVT; 1352 1353 /// isMatchingInputConstraint - Return true of this is an input operand that 1354 /// is a matching constraint like "4". 1355 bool isMatchingInputConstraint() const; 1356 1357 /// getMatchedOperand - If this is an input matching constraint, this method 1358 /// returns the output operand it matches. 1359 unsigned getMatchedOperand() const; 1360 1361 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1362 : InlineAsm::ConstraintInfo(info), 1363 ConstraintType(TargetLowering::C_Unknown), 1364 CallOperandVal(0), ConstraintVT(MVT::Other) { 1365 } 1366 }; 1367 1368 /// ComputeConstraintToUse - Determines the constraint code and constraint 1369 /// type to use for the specific AsmOperandInfo, setting 1370 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1371 /// being passed in is available, it can be passed in as Op, otherwise an 1372 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1373 /// constraint of the inline asm instruction being processed is 'm'. 1374 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1375 SDValue Op, 1376 bool hasMemory, 1377 SelectionDAG *DAG = 0) const; 1378 1379 /// getConstraintType - Given a constraint, return the type of constraint it 1380 /// is for this target. 1381 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1382 1383 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1384 /// return a list of registers that can be used to satisfy the constraint. 1385 /// This should only be used for C_RegisterClass constraints. 1386 virtual std::vector<unsigned> 1387 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1388 EVT VT) const; 1389 1390 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1391 /// {edx}), return the register number and the register class for the 1392 /// register. 1393 /// 1394 /// Given a register class constraint, like 'r', if this corresponds directly 1395 /// to an LLVM register class, return a register of 0 and the register class 1396 /// pointer. 1397 /// 1398 /// This should only be used for C_Register constraints. On error, 1399 /// this returns a register number of 0 and a null register class pointer.. 1400 virtual std::pair<unsigned, const TargetRegisterClass*> 1401 getRegForInlineAsmConstraint(const std::string &Constraint, 1402 EVT VT) const; 1403 1404 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1405 /// with another that has more specific requirements based on the type of the 1406 /// corresponding operand. This returns null if there is no replacement to 1407 /// make. 1408 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1409 1410 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1411 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1412 /// it means one of the asm constraint of the inline asm instruction being 1413 /// processed is 'm'. 1414 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1415 bool hasMemory, 1416 std::vector<SDValue> &Ops, 1417 SelectionDAG &DAG) const; 1418 1419 //===--------------------------------------------------------------------===// 1420 // Instruction Emitting Hooks 1421 // 1422 1423 // EmitInstrWithCustomInserter - This method should be implemented by targets 1424 // that mark instructions with the 'usesCustomInserter' flag. These 1425 // instructions are special in various ways, which require special support to 1426 // insert. The specified MachineInstr is created but not inserted into any 1427 // basic blocks, and this method is called to expand it into a sequence of 1428 // instructions, potentially also creating new basic blocks and control flow. 1429 // When new basic blocks are inserted and the edges from MBB to its successors 1430 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the 1431 // DenseMap. 1432 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1433 MachineBasicBlock *MBB, 1434 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 1435 1436 //===--------------------------------------------------------------------===// 1437 // Addressing mode description hooks (used by LSR etc). 1438 // 1439 1440 /// AddrMode - This represents an addressing mode of: 1441 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1442 /// If BaseGV is null, there is no BaseGV. 1443 /// If BaseOffs is zero, there is no base offset. 1444 /// If HasBaseReg is false, there is no base register. 1445 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1446 /// no scale. 1447 /// 1448 struct AddrMode { 1449 GlobalValue *BaseGV; 1450 int64_t BaseOffs; 1451 bool HasBaseReg; 1452 int64_t Scale; 1453 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1454 }; 1455 1456 /// isLegalAddressingMode - Return true if the addressing mode represented by 1457 /// AM is legal for this target, for a load/store of the specified type. 1458 /// The type may be VoidTy, in which case only return true if the addressing 1459 /// mode is legal for a load/store of any legal type. 1460 /// TODO: Handle pre/postinc as well. 1461 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1462 1463 /// isTruncateFree - Return true if it's free to truncate a value of 1464 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1465 /// register EAX to i16 by referencing its sub-register AX. 1466 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1467 return false; 1468 } 1469 1470 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1471 return false; 1472 } 1473 1474 /// isZExtFree - Return true if any actual instruction that defines a 1475 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1476 /// register. This does not necessarily include registers defined in 1477 /// unknown ways, such as incoming arguments, or copies from unknown 1478 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1479 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1480 /// all instructions that define 32-bit values implicit zero-extend the 1481 /// result out to 64 bits. 1482 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1483 return false; 1484 } 1485 1486 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1487 return false; 1488 } 1489 1490 /// isNarrowingProfitable - Return true if it's profitable to narrow 1491 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1492 /// from i32 to i8 but not from i32 to i16. 1493 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1494 return false; 1495 } 1496 1497 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1498 /// icmp immediate, that is the target has icmp instructions which can compare 1499 /// a register against the immediate without having to materialize the 1500 /// immediate into a register. 1501 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1502 return true; 1503 } 1504 1505 //===--------------------------------------------------------------------===// 1506 // Div utility functions 1507 // 1508 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1509 std::vector<SDNode*>* Created) const; 1510 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1511 std::vector<SDNode*>* Created) const; 1512 1513 1514 //===--------------------------------------------------------------------===// 1515 // Runtime Library hooks 1516 // 1517 1518 /// setLibcallName - Rename the default libcall routine name for the specified 1519 /// libcall. 1520 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1521 LibcallRoutineNames[Call] = Name; 1522 } 1523 1524 /// getLibcallName - Get the libcall routine name for the specified libcall. 1525 /// 1526 const char *getLibcallName(RTLIB::Libcall Call) const { 1527 return LibcallRoutineNames[Call]; 1528 } 1529 1530 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1531 /// result of the comparison libcall against zero. 1532 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1533 CmpLibcallCCs[Call] = CC; 1534 } 1535 1536 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1537 /// the comparison libcall against zero. 1538 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1539 return CmpLibcallCCs[Call]; 1540 } 1541 1542 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1543 /// specified libcall. 1544 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1545 LibcallCallingConvs[Call] = CC; 1546 } 1547 1548 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1549 /// specified libcall. 1550 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1551 return LibcallCallingConvs[Call]; 1552 } 1553 1554private: 1555 const TargetMachine &TM; 1556 const TargetData *TD; 1557 const TargetLoweringObjectFile &TLOF; 1558 1559 /// PointerTy - The type to use for pointers, usually i32 or i64. 1560 /// 1561 MVT PointerTy; 1562 1563 /// IsLittleEndian - True if this is a little endian target. 1564 /// 1565 bool IsLittleEndian; 1566 1567 /// SelectIsExpensive - Tells the code generator not to expand operations 1568 /// into sequences that use the select operations if possible. 1569 bool SelectIsExpensive; 1570 1571 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1572 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1573 /// a real cost model is in place. If we ever optimize for size, this will be 1574 /// set to true unconditionally. 1575 bool IntDivIsCheap; 1576 1577 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1578 /// srl/add/sra for a signed divide by power of two, and let the target handle 1579 /// it. 1580 bool Pow2DivIsCheap; 1581 1582 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1583 /// llvm.setjmp. Defaults to false. 1584 bool UseUnderscoreSetJmp; 1585 1586 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1587 /// llvm.longjmp. Defaults to false. 1588 bool UseUnderscoreLongJmp; 1589 1590 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1591 /// PointerTy is. 1592 MVT ShiftAmountTy; 1593 1594 /// BooleanContents - Information about the contents of the high-bits in 1595 /// boolean values held in a type wider than i1. See getBooleanContents. 1596 BooleanContent BooleanContents; 1597 1598 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1599 /// total cycles or lowest register usage. 1600 SchedPreference SchedPreferenceInfo; 1601 1602 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1603 unsigned JumpBufSize; 1604 1605 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1606 /// buffers 1607 unsigned JumpBufAlignment; 1608 1609 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1610 /// if-converted. 1611 unsigned IfCvtBlockSizeLimit; 1612 1613 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1614 /// duplicated during if-conversion. 1615 unsigned IfCvtDupBlockSizeLimit; 1616 1617 /// PrefLoopAlignment - The perferred loop alignment. 1618 /// 1619 unsigned PrefLoopAlignment; 1620 1621 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1622 /// specifies the register that llvm.savestack/llvm.restorestack should save 1623 /// and restore. 1624 unsigned StackPointerRegisterToSaveRestore; 1625 1626 /// ExceptionPointerRegister - If set to a physical register, this specifies 1627 /// the register that receives the exception address on entry to a landing 1628 /// pad. 1629 unsigned ExceptionPointerRegister; 1630 1631 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1632 /// the register that receives the exception typeid on entry to a landing 1633 /// pad. 1634 unsigned ExceptionSelectorRegister; 1635 1636 /// RegClassForVT - This indicates the default register class to use for 1637 /// each ValueType the target supports natively. 1638 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1639 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1640 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1641 1642 /// Synthesizable indicates whether it is OK for the compiler to create new 1643 /// operations using this type. All Legal types are Synthesizable except 1644 /// MMX types on X86. Non-Legal types are not Synthesizable. 1645 bool Synthesizable[MVT::LAST_VALUETYPE]; 1646 1647 /// TransformToType - For any value types we are promoting or expanding, this 1648 /// contains the value type that we are changing to. For Expanded types, this 1649 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1650 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1651 /// by the system, this holds the same type (e.g. i32 -> i32). 1652 EVT TransformToType[MVT::LAST_VALUETYPE]; 1653 1654 /// OpActions - For each operation and each value type, keep a LegalizeAction 1655 /// that indicates how instruction selection should deal with the operation. 1656 /// Most operations are Legal (aka, supported natively by the target), but 1657 /// operations that are not should be described. Note that operations on 1658 /// non-legal value types are not described here. 1659 /// This array is accessed using VT.getSimpleVT(), so it is subject to 1660 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits. 1661 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END]; 1662 1663 /// LoadExtActions - For each load of load extension type and each value type, 1664 /// keep a LegalizeAction that indicates how instruction selection should deal 1665 /// with the load. 1666 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1667 1668 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1669 /// indicates how instruction selection should deal with the store. 1670 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1671 1672 /// IndexedModeActions - For each indexed mode and each value type, 1673 /// keep a pair of LegalizeAction that indicates how instruction 1674 /// selection should deal with the load / store. The first 1675 /// dimension is now the value_type for the reference. The second 1676 /// dimension is the load [0] vs. store[1]. The third dimension 1677 /// represents the various modes for load store. 1678 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE]; 1679 1680 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1681 /// LegalizeAction that indicates how instruction selection should 1682 /// deal with the condition code. 1683 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1684 1685 ValueTypeActionImpl ValueTypeActions; 1686 1687 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1688 1689 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1690 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1691 /// which sets a bit in this array. 1692 unsigned char 1693 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1694 1695 /// PromoteToType - For operations that must be promoted to a specific type, 1696 /// this holds the destination type. This map should be sparse, so don't hold 1697 /// it as an array. 1698 /// 1699 /// Targets add entries to this map with AddPromotedToType(..), clients access 1700 /// this with getTypeToPromoteTo(..). 1701 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1702 PromoteToType; 1703 1704 /// LibcallRoutineNames - Stores the name each libcall. 1705 /// 1706 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1707 1708 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1709 /// of each of the comparison libcall against zero. 1710 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1711 1712 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1713 /// libcall. 1714 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1715 1716protected: 1717 /// When lowering \@llvm.memset this field specifies the maximum number of 1718 /// store operations that may be substituted for the call to memset. Targets 1719 /// must set this value based on the cost threshold for that target. Targets 1720 /// should assume that the memset will be done using as many of the largest 1721 /// store operations first, followed by smaller ones, if necessary, per 1722 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1723 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1724 /// store. This only applies to setting a constant array of a constant size. 1725 /// @brief Specify maximum number of store instructions per memset call. 1726 unsigned maxStoresPerMemset; 1727 1728 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1729 /// store operations that may be substituted for a call to memcpy. Targets 1730 /// must set this value based on the cost threshold for that target. Targets 1731 /// should assume that the memcpy will be done using as many of the largest 1732 /// store operations first, followed by smaller ones, if necessary, per 1733 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1734 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1735 /// and one 1-byte store. This only applies to copying a constant array of 1736 /// constant size. 1737 /// @brief Specify maximum bytes of store instructions per memcpy call. 1738 unsigned maxStoresPerMemcpy; 1739 1740 /// When lowering \@llvm.memmove this field specifies the maximum number of 1741 /// store instructions that may be substituted for a call to memmove. Targets 1742 /// must set this value based on the cost threshold for that target. Targets 1743 /// should assume that the memmove will be done using as many of the largest 1744 /// store operations first, followed by smaller ones, if necessary, per 1745 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1746 /// with 8-bit alignment would result in nine 1-byte stores. This only 1747 /// applies to copying a constant array of constant size. 1748 /// @brief Specify maximum bytes of store instructions per memmove call. 1749 unsigned maxStoresPerMemmove; 1750 1751 /// This field specifies whether the target can benefit from code placement 1752 /// optimization. 1753 bool benefitFromCodePlacementOpt; 1754}; 1755} // end llvm namespace 1756 1757#endif 1758