TargetLowering.h revision f17008844adfeb3716969a6004e28dcf176a38b2
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/InlineAsm.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/ADT/APFloat.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallSet.h" 31#include "llvm/ADT/SmallVector.h" 32#include "llvm/ADT/STLExtras.h" 33#include "llvm/Support/DebugLoc.h" 34#include "llvm/Target/TargetMachine.h" 35#include <climits> 36#include <map> 37#include <vector> 38 39namespace llvm { 40 class AllocaInst; 41 class CallInst; 42 class Function; 43 class FastISel; 44 class MachineBasicBlock; 45 class MachineFunction; 46 class MachineFrameInfo; 47 class MachineInstr; 48 class MachineModuleInfo; 49 class DwarfWriter; 50 class SDNode; 51 class SDValue; 52 class SelectionDAG; 53 class TargetData; 54 class TargetMachine; 55 class TargetRegisterClass; 56 class TargetSubtarget; 57 class TargetLoweringObjectFile; 58 class Value; 59 60 // FIXME: should this be here? 61 namespace TLSModel { 62 enum Model { 63 GeneralDynamic, 64 LocalDynamic, 65 InitialExec, 66 LocalExec 67 }; 68 } 69 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 70 71 72//===----------------------------------------------------------------------===// 73/// TargetLowering - This class defines information used to lower LLVM code to 74/// legal SelectionDAG operators that the target instruction selector can accept 75/// natively. 76/// 77/// This class also defines callbacks that targets must implement to lower 78/// target-specific constructs to SelectionDAG operators. 79/// 80class TargetLowering { 81 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 82 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 83public: 84 /// LegalizeAction - This enum indicates whether operations are valid for a 85 /// target, and if not, what action should be used to make them valid. 86 enum LegalizeAction { 87 Legal, // The target natively supports this operation. 88 Promote, // This operation should be executed in a larger type. 89 Expand, // Try to expand this to other ops, otherwise use a libcall. 90 Custom // Use the LowerOperation hook to implement custom lowering. 91 }; 92 93 enum BooleanContent { // How the target represents true/false values. 94 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 95 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 96 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 97 }; 98 99 enum SchedPreference { 100 SchedulingForLatency, // Scheduling for shortest total latency. 101 SchedulingForRegPressure // Scheduling for lowest register pressure. 102 }; 103 104 /// NOTE: The constructor takes ownership of TLOF. 105 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF); 106 virtual ~TargetLowering(); 107 108 TargetMachine &getTargetMachine() const { return TM; } 109 const TargetData *getTargetData() const { return TD; } 110 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 111 112 bool isBigEndian() const { return !IsLittleEndian; } 113 bool isLittleEndian() const { return IsLittleEndian; } 114 MVT getPointerTy() const { return PointerTy; } 115 MVT getShiftAmountTy() const { return ShiftAmountTy; } 116 117 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 118 /// codegen. 119 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 120 121 /// isSelectExpensive - Return true if the select operation is expensive for 122 /// this target. 123 bool isSelectExpensive() const { return SelectIsExpensive; } 124 125 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 126 /// a sequence of several shifts, adds, and multiplies for this target. 127 bool isIntDivCheap() const { return IntDivIsCheap; } 128 129 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 130 /// srl/add/sra. 131 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 132 133 /// getSetCCResultType - Return the ValueType of the result of SETCC 134 /// operations. Also used to obtain the target's preferred type for 135 /// the condition operand of SELECT and BRCOND nodes. In the case of 136 /// BRCOND the argument passed is MVT::Other since there are no other 137 /// operands to get a type hint from. 138 virtual MVT getSetCCResultType(MVT VT) const; 139 140 /// getBooleanContents - For targets without i1 registers, this gives the 141 /// nature of the high-bits of boolean values held in types wider than i1. 142 /// "Boolean values" are special true/false values produced by nodes like 143 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 144 /// Not to be confused with general values promoted from i1. 145 BooleanContent getBooleanContents() const { return BooleanContents;} 146 147 /// getSchedulingPreference - Return target scheduling preference. 148 SchedPreference getSchedulingPreference() const { 149 return SchedPreferenceInfo; 150 } 151 152 /// getRegClassFor - Return the register class that should be used for the 153 /// specified value type. This may only be called on legal types. 154 TargetRegisterClass *getRegClassFor(MVT VT) const { 155 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 156 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; 157 assert(RC && "This value type is not natively supported!"); 158 return RC; 159 } 160 161 /// isTypeLegal - Return true if the target has native support for the 162 /// specified value type. This means that it has a register that directly 163 /// holds it without promotions or expansions. 164 bool isTypeLegal(MVT VT) const { 165 assert(!VT.isSimple() || 166 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 167 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; 168 } 169 170 class ValueTypeActionImpl { 171 /// ValueTypeActions - This is a bitvector that contains two bits for each 172 /// value type, where the two bits correspond to the LegalizeAction enum. 173 /// This can be queried with "getTypeAction(VT)". 174 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2 175 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2]; 176 public: 177 ValueTypeActionImpl() { 178 ValueTypeActions[0] = ValueTypeActions[1] = 0; 179 ValueTypeActions[2] = ValueTypeActions[3] = 0; 180 } 181 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 182 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 183 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 184 ValueTypeActions[2] = RHS.ValueTypeActions[2]; 185 ValueTypeActions[3] = RHS.ValueTypeActions[3]; 186 } 187 188 LegalizeAction getTypeAction(MVT VT) const { 189 if (VT.isExtended()) { 190 if (VT.isVector()) { 191 return VT.isPow2VectorType() ? Expand : Promote; 192 } 193 if (VT.isInteger()) 194 // First promote to a power-of-two size, then expand if necessary. 195 return VT == VT.getRoundIntegerType() ? Expand : Promote; 196 assert(0 && "Unsupported extended type!"); 197 return Legal; 198 } 199 unsigned I = VT.getSimpleVT(); 200 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 201 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 202 } 203 void setTypeAction(MVT VT, LegalizeAction Action) { 204 unsigned I = VT.getSimpleVT(); 205 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 206 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 207 } 208 }; 209 210 const ValueTypeActionImpl &getValueTypeActions() const { 211 return ValueTypeActions; 212 } 213 214 /// getTypeAction - Return how we should legalize values of this type, either 215 /// it is already legal (return 'Legal') or we need to promote it to a larger 216 /// type (return 'Promote'), or we need to expand it into multiple registers 217 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 218 LegalizeAction getTypeAction(MVT VT) const { 219 return ValueTypeActions.getTypeAction(VT); 220 } 221 222 /// getTypeToTransformTo - For types supported by the target, this is an 223 /// identity function. For types that must be promoted to larger types, this 224 /// returns the larger type to promote to. For integer types that are larger 225 /// than the largest integer register, this contains one step in the expansion 226 /// to get to the smaller register. For illegal floating point types, this 227 /// returns the integer type to transform to. 228 MVT getTypeToTransformTo(MVT VT) const { 229 if (VT.isSimple()) { 230 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); 231 MVT NVT = TransformToType[VT.getSimpleVT()]; 232 assert(getTypeAction(NVT) != Promote && 233 "Promote may not follow Expand or Promote"); 234 return NVT; 235 } 236 237 if (VT.isVector()) { 238 MVT NVT = VT.getPow2VectorType(); 239 if (NVT == VT) { 240 // Vector length is a power of 2 - split to half the size. 241 unsigned NumElts = VT.getVectorNumElements(); 242 MVT EltVT = VT.getVectorElementType(); 243 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2); 244 } 245 // Promote to a power of two size, avoiding multi-step promotion. 246 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 247 } else if (VT.isInteger()) { 248 MVT NVT = VT.getRoundIntegerType(); 249 if (NVT == VT) 250 // Size is a power of two - expand to half the size. 251 return MVT::getIntegerVT(VT.getSizeInBits() / 2); 252 else 253 // Promote to a power of two size, avoiding multi-step promotion. 254 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 255 } 256 assert(0 && "Unsupported extended type!"); 257 return MVT(MVT::Other); // Not reached 258 } 259 260 /// getTypeToExpandTo - For types supported by the target, this is an 261 /// identity function. For types that must be expanded (i.e. integer types 262 /// that are larger than the largest integer register or illegal floating 263 /// point types), this returns the largest legal type it will be expanded to. 264 MVT getTypeToExpandTo(MVT VT) const { 265 assert(!VT.isVector()); 266 while (true) { 267 switch (getTypeAction(VT)) { 268 case Legal: 269 return VT; 270 case Expand: 271 VT = getTypeToTransformTo(VT); 272 break; 273 default: 274 assert(false && "Type is not legal nor is it to be expanded!"); 275 return VT; 276 } 277 } 278 return VT; 279 } 280 281 /// getVectorTypeBreakdown - Vector types are broken down into some number of 282 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 283 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 284 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 285 /// 286 /// This method returns the number of registers needed, and the VT for each 287 /// register. It also returns the VT and quantity of the intermediate values 288 /// before they are promoted/expanded. 289 /// 290 unsigned getVectorTypeBreakdown(MVT VT, 291 MVT &IntermediateVT, 292 unsigned &NumIntermediates, 293 MVT &RegisterVT) const; 294 295 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 296 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 297 /// this is the case, it returns true and store the intrinsic 298 /// information into the IntrinsicInfo that was passed to the function. 299 typedef struct IntrinsicInfo { 300 unsigned opc; // target opcode 301 MVT memVT; // memory VT 302 const Value* ptrVal; // value representing memory location 303 int offset; // offset off of ptrVal 304 unsigned align; // alignment 305 bool vol; // is volatile? 306 bool readMem; // reads memory? 307 bool writeMem; // writes memory? 308 } IntrinisicInfo; 309 310 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 311 CallInst &I, unsigned Intrinsic) { 312 return false; 313 } 314 315 /// getWidenVectorType: given a vector type, returns the type to widen to 316 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 317 /// If there is no vector type that we want to widen to, returns MVT::Other 318 /// When and were to widen is target dependent based on the cost of 319 /// scalarizing vs using the wider vector type. 320 virtual MVT getWidenVectorType(MVT VT) const; 321 322 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 323 legal_fpimm_iterator legal_fpimm_begin() const { 324 return LegalFPImmediates.begin(); 325 } 326 legal_fpimm_iterator legal_fpimm_end() const { 327 return LegalFPImmediates.end(); 328 } 329 330 /// isShuffleMaskLegal - Targets can use this to indicate that they only 331 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 332 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 333 /// are assumed to be legal. 334 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 335 MVT VT) const { 336 return true; 337 } 338 339 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 340 /// used by Targets can use this to indicate if there is a suitable 341 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 342 /// pool entry. 343 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 344 MVT VT) const { 345 return false; 346 } 347 348 /// getOperationAction - Return how this operation should be treated: either 349 /// it is legal, needs to be promoted to a larger size, needs to be 350 /// expanded to some other code sequence, or the target has a custom expander 351 /// for it. 352 LegalizeAction getOperationAction(unsigned Op, MVT VT) const { 353 if (VT.isExtended()) return Expand; 354 assert(Op < array_lengthof(OpActions[0]) && 355 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 && 356 "Table isn't big enough!"); 357 unsigned I = (unsigned) VT.getSimpleVT(); 358 unsigned J = I & 31; 359 I = I >> 5; 360 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3); 361 } 362 363 /// isOperationLegalOrCustom - Return true if the specified operation is 364 /// legal on this target or can be made legal with custom lowering. This 365 /// is used to help guide high-level lowering decisions. 366 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const { 367 return (VT == MVT::Other || isTypeLegal(VT)) && 368 (getOperationAction(Op, VT) == Legal || 369 getOperationAction(Op, VT) == Custom); 370 } 371 372 /// isOperationLegal - Return true if the specified operation is legal on this 373 /// target. 374 bool isOperationLegal(unsigned Op, MVT VT) const { 375 return (VT == MVT::Other || isTypeLegal(VT)) && 376 getOperationAction(Op, VT) == Legal; 377 } 378 379 /// getLoadExtAction - Return how this load with extension should be treated: 380 /// either it is legal, needs to be promoted to a larger size, needs to be 381 /// expanded to some other code sequence, or the target has a custom expander 382 /// for it. 383 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const { 384 assert(LType < array_lengthof(LoadExtActions) && 385 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 386 "Table isn't big enough!"); 387 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3); 388 } 389 390 /// isLoadExtLegal - Return true if the specified load with extension is legal 391 /// on this target. 392 bool isLoadExtLegal(unsigned LType, MVT VT) const { 393 return VT.isSimple() && 394 (getLoadExtAction(LType, VT) == Legal || 395 getLoadExtAction(LType, VT) == Custom); 396 } 397 398 /// getTruncStoreAction - Return how this store with truncation should be 399 /// treated: either it is legal, needs to be promoted to a larger size, needs 400 /// to be expanded to some other code sequence, or the target has a custom 401 /// expander for it. 402 LegalizeAction getTruncStoreAction(MVT ValVT, 403 MVT MemVT) const { 404 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 405 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 406 "Table isn't big enough!"); 407 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> 408 (2*MemVT.getSimpleVT())) & 3); 409 } 410 411 /// isTruncStoreLegal - Return true if the specified store with truncation is 412 /// legal on this target. 413 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { 414 return isTypeLegal(ValVT) && MemVT.isSimple() && 415 (getTruncStoreAction(ValVT, MemVT) == Legal || 416 getTruncStoreAction(ValVT, MemVT) == Custom); 417 } 418 419 /// getIndexedLoadAction - Return how the indexed load should be treated: 420 /// either it is legal, needs to be promoted to a larger size, needs to be 421 /// expanded to some other code sequence, or the target has a custom expander 422 /// for it. 423 LegalizeAction 424 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 425 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) && 426 ((unsigned)VT.getSimpleVT()) < MVT::LAST_VALUETYPE && 427 "Table isn't big enough!"); 428 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode])); 429 } 430 431 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 432 /// on this target. 433 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { 434 return VT.isSimple() && 435 (getIndexedLoadAction(IdxMode, VT) == Legal || 436 getIndexedLoadAction(IdxMode, VT) == Custom); 437 } 438 439 /// getIndexedStoreAction - Return how the indexed store should be treated: 440 /// either it is legal, needs to be promoted to a larger size, needs to be 441 /// expanded to some other code sequence, or the target has a custom expander 442 /// for it. 443 LegalizeAction 444 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 445 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) && 446 (unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE && 447 "Table isn't big enough!"); 448 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode])); 449 } 450 451 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 452 /// on this target. 453 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { 454 return VT.isSimple() && 455 (getIndexedStoreAction(IdxMode, VT) == Legal || 456 getIndexedStoreAction(IdxMode, VT) == Custom); 457 } 458 459 /// getConvertAction - Return how the conversion should be treated: 460 /// either it is legal, needs to be promoted to a larger size, needs to be 461 /// expanded to some other code sequence, or the target has a custom expander 462 /// for it. 463 LegalizeAction 464 getConvertAction(MVT FromVT, MVT ToVT) const { 465 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 466 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 467 "Table isn't big enough!"); 468 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> 469 (2*ToVT.getSimpleVT())) & 3); 470 } 471 472 /// isConvertLegal - Return true if the specified conversion is legal 473 /// on this target. 474 bool isConvertLegal(MVT FromVT, MVT ToVT) const { 475 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 476 (getConvertAction(FromVT, ToVT) == Legal || 477 getConvertAction(FromVT, ToVT) == Custom); 478 } 479 480 /// getCondCodeAction - Return how the condition code should be treated: 481 /// either it is legal, needs to be expanded to some other code sequence, 482 /// or the target has a custom expander for it. 483 LegalizeAction 484 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 485 assert((unsigned)CC < array_lengthof(CondCodeActions) && 486 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 487 "Table isn't big enough!"); 488 LegalizeAction Action = (LegalizeAction) 489 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3); 490 assert(Action != Promote && "Can't promote condition code!"); 491 return Action; 492 } 493 494 /// isCondCodeLegal - Return true if the specified condition code is legal 495 /// on this target. 496 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 497 return getCondCodeAction(CC, VT) == Legal || 498 getCondCodeAction(CC, VT) == Custom; 499 } 500 501 502 /// getTypeToPromoteTo - If the action for this operation is to promote, this 503 /// method returns the ValueType to promote to. 504 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 505 assert(getOperationAction(Op, VT) == Promote && 506 "This operation isn't promoted!"); 507 508 // See if this has an explicit type specified. 509 std::map<std::pair<unsigned, MVT::SimpleValueType>, 510 MVT::SimpleValueType>::const_iterator PTTI = 511 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); 512 if (PTTI != PromoteToType.end()) return PTTI->second; 513 514 assert((VT.isInteger() || VT.isFloatingPoint()) && 515 "Cannot autopromote this type, add it with AddPromotedToType."); 516 517 MVT NVT = VT; 518 do { 519 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); 520 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 521 "Didn't find type to promote to!"); 522 } while (!isTypeLegal(NVT) || 523 getOperationAction(Op, NVT) == Promote); 524 return NVT; 525 } 526 527 /// getValueType - Return the MVT corresponding to this LLVM type. 528 /// This is fixed by the LLVM operations except for the pointer size. If 529 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 530 /// counterpart (e.g. structs), otherwise it will assert. 531 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 532 MVT VT = MVT::getMVT(Ty, AllowUnknown); 533 return VT == MVT::iPTR ? PointerTy : VT; 534 } 535 536 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 537 /// function arguments in the caller parameter area. This is the actual 538 /// alignment, not its logarithm. 539 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 540 541 /// getRegisterType - Return the type of registers that this ValueType will 542 /// eventually require. 543 MVT getRegisterType(MVT VT) const { 544 if (VT.isSimple()) { 545 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); 546 return RegisterTypeForVT[VT.getSimpleVT()]; 547 } 548 if (VT.isVector()) { 549 MVT VT1, RegisterVT; 550 unsigned NumIntermediates; 551 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 552 return RegisterVT; 553 } 554 if (VT.isInteger()) { 555 return getRegisterType(getTypeToTransformTo(VT)); 556 } 557 assert(0 && "Unsupported extended type!"); 558 return MVT(MVT::Other); // Not reached 559 } 560 561 /// getNumRegisters - Return the number of registers that this ValueType will 562 /// eventually require. This is one for any types promoted to live in larger 563 /// registers, but may be more than one for types (like i64) that are split 564 /// into pieces. For types like i140, which are first promoted then expanded, 565 /// it is the number of registers needed to hold all the bits of the original 566 /// type. For an i140 on a 32 bit machine this means 5 registers. 567 unsigned getNumRegisters(MVT VT) const { 568 if (VT.isSimple()) { 569 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); 570 return NumRegistersForVT[VT.getSimpleVT()]; 571 } 572 if (VT.isVector()) { 573 MVT VT1, VT2; 574 unsigned NumIntermediates; 575 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 576 } 577 if (VT.isInteger()) { 578 unsigned BitWidth = VT.getSizeInBits(); 579 unsigned RegWidth = getRegisterType(VT).getSizeInBits(); 580 return (BitWidth + RegWidth - 1) / RegWidth; 581 } 582 assert(0 && "Unsupported extended type!"); 583 return 0; // Not reached 584 } 585 586 /// ShouldShrinkFPConstant - If true, then instruction selection should 587 /// seek to shrink the FP constant of the specified type to a smaller type 588 /// in order to save space and / or reduce runtime. 589 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } 590 591 /// hasTargetDAGCombine - If true, the target has custom DAG combine 592 /// transformations that it can perform for the specified node. 593 bool hasTargetDAGCombine(ISD::NodeType NT) const { 594 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 595 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 596 } 597 598 /// This function returns the maximum number of store operations permitted 599 /// to replace a call to llvm.memset. The value is set by the target at the 600 /// performance threshold for such a replacement. 601 /// @brief Get maximum # of store operations permitted for llvm.memset 602 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 603 604 /// This function returns the maximum number of store operations permitted 605 /// to replace a call to llvm.memcpy. The value is set by the target at the 606 /// performance threshold for such a replacement. 607 /// @brief Get maximum # of store operations permitted for llvm.memcpy 608 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 609 610 /// This function returns the maximum number of store operations permitted 611 /// to replace a call to llvm.memmove. The value is set by the target at the 612 /// performance threshold for such a replacement. 613 /// @brief Get maximum # of store operations permitted for llvm.memmove 614 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 615 616 /// This function returns true if the target allows unaligned memory accesses. 617 /// This is used, for example, in situations where an array copy/move/set is 618 /// converted to a sequence of store operations. It's use helps to ensure that 619 /// such replacements don't generate code that causes an alignment error 620 /// (trap) on the target machine. 621 /// @brief Determine if the target supports unaligned memory accesses. 622 bool allowsUnalignedMemoryAccesses() const { 623 return allowUnalignedMemoryAccesses; 624 } 625 626 /// This function returns true if the target would benefit from code placement 627 /// optimization. 628 /// @brief Determine if the target should perform code placement optimization. 629 bool shouldOptimizeCodePlacement() const { 630 return benefitFromCodePlacementOpt; 631 } 632 633 /// getOptimalMemOpType - Returns the target specific optimal type for load 634 /// and store operations as a result of memset, memcpy, and memmove lowering. 635 /// It returns MVT::iAny if SelectionDAG should be responsible for 636 /// determining it. 637 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, 638 bool isSrcConst, bool isSrcStr, 639 SelectionDAG &DAG) const { 640 return MVT::iAny; 641 } 642 643 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 644 /// to implement llvm.setjmp. 645 bool usesUnderscoreSetJmp() const { 646 return UseUnderscoreSetJmp; 647 } 648 649 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 650 /// to implement llvm.longjmp. 651 bool usesUnderscoreLongJmp() const { 652 return UseUnderscoreLongJmp; 653 } 654 655 /// getStackPointerRegisterToSaveRestore - If a physical register, this 656 /// specifies the register that llvm.savestack/llvm.restorestack should save 657 /// and restore. 658 unsigned getStackPointerRegisterToSaveRestore() const { 659 return StackPointerRegisterToSaveRestore; 660 } 661 662 /// getExceptionAddressRegister - If a physical register, this returns 663 /// the register that receives the exception address on entry to a landing 664 /// pad. 665 unsigned getExceptionAddressRegister() const { 666 return ExceptionPointerRegister; 667 } 668 669 /// getExceptionSelectorRegister - If a physical register, this returns 670 /// the register that receives the exception typeid on entry to a landing 671 /// pad. 672 unsigned getExceptionSelectorRegister() const { 673 return ExceptionSelectorRegister; 674 } 675 676 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 677 /// set, the default is 200) 678 unsigned getJumpBufSize() const { 679 return JumpBufSize; 680 } 681 682 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 683 /// (if never set, the default is 0) 684 unsigned getJumpBufAlignment() const { 685 return JumpBufAlignment; 686 } 687 688 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 689 /// limit. Any block whose size is greater should not be predicated. 690 unsigned getIfCvtBlockSizeLimit() const { 691 return IfCvtBlockSizeLimit; 692 } 693 694 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 695 /// block to be considered for duplication. Any block whose size is greater 696 /// should not be duplicated to facilitate its predication. 697 unsigned getIfCvtDupBlockSizeLimit() const { 698 return IfCvtDupBlockSizeLimit; 699 } 700 701 /// getPrefLoopAlignment - return the preferred loop alignment. 702 /// 703 unsigned getPrefLoopAlignment() const { 704 return PrefLoopAlignment; 705 } 706 707 /// getPreIndexedAddressParts - returns true by value, base pointer and 708 /// offset pointer and addressing mode by reference if the node's address 709 /// can be legally represented as pre-indexed load / store address. 710 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 711 SDValue &Offset, 712 ISD::MemIndexedMode &AM, 713 SelectionDAG &DAG) const { 714 return false; 715 } 716 717 /// getPostIndexedAddressParts - returns true by value, base pointer and 718 /// offset pointer and addressing mode by reference if this node can be 719 /// combined with a load / store to form a post-indexed load / store. 720 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 721 SDValue &Base, SDValue &Offset, 722 ISD::MemIndexedMode &AM, 723 SelectionDAG &DAG) const { 724 return false; 725 } 726 727 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 728 /// jumptable. 729 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 730 SelectionDAG &DAG) const; 731 732 /// isOffsetFoldingLegal - Return true if folding a constant offset 733 /// with the given GlobalAddress is legal. It is frequently not legal in 734 /// PIC relocation models. 735 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 736 737 /// getFunctionAlignment - Return the Log2 alignment of this function. 738 virtual unsigned getFunctionAlignment(const Function *) const = 0; 739 740 //===--------------------------------------------------------------------===// 741 // TargetLowering Optimization Methods 742 // 743 744 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 745 /// SDValues for returning information from TargetLowering to its clients 746 /// that want to combine 747 struct TargetLoweringOpt { 748 SelectionDAG &DAG; 749 SDValue Old; 750 SDValue New; 751 752 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 753 754 bool CombineTo(SDValue O, SDValue N) { 755 Old = O; 756 New = N; 757 return true; 758 } 759 760 /// ShrinkDemandedConstant - Check to see if the specified operand of the 761 /// specified instruction is a constant integer. If so, check to see if 762 /// there are any bits set in the constant that are not demanded. If so, 763 /// shrink the constant and return true. 764 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 765 766 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 767 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 768 /// cast, but it could be generalized for targets with other types of 769 /// implicit widening casts. 770 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 771 DebugLoc dl); 772 }; 773 774 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 775 /// DemandedMask bits of the result of Op are ever used downstream. If we can 776 /// use this information to simplify Op, create a new simplified DAG node and 777 /// return true, returning the original and new nodes in Old and New. 778 /// Otherwise, analyze the expression and return a mask of KnownOne and 779 /// KnownZero bits for the expression (used to simplify the caller). 780 /// The KnownZero/One bits may only be accurate for those bits in the 781 /// DemandedMask. 782 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 783 APInt &KnownZero, APInt &KnownOne, 784 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 785 786 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 787 /// Mask are known to be either zero or one and return them in the 788 /// KnownZero/KnownOne bitsets. 789 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 790 const APInt &Mask, 791 APInt &KnownZero, 792 APInt &KnownOne, 793 const SelectionDAG &DAG, 794 unsigned Depth = 0) const; 795 796 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 797 /// targets that want to expose additional information about sign bits to the 798 /// DAG Combiner. 799 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 800 unsigned Depth = 0) const; 801 802 struct DAGCombinerInfo { 803 void *DC; // The DAG Combiner object. 804 bool BeforeLegalize; 805 bool BeforeLegalizeOps; 806 bool CalledByLegalizer; 807 public: 808 SelectionDAG &DAG; 809 810 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 811 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 812 CalledByLegalizer(cl), DAG(dag) {} 813 814 bool isBeforeLegalize() const { return BeforeLegalize; } 815 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 816 bool isCalledByLegalizer() const { return CalledByLegalizer; } 817 818 void AddToWorklist(SDNode *N); 819 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 820 bool AddTo = true); 821 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 822 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 823 824 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 825 }; 826 827 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 828 /// and cc. If it is unable to simplify it, return a null SDValue. 829 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 830 ISD::CondCode Cond, bool foldBooleans, 831 DAGCombinerInfo &DCI, DebugLoc dl) const; 832 833 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 834 /// node is a GlobalAddress + offset. 835 virtual bool 836 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 837 838 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 839 /// location that is 'Dist' units away from the location that the 'Base' load 840 /// is loading from. 841 bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, 842 int Dist, const MachineFrameInfo *MFI) const; 843 844 /// PerformDAGCombine - This method will be invoked for all target nodes and 845 /// for any target-independent nodes that the target has registered with 846 /// invoke it for. 847 /// 848 /// The semantics are as follows: 849 /// Return Value: 850 /// SDValue.Val == 0 - No change was made 851 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 852 /// otherwise - N should be replaced by the returned Operand. 853 /// 854 /// In addition, methods provided by DAGCombinerInfo may be used to perform 855 /// more complex transformations. 856 /// 857 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 858 859 //===--------------------------------------------------------------------===// 860 // TargetLowering Configuration Methods - These methods should be invoked by 861 // the derived class constructor to configure this object for the target. 862 // 863 864protected: 865 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 866 /// GOT for PC-relative code. 867 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 868 869 /// setShiftAmountType - Describe the type that should be used for shift 870 /// amounts. This type defaults to the pointer type. 871 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 872 873 /// setBooleanContents - Specify how the target extends the result of a 874 /// boolean value from i1 to a wider type. See getBooleanContents. 875 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 876 877 /// setSchedulingPreference - Specify the target scheduling preference. 878 void setSchedulingPreference(SchedPreference Pref) { 879 SchedPreferenceInfo = Pref; 880 } 881 882 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 883 /// use _setjmp to implement llvm.setjmp or the non _ version. 884 /// Defaults to false. 885 void setUseUnderscoreSetJmp(bool Val) { 886 UseUnderscoreSetJmp = Val; 887 } 888 889 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 890 /// use _longjmp to implement llvm.longjmp or the non _ version. 891 /// Defaults to false. 892 void setUseUnderscoreLongJmp(bool Val) { 893 UseUnderscoreLongJmp = Val; 894 } 895 896 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 897 /// specifies the register that llvm.savestack/llvm.restorestack should save 898 /// and restore. 899 void setStackPointerRegisterToSaveRestore(unsigned R) { 900 StackPointerRegisterToSaveRestore = R; 901 } 902 903 /// setExceptionPointerRegister - If set to a physical register, this sets 904 /// the register that receives the exception address on entry to a landing 905 /// pad. 906 void setExceptionPointerRegister(unsigned R) { 907 ExceptionPointerRegister = R; 908 } 909 910 /// setExceptionSelectorRegister - If set to a physical register, this sets 911 /// the register that receives the exception typeid on entry to a landing 912 /// pad. 913 void setExceptionSelectorRegister(unsigned R) { 914 ExceptionSelectorRegister = R; 915 } 916 917 /// SelectIsExpensive - Tells the code generator not to expand operations 918 /// into sequences that use the select operations if possible. 919 void setSelectIsExpensive() { SelectIsExpensive = true; } 920 921 /// setIntDivIsCheap - Tells the code generator that integer divide is 922 /// expensive, and if possible, should be replaced by an alternate sequence 923 /// of instructions not containing an integer divide. 924 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 925 926 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 927 /// srl/add/sra for a signed divide by power of two, and let the target handle 928 /// it. 929 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 930 931 /// addRegisterClass - Add the specified register class as an available 932 /// regclass for the specified value type. This indicates the selector can 933 /// handle values of that class natively. 934 void addRegisterClass(MVT VT, TargetRegisterClass *RC) { 935 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 936 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 937 RegClassForVT[VT.getSimpleVT()] = RC; 938 } 939 940 /// computeRegisterProperties - Once all of the register classes are added, 941 /// this allows us to compute derived properties we expose. 942 void computeRegisterProperties(); 943 944 /// setOperationAction - Indicate that the specified operation does not work 945 /// with the specified type and indicate what to do about it. 946 void setOperationAction(unsigned Op, MVT VT, 947 LegalizeAction Action) { 948 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 && 949 Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 950 unsigned I = (unsigned) VT.getSimpleVT(); 951 unsigned J = I & 31; 952 I = I >> 5; 953 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2)); 954 OpActions[I][Op] |= (uint64_t)Action << (J*2); 955 } 956 957 /// setLoadExtAction - Indicate that the specified load with extension does 958 /// not work with the with specified type and indicate what to do about it. 959 void setLoadExtAction(unsigned ExtType, MVT VT, 960 LegalizeAction Action) { 961 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 962 ExtType < array_lengthof(LoadExtActions) && 963 "Table isn't big enough!"); 964 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 965 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2; 966 } 967 968 /// setTruncStoreAction - Indicate that the specified truncating store does 969 /// not work with the with specified type and indicate what to do about it. 970 void setTruncStoreAction(MVT ValVT, MVT MemVT, 971 LegalizeAction Action) { 972 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 973 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 974 "Table isn't big enough!"); 975 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) << 976 MemVT.getSimpleVT()*2); 977 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action << 978 MemVT.getSimpleVT()*2; 979 } 980 981 /// setIndexedLoadAction - Indicate that the specified indexed load does or 982 /// does not work with the with specified type and indicate what to do abort 983 /// it. NOTE: All indexed mode loads are initialized to Expand in 984 /// TargetLowering.cpp 985 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 986 LegalizeAction Action) { 987 assert((unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE && 988 IdxMode < array_lengthof(IndexedModeActions[0][0]) && 989 "Table isn't big enough!"); 990 IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode] = (uint8_t)Action; 991 } 992 993 /// setIndexedStoreAction - Indicate that the specified indexed store does or 994 /// does not work with the with specified type and indicate what to do about 995 /// it. NOTE: All indexed mode stores are initialized to Expand in 996 /// TargetLowering.cpp 997 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 998 LegalizeAction Action) { 999 assert((unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE && 1000 IdxMode < array_lengthof(IndexedModeActions[0][1] ) && 1001 "Table isn't big enough!"); 1002 IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode] = (uint8_t)Action; 1003 } 1004 1005 /// setConvertAction - Indicate that the specified conversion does or does 1006 /// not work with the with specified type and indicate what to do about it. 1007 void setConvertAction(MVT FromVT, MVT ToVT, 1008 LegalizeAction Action) { 1009 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 1010 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 1011 "Table isn't big enough!"); 1012 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) << 1013 ToVT.getSimpleVT()*2); 1014 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action << 1015 ToVT.getSimpleVT()*2; 1016 } 1017 1018 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1019 /// supported on the target and indicate what to do about it. 1020 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { 1021 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 1022 (unsigned)CC < array_lengthof(CondCodeActions) && 1023 "Table isn't big enough!"); 1024 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 1025 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2; 1026 } 1027 1028 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1029 /// promotion code defaults to trying a larger integer/fp until it can find 1030 /// one that works. If that default is insufficient, this method can be used 1031 /// by the target to override the default. 1032 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1033 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] = 1034 DestVT.getSimpleVT(); 1035 } 1036 1037 /// addLegalFPImmediate - Indicate that this target can instruction select 1038 /// the specified FP immediate natively. 1039 void addLegalFPImmediate(const APFloat& Imm) { 1040 LegalFPImmediates.push_back(Imm); 1041 } 1042 1043 /// setTargetDAGCombine - Targets should invoke this method for each target 1044 /// independent node that they want to provide a custom DAG combiner for by 1045 /// implementing the PerformDAGCombine virtual method. 1046 void setTargetDAGCombine(ISD::NodeType NT) { 1047 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1048 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1049 } 1050 1051 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1052 /// bytes); default is 200 1053 void setJumpBufSize(unsigned Size) { 1054 JumpBufSize = Size; 1055 } 1056 1057 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1058 /// alignment (in bytes); default is 0 1059 void setJumpBufAlignment(unsigned Align) { 1060 JumpBufAlignment = Align; 1061 } 1062 1063 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1064 /// limit (in number of instructions); default is 2. 1065 void setIfCvtBlockSizeLimit(unsigned Limit) { 1066 IfCvtBlockSizeLimit = Limit; 1067 } 1068 1069 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1070 /// of instructions) to be considered for code duplication during 1071 /// if-conversion; default is 2. 1072 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1073 IfCvtDupBlockSizeLimit = Limit; 1074 } 1075 1076 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1077 /// alignment is zero, it means the target does not care about loop alignment. 1078 void setPrefLoopAlignment(unsigned Align) { 1079 PrefLoopAlignment = Align; 1080 } 1081 1082public: 1083 1084 virtual const TargetSubtarget *getSubtarget() { 1085 assert(0 && "Not Implemented"); 1086 return NULL; // this is here to silence compiler errors 1087 } 1088 1089 //===--------------------------------------------------------------------===// 1090 // Lowering methods - These methods must be implemented by targets so that 1091 // the SelectionDAGLowering code knows how to lower these. 1092 // 1093 1094 /// LowerArguments - This hook must be implemented to indicate how we should 1095 /// lower the arguments for the specified function, into the specified DAG. 1096 virtual void 1097 LowerArguments(Function &F, SelectionDAG &DAG, 1098 SmallVectorImpl<SDValue>& ArgValues, DebugLoc dl); 1099 1100 /// LowerCallTo - This hook lowers an abstract call to a function into an 1101 /// actual call. This returns a pair of operands. The first element is the 1102 /// return value for the function (if RetTy is not VoidTy). The second 1103 /// element is the outgoing token chain. 1104 struct ArgListEntry { 1105 SDValue Node; 1106 const Type* Ty; 1107 bool isSExt : 1; 1108 bool isZExt : 1; 1109 bool isInReg : 1; 1110 bool isSRet : 1; 1111 bool isNest : 1; 1112 bool isByVal : 1; 1113 uint16_t Alignment; 1114 1115 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1116 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1117 }; 1118 typedef std::vector<ArgListEntry> ArgListTy; 1119 virtual std::pair<SDValue, SDValue> 1120 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1121 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1122 unsigned CallingConv, bool isTailCall, SDValue Callee, 1123 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl); 1124 1125 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1126 /// memcpy. This can be used by targets to provide code sequences for cases 1127 /// that don't fit the target's parameters for simple loads/stores and can be 1128 /// more efficient than using a library call. This function can return a null 1129 /// SDValue if the target declines to use custom code and a different 1130 /// lowering strategy should be used. 1131 /// 1132 /// If AlwaysInline is true, the size is constant and the target should not 1133 /// emit any calls and is strongly encouraged to attempt to emit inline code 1134 /// even if it is beyond the usual threshold because this intrinsic is being 1135 /// expanded in a place where calls are not feasible (e.g. within the prologue 1136 /// for another call). If the target chooses to decline an AlwaysInline 1137 /// request here, legalize will resort to using simple loads and stores. 1138 virtual SDValue 1139 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1140 SDValue Chain, 1141 SDValue Op1, SDValue Op2, 1142 SDValue Op3, unsigned Align, 1143 bool AlwaysInline, 1144 const Value *DstSV, uint64_t DstOff, 1145 const Value *SrcSV, uint64_t SrcOff) { 1146 return SDValue(); 1147 } 1148 1149 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1150 /// memmove. This can be used by targets to provide code sequences for cases 1151 /// that don't fit the target's parameters for simple loads/stores and can be 1152 /// more efficient than using a library call. This function can return a null 1153 /// SDValue if the target declines to use custom code and a different 1154 /// lowering strategy should be used. 1155 virtual SDValue 1156 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1157 SDValue Chain, 1158 SDValue Op1, SDValue Op2, 1159 SDValue Op3, unsigned Align, 1160 const Value *DstSV, uint64_t DstOff, 1161 const Value *SrcSV, uint64_t SrcOff) { 1162 return SDValue(); 1163 } 1164 1165 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1166 /// memset. This can be used by targets to provide code sequences for cases 1167 /// that don't fit the target's parameters for simple stores and can be more 1168 /// efficient than using a library call. This function can return a null 1169 /// SDValue if the target declines to use custom code and a different 1170 /// lowering strategy should be used. 1171 virtual SDValue 1172 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1173 SDValue Chain, 1174 SDValue Op1, SDValue Op2, 1175 SDValue Op3, unsigned Align, 1176 const Value *DstSV, uint64_t DstOff) { 1177 return SDValue(); 1178 } 1179 1180 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1181 /// to legalize nodes with an illegal operand type but legal result types. 1182 /// It replaces the LowerOperation callback in the type Legalizer. 1183 /// The reason we can not do away with LowerOperation entirely is that 1184 /// LegalizeDAG isn't yet ready to use this callback. 1185 /// TODO: Consider merging with ReplaceNodeResults. 1186 1187 /// The target places new result values for the node in Results (their number 1188 /// and types must exactly match those of the original return values of 1189 /// the node), or leaves Results empty, which indicates that the node is not 1190 /// to be custom lowered after all. 1191 /// The default implementation calls LowerOperation. 1192 virtual void LowerOperationWrapper(SDNode *N, 1193 SmallVectorImpl<SDValue> &Results, 1194 SelectionDAG &DAG); 1195 1196 /// LowerOperation - This callback is invoked for operations that are 1197 /// unsupported by the target, which are registered to use 'custom' lowering, 1198 /// and whose defined values are all legal. 1199 /// If the target has no operations that require custom lowering, it need not 1200 /// implement this. The default implementation of this aborts. 1201 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1202 1203 /// ReplaceNodeResults - This callback is invoked when a node result type is 1204 /// illegal for the target, and the operation was registered to use 'custom' 1205 /// lowering for that result type. The target places new result values for 1206 /// the node in Results (their number and types must exactly match those of 1207 /// the original return values of the node), or leaves Results empty, which 1208 /// indicates that the node is not to be custom lowered after all. 1209 /// 1210 /// If the target has no operations that require custom lowering, it need not 1211 /// implement this. The default implementation aborts. 1212 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1213 SelectionDAG &DAG) { 1214 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1215 } 1216 1217 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1218 /// tail call optimization. Targets which want to do tail call optimization 1219 /// should override this function. 1220 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call, 1221 SDValue Ret, 1222 SelectionDAG &DAG) const { 1223 return false; 1224 } 1225 1226 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly 1227 /// preceeds the RET node and whether the return uses the result of the node 1228 /// or is a void return. This function can be used by the target to determine 1229 /// eligiblity of tail call optimization. 1230 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret); 1231 1232 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1233 /// it exists. Skip a possible ISD::TokenFactor. 1234 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1235 unsigned TailCallNodeOpCode) { 1236 if (Chain.getOpcode() == TailCallNodeOpCode) { 1237 return Chain; 1238 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1239 if (Chain.getNumOperands() && 1240 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1241 return Chain.getOperand(0); 1242 } 1243 return Chain; 1244 } 1245 1246 /// getTargetNodeName() - This method returns the name of a target specific 1247 /// DAG node. 1248 virtual const char *getTargetNodeName(unsigned Opcode) const; 1249 1250 /// createFastISel - This method returns a target specific FastISel object, 1251 /// or null if the target does not support "fast" ISel. 1252 virtual FastISel * 1253 createFastISel(MachineFunction &, 1254 MachineModuleInfo *, DwarfWriter *, 1255 DenseMap<const Value *, unsigned> &, 1256 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1257 DenseMap<const AllocaInst *, int> & 1258#ifndef NDEBUG 1259 , SmallSet<Instruction*, 8> &CatchInfoLost 1260#endif 1261 ) { 1262 return 0; 1263 } 1264 1265 //===--------------------------------------------------------------------===// 1266 // Inline Asm Support hooks 1267 // 1268 1269 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1270 /// call to be explicit llvm code if it wants to. This is useful for 1271 /// turning simple inline asms into LLVM intrinsics, which gives the 1272 /// compiler more information about the behavior of the code. 1273 virtual bool ExpandInlineAsm(CallInst *CI) const { 1274 return false; 1275 } 1276 1277 enum ConstraintType { 1278 C_Register, // Constraint represents specific register(s). 1279 C_RegisterClass, // Constraint represents any of register(s) in class. 1280 C_Memory, // Memory constraint. 1281 C_Other, // Something else. 1282 C_Unknown // Unsupported constraint. 1283 }; 1284 1285 /// AsmOperandInfo - This contains information for each constraint that we are 1286 /// lowering. 1287 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1288 /// ConstraintCode - This contains the actual string for the code, like "m". 1289 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1290 /// most closely matches the operand. 1291 std::string ConstraintCode; 1292 1293 /// ConstraintType - Information about the constraint code, e.g. Register, 1294 /// RegisterClass, Memory, Other, Unknown. 1295 TargetLowering::ConstraintType ConstraintType; 1296 1297 /// CallOperandval - If this is the result output operand or a 1298 /// clobber, this is null, otherwise it is the incoming operand to the 1299 /// CallInst. This gets modified as the asm is processed. 1300 Value *CallOperandVal; 1301 1302 /// ConstraintVT - The ValueType for the operand value. 1303 MVT ConstraintVT; 1304 1305 /// isMatchingInputConstraint - Return true of this is an input operand that 1306 /// is a matching constraint like "4". 1307 bool isMatchingInputConstraint() const; 1308 1309 /// getMatchedOperand - If this is an input matching constraint, this method 1310 /// returns the output operand it matches. 1311 unsigned getMatchedOperand() const; 1312 1313 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1314 : InlineAsm::ConstraintInfo(info), 1315 ConstraintType(TargetLowering::C_Unknown), 1316 CallOperandVal(0), ConstraintVT(MVT::Other) { 1317 } 1318 }; 1319 1320 /// ComputeConstraintToUse - Determines the constraint code and constraint 1321 /// type to use for the specific AsmOperandInfo, setting 1322 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1323 /// being passed in is available, it can be passed in as Op, otherwise an 1324 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1325 /// constraint of the inline asm instruction being processed is 'm'. 1326 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1327 SDValue Op, 1328 bool hasMemory, 1329 SelectionDAG *DAG = 0) const; 1330 1331 /// getConstraintType - Given a constraint, return the type of constraint it 1332 /// is for this target. 1333 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1334 1335 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1336 /// return a list of registers that can be used to satisfy the constraint. 1337 /// This should only be used for C_RegisterClass constraints. 1338 virtual std::vector<unsigned> 1339 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1340 MVT VT) const; 1341 1342 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1343 /// {edx}), return the register number and the register class for the 1344 /// register. 1345 /// 1346 /// Given a register class constraint, like 'r', if this corresponds directly 1347 /// to an LLVM register class, return a register of 0 and the register class 1348 /// pointer. 1349 /// 1350 /// This should only be used for C_Register constraints. On error, 1351 /// this returns a register number of 0 and a null register class pointer.. 1352 virtual std::pair<unsigned, const TargetRegisterClass*> 1353 getRegForInlineAsmConstraint(const std::string &Constraint, 1354 MVT VT) const; 1355 1356 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1357 /// with another that has more specific requirements based on the type of the 1358 /// corresponding operand. This returns null if there is no replacement to 1359 /// make. 1360 virtual const char *LowerXConstraint(MVT ConstraintVT) const; 1361 1362 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1363 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1364 /// it means one of the asm constraint of the inline asm instruction being 1365 /// processed is 'm'. 1366 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1367 bool hasMemory, 1368 std::vector<SDValue> &Ops, 1369 SelectionDAG &DAG) const; 1370 1371 //===--------------------------------------------------------------------===// 1372 // Scheduler hooks 1373 // 1374 1375 // EmitInstrWithCustomInserter - This method should be implemented by targets 1376 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1377 // instructions are special in various ways, which require special support to 1378 // insert. The specified MachineInstr is created but not inserted into any 1379 // basic blocks, and the scheduler passes ownership of it to this method. 1380 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1381 MachineBasicBlock *MBB) const; 1382 1383 //===--------------------------------------------------------------------===// 1384 // Addressing mode description hooks (used by LSR etc). 1385 // 1386 1387 /// AddrMode - This represents an addressing mode of: 1388 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1389 /// If BaseGV is null, there is no BaseGV. 1390 /// If BaseOffs is zero, there is no base offset. 1391 /// If HasBaseReg is false, there is no base register. 1392 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1393 /// no scale. 1394 /// 1395 struct AddrMode { 1396 GlobalValue *BaseGV; 1397 int64_t BaseOffs; 1398 bool HasBaseReg; 1399 int64_t Scale; 1400 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1401 }; 1402 1403 /// isLegalAddressingMode - Return true if the addressing mode represented by 1404 /// AM is legal for this target, for a load/store of the specified type. 1405 /// The type may be VoidTy, in which case only return true if the addressing 1406 /// mode is legal for a load/store of any legal type. 1407 /// TODO: Handle pre/postinc as well. 1408 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1409 1410 /// isTruncateFree - Return true if it's free to truncate a value of 1411 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1412 /// register EAX to i16 by referencing its sub-register AX. 1413 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1414 return false; 1415 } 1416 1417 virtual bool isTruncateFree(MVT VT1, MVT VT2) const { 1418 return false; 1419 } 1420 1421 /// isZExtFree - Return true if any actual instruction that defines a 1422 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 1423 /// register. This does not necessarily include registers defined in 1424 /// unknown ways, such as incoming arguments, or copies from unknown 1425 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1426 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1427 /// all instructions that define 32-bit values implicit zero-extend the 1428 /// result out to 64 bits. 1429 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1430 return false; 1431 } 1432 1433 virtual bool isZExtFree(MVT VT1, MVT VT2) const { 1434 return false; 1435 } 1436 1437 /// isNarrowingProfitable - Return true if it's profitable to narrow 1438 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1439 /// from i32 to i8 but not from i32 to i16. 1440 virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const { 1441 return false; 1442 } 1443 1444 //===--------------------------------------------------------------------===// 1445 // Div utility functions 1446 // 1447 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1448 std::vector<SDNode*>* Created) const; 1449 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1450 std::vector<SDNode*>* Created) const; 1451 1452 1453 //===--------------------------------------------------------------------===// 1454 // Runtime Library hooks 1455 // 1456 1457 /// setLibcallName - Rename the default libcall routine name for the specified 1458 /// libcall. 1459 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1460 LibcallRoutineNames[Call] = Name; 1461 } 1462 1463 /// getLibcallName - Get the libcall routine name for the specified libcall. 1464 /// 1465 const char *getLibcallName(RTLIB::Libcall Call) const { 1466 return LibcallRoutineNames[Call]; 1467 } 1468 1469 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1470 /// result of the comparison libcall against zero. 1471 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1472 CmpLibcallCCs[Call] = CC; 1473 } 1474 1475 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1476 /// the comparison libcall against zero. 1477 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1478 return CmpLibcallCCs[Call]; 1479 } 1480 1481private: 1482 TargetMachine &TM; 1483 const TargetData *TD; 1484 TargetLoweringObjectFile &TLOF; 1485 1486 /// PointerTy - The type to use for pointers, usually i32 or i64. 1487 /// 1488 MVT PointerTy; 1489 1490 /// IsLittleEndian - True if this is a little endian target. 1491 /// 1492 bool IsLittleEndian; 1493 1494 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1495 /// 1496 bool UsesGlobalOffsetTable; 1497 1498 /// SelectIsExpensive - Tells the code generator not to expand operations 1499 /// into sequences that use the select operations if possible. 1500 bool SelectIsExpensive; 1501 1502 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1503 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1504 /// a real cost model is in place. If we ever optimize for size, this will be 1505 /// set to true unconditionally. 1506 bool IntDivIsCheap; 1507 1508 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1509 /// srl/add/sra for a signed divide by power of two, and let the target handle 1510 /// it. 1511 bool Pow2DivIsCheap; 1512 1513 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1514 /// llvm.setjmp. Defaults to false. 1515 bool UseUnderscoreSetJmp; 1516 1517 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1518 /// llvm.longjmp. Defaults to false. 1519 bool UseUnderscoreLongJmp; 1520 1521 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1522 /// PointerTy is. 1523 MVT ShiftAmountTy; 1524 1525 /// BooleanContents - Information about the contents of the high-bits in 1526 /// boolean values held in a type wider than i1. See getBooleanContents. 1527 BooleanContent BooleanContents; 1528 1529 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1530 /// total cycles or lowest register usage. 1531 SchedPreference SchedPreferenceInfo; 1532 1533 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1534 unsigned JumpBufSize; 1535 1536 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1537 /// buffers 1538 unsigned JumpBufAlignment; 1539 1540 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1541 /// if-converted. 1542 unsigned IfCvtBlockSizeLimit; 1543 1544 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1545 /// duplicated during if-conversion. 1546 unsigned IfCvtDupBlockSizeLimit; 1547 1548 /// PrefLoopAlignment - The perferred loop alignment. 1549 /// 1550 unsigned PrefLoopAlignment; 1551 1552 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1553 /// specifies the register that llvm.savestack/llvm.restorestack should save 1554 /// and restore. 1555 unsigned StackPointerRegisterToSaveRestore; 1556 1557 /// ExceptionPointerRegister - If set to a physical register, this specifies 1558 /// the register that receives the exception address on entry to a landing 1559 /// pad. 1560 unsigned ExceptionPointerRegister; 1561 1562 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1563 /// the register that receives the exception typeid on entry to a landing 1564 /// pad. 1565 unsigned ExceptionSelectorRegister; 1566 1567 /// RegClassForVT - This indicates the default register class to use for 1568 /// each ValueType the target supports natively. 1569 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1570 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1571 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1572 1573 /// TransformToType - For any value types we are promoting or expanding, this 1574 /// contains the value type that we are changing to. For Expanded types, this 1575 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1576 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1577 /// by the system, this holds the same type (e.g. i32 -> i32). 1578 MVT TransformToType[MVT::LAST_VALUETYPE]; 1579 1580 /// OpActions - For each operation and each value type, keep a LegalizeAction 1581 /// that indicates how instruction selection should deal with the operation. 1582 /// Most operations are Legal (aka, supported natively by the target), but 1583 /// operations that are not should be described. Note that operations on 1584 /// non-legal value types are not described here. 1585 /// This array is accessed using VT.getSimpleVT(), so it is subject to 1586 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits. 1587 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END]; 1588 1589 /// LoadExtActions - For each load of load extension type and each value type, 1590 /// keep a LegalizeAction that indicates how instruction selection should deal 1591 /// with the load. 1592 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1593 1594 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1595 /// indicates how instruction selection should deal with the store. 1596 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1597 1598 /// IndexedModeActions - For each indexed mode and each value type, 1599 /// keep a pair of LegalizeAction that indicates how instruction 1600 /// selection should deal with the load / store. The first 1601 /// dimension is now the value_type for the reference. The second 1602 /// dimension is the load [0] vs. store[1]. The third dimension 1603 /// represents the various modes for load store. 1604 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE]; 1605 1606 /// ConvertActions - For each conversion from source type to destination type, 1607 /// keep a LegalizeAction that indicates how instruction selection should 1608 /// deal with the conversion. 1609 /// Currently, this is used only for floating->floating conversions 1610 /// (FP_EXTEND and FP_ROUND). 1611 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1612 1613 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1614 /// LegalizeAction that indicates how instruction selection should 1615 /// deal with the condition code. 1616 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1617 1618 ValueTypeActionImpl ValueTypeActions; 1619 1620 std::vector<APFloat> LegalFPImmediates; 1621 1622 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses; 1623 1624 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1625 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1626 /// which sets a bit in this array. 1627 unsigned char 1628 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1629 1630 /// PromoteToType - For operations that must be promoted to a specific type, 1631 /// this holds the destination type. This map should be sparse, so don't hold 1632 /// it as an array. 1633 /// 1634 /// Targets add entries to this map with AddPromotedToType(..), clients access 1635 /// this with getTypeToPromoteTo(..). 1636 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1637 PromoteToType; 1638 1639 /// LibcallRoutineNames - Stores the name each libcall. 1640 /// 1641 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1642 1643 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1644 /// of each of the comparison libcall against zero. 1645 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1646 1647protected: 1648 /// When lowering \@llvm.memset this field specifies the maximum number of 1649 /// store operations that may be substituted for the call to memset. Targets 1650 /// must set this value based on the cost threshold for that target. Targets 1651 /// should assume that the memset will be done using as many of the largest 1652 /// store operations first, followed by smaller ones, if necessary, per 1653 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1654 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1655 /// store. This only applies to setting a constant array of a constant size. 1656 /// @brief Specify maximum number of store instructions per memset call. 1657 unsigned maxStoresPerMemset; 1658 1659 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1660 /// store operations that may be substituted for a call to memcpy. Targets 1661 /// must set this value based on the cost threshold for that target. Targets 1662 /// should assume that the memcpy will be done using as many of the largest 1663 /// store operations first, followed by smaller ones, if necessary, per 1664 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1665 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1666 /// and one 1-byte store. This only applies to copying a constant array of 1667 /// constant size. 1668 /// @brief Specify maximum bytes of store instructions per memcpy call. 1669 unsigned maxStoresPerMemcpy; 1670 1671 /// When lowering \@llvm.memmove this field specifies the maximum number of 1672 /// store instructions that may be substituted for a call to memmove. Targets 1673 /// must set this value based on the cost threshold for that target. Targets 1674 /// should assume that the memmove will be done using as many of the largest 1675 /// store operations first, followed by smaller ones, if necessary, per 1676 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1677 /// with 8-bit alignment would result in nine 1-byte stores. This only 1678 /// applies to copying a constant array of constant size. 1679 /// @brief Specify maximum bytes of store instructions per memmove call. 1680 unsigned maxStoresPerMemmove; 1681 1682 /// This field specifies whether the target machine permits unaligned memory 1683 /// accesses. This is used, for example, to determine the size of store 1684 /// operations when copying small arrays and other similar tasks. 1685 /// @brief Indicate whether the target permits unaligned memory accesses. 1686 bool allowUnalignedMemoryAccesses; 1687 1688 /// This field specifies whether the target can benefit from code placement 1689 /// optimization. 1690 bool benefitFromCodePlacementOpt; 1691}; 1692} // end llvm namespace 1693 1694#endif 1695