TargetLowering.h revision f7a0c7bf8bc8318ed28d889c9a56437ab3e91385
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/CodeGen/SelectionDAGNodes.h" 28#include "llvm/CodeGen/RuntimeLibcalls.h" 29#include "llvm/ADT/APFloat.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallSet.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/STLExtras.h" 34#include "llvm/Support/DebugLoc.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class AllocaInst; 42 class CallInst; 43 class Function; 44 class FastISel; 45 class MachineBasicBlock; 46 class MachineFunction; 47 class MachineFrameInfo; 48 class MachineInstr; 49 class MachineJumpTableInfo; 50 class MCContext; 51 class MCExpr; 52 class SDNode; 53 class SDValue; 54 class SelectionDAG; 55 class TargetData; 56 class TargetMachine; 57 class TargetRegisterClass; 58 class TargetLoweringObjectFile; 59 class Value; 60 61 // FIXME: should this be here? 62 namespace TLSModel { 63 enum Model { 64 GeneralDynamic, 65 LocalDynamic, 66 InitialExec, 67 LocalExec 68 }; 69 } 70 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 71 72 73//===----------------------------------------------------------------------===// 74/// TargetLowering - This class defines information used to lower LLVM code to 75/// legal SelectionDAG operators that the target instruction selector can accept 76/// natively. 77/// 78/// This class also defines callbacks that targets must implement to lower 79/// target-specific constructs to SelectionDAG operators. 80/// 81class TargetLowering { 82 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 83 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 84public: 85 /// LegalizeAction - This enum indicates whether operations are valid for a 86 /// target, and if not, what action should be used to make them valid. 87 enum LegalizeAction { 88 Legal, // The target natively supports this operation. 89 Promote, // This operation should be executed in a larger type. 90 Expand, // Try to expand this to other ops, otherwise use a libcall. 91 Custom // Use the LowerOperation hook to implement custom lowering. 92 }; 93 94 enum BooleanContent { // How the target represents true/false values. 95 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 96 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 97 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 98 }; 99 100 /// NOTE: The constructor takes ownership of TLOF. 101 explicit TargetLowering(const TargetMachine &TM, 102 const TargetLoweringObjectFile *TLOF); 103 virtual ~TargetLowering(); 104 105 const TargetMachine &getTargetMachine() const { return TM; } 106 const TargetData *getTargetData() const { return TD; } 107 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 108 109 bool isBigEndian() const { return !IsLittleEndian; } 110 bool isLittleEndian() const { return IsLittleEndian; } 111 MVT getPointerTy() const { return PointerTy; } 112 MVT getShiftAmountTy() const { return ShiftAmountTy; } 113 114 /// isSelectExpensive - Return true if the select operation is expensive for 115 /// this target. 116 bool isSelectExpensive() const { return SelectIsExpensive; } 117 118 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 119 /// a sequence of several shifts, adds, and multiplies for this target. 120 bool isIntDivCheap() const { return IntDivIsCheap; } 121 122 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 123 /// srl/add/sra. 124 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 125 126 /// getSetCCResultType - Return the ValueType of the result of SETCC 127 /// operations. Also used to obtain the target's preferred type for 128 /// the condition operand of SELECT and BRCOND nodes. In the case of 129 /// BRCOND the argument passed is MVT::Other since there are no other 130 /// operands to get a type hint from. 131 virtual 132 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 133 134 /// getCmpLibcallReturnType - Return the ValueType for comparison 135 /// libcalls. Comparions libcalls include floating point comparion calls, 136 /// and Ordered/Unordered check calls on floating point numbers. 137 virtual 138 MVT::SimpleValueType getCmpLibcallReturnType() const; 139 140 /// getBooleanContents - For targets without i1 registers, this gives the 141 /// nature of the high-bits of boolean values held in types wider than i1. 142 /// "Boolean values" are special true/false values produced by nodes like 143 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 144 /// Not to be confused with general values promoted from i1. 145 BooleanContent getBooleanContents() const { return BooleanContents;} 146 147 /// getSchedulingPreference - Return target scheduling preference. 148 Sched::Preference getSchedulingPreference() const { 149 return SchedPreferenceInfo; 150 } 151 152 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 153 /// different scheduling heuristics for different nodes. This function returns 154 /// the preference (or none) for the given node. 155 virtual Sched::Preference getSchedulingPreference(SDNode *N) const { 156 return Sched::None; 157 } 158 159 /// getRegClassFor - Return the register class that should be used for the 160 /// specified value type. 161 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { 162 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 163 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 164 assert(RC && "This value type is not natively supported!"); 165 return RC; 166 } 167 168 /// isTypeLegal - Return true if the target has native support for the 169 /// specified value type. This means that it has a register that directly 170 /// holds it without promotions or expansions. 171 bool isTypeLegal(EVT VT) const { 172 assert(!VT.isSimple() || 173 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 174 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 175 } 176 177 /// isTypeSynthesizable - Return true if it's OK for the compiler to create 178 /// new operations of this type. All Legal types are synthesizable except 179 /// MMX vector types on X86. Non-Legal types are not synthesizable. 180 bool isTypeSynthesizable(EVT VT) const { 181 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy]; 182 } 183 184 class ValueTypeActionImpl { 185 /// ValueTypeActions - For each value type, keep a LegalizeAction enum 186 /// that indicates how instruction selection should deal with the type. 187 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 188 public: 189 ValueTypeActionImpl() { 190 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 191 } 192 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 193 if (VT.isExtended()) { 194 if (VT.isVector()) { 195 return VT.isPow2VectorType() ? Expand : Promote; 196 } 197 if (VT.isInteger()) 198 // First promote to a power-of-two size, then expand if necessary. 199 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote; 200 assert(0 && "Unsupported extended type!"); 201 return Legal; 202 } 203 unsigned I = VT.getSimpleVT().SimpleTy; 204 return (LegalizeAction)ValueTypeActions[I]; 205 } 206 void setTypeAction(EVT VT, LegalizeAction Action) { 207 unsigned I = VT.getSimpleVT().SimpleTy; 208 ValueTypeActions[I] = Action; 209 } 210 }; 211 212 const ValueTypeActionImpl &getValueTypeActions() const { 213 return ValueTypeActions; 214 } 215 216 /// getTypeAction - Return how we should legalize values of this type, either 217 /// it is already legal (return 'Legal') or we need to promote it to a larger 218 /// type (return 'Promote'), or we need to expand it into multiple registers 219 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 220 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 221 return ValueTypeActions.getTypeAction(Context, VT); 222 } 223 224 /// getTypeToTransformTo - For types supported by the target, this is an 225 /// identity function. For types that must be promoted to larger types, this 226 /// returns the larger type to promote to. For integer types that are larger 227 /// than the largest integer register, this contains one step in the expansion 228 /// to get to the smaller register. For illegal floating point types, this 229 /// returns the integer type to transform to. 230 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 231 if (VT.isSimple()) { 232 assert((unsigned)VT.getSimpleVT().SimpleTy < 233 array_lengthof(TransformToType)); 234 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 235 assert(getTypeAction(Context, NVT) != Promote && 236 "Promote may not follow Expand or Promote"); 237 return NVT; 238 } 239 240 if (VT.isVector()) { 241 EVT NVT = VT.getPow2VectorType(Context); 242 if (NVT == VT) { 243 // Vector length is a power of 2 - split to half the size. 244 unsigned NumElts = VT.getVectorNumElements(); 245 EVT EltVT = VT.getVectorElementType(); 246 return (NumElts == 1) ? 247 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 248 } 249 // Promote to a power of two size, avoiding multi-step promotion. 250 return getTypeAction(Context, NVT) == Promote ? 251 getTypeToTransformTo(Context, NVT) : NVT; 252 } else if (VT.isInteger()) { 253 EVT NVT = VT.getRoundIntegerType(Context); 254 if (NVT == VT) 255 // Size is a power of two - expand to half the size. 256 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 257 else 258 // Promote to a power of two size, avoiding multi-step promotion. 259 return getTypeAction(Context, NVT) == Promote ? 260 getTypeToTransformTo(Context, NVT) : NVT; 261 } 262 assert(0 && "Unsupported extended type!"); 263 return MVT(MVT::Other); // Not reached 264 } 265 266 /// getTypeToExpandTo - For types supported by the target, this is an 267 /// identity function. For types that must be expanded (i.e. integer types 268 /// that are larger than the largest integer register or illegal floating 269 /// point types), this returns the largest legal type it will be expanded to. 270 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 271 assert(!VT.isVector()); 272 while (true) { 273 switch (getTypeAction(Context, VT)) { 274 case Legal: 275 return VT; 276 case Expand: 277 VT = getTypeToTransformTo(Context, VT); 278 break; 279 default: 280 assert(false && "Type is not legal nor is it to be expanded!"); 281 return VT; 282 } 283 } 284 return VT; 285 } 286 287 /// getVectorTypeBreakdown - Vector types are broken down into some number of 288 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 289 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 290 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 291 /// 292 /// This method returns the number of registers needed, and the VT for each 293 /// register. It also returns the VT and quantity of the intermediate values 294 /// before they are promoted/expanded. 295 /// 296 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 297 EVT &IntermediateVT, 298 unsigned &NumIntermediates, 299 EVT &RegisterVT) const; 300 301 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 302 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 303 /// this is the case, it returns true and store the intrinsic 304 /// information into the IntrinsicInfo that was passed to the function. 305 struct IntrinsicInfo { 306 unsigned opc; // target opcode 307 EVT memVT; // memory VT 308 const Value* ptrVal; // value representing memory location 309 int offset; // offset off of ptrVal 310 unsigned align; // alignment 311 bool vol; // is volatile? 312 bool readMem; // reads memory? 313 bool writeMem; // writes memory? 314 }; 315 316 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 317 const CallInst &I, unsigned Intrinsic) const { 318 return false; 319 } 320 321 /// isFPImmLegal - Returns true if the target can instruction select the 322 /// specified FP immediate natively. If false, the legalizer will materialize 323 /// the FP immediate as a load from a constant pool. 324 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 325 return false; 326 } 327 328 /// isShuffleMaskLegal - Targets can use this to indicate that they only 329 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 330 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 331 /// are assumed to be legal. 332 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 333 EVT VT) const { 334 return true; 335 } 336 337 /// canOpTrap - Returns true if the operation can trap for the value type. 338 /// VT must be a legal type. By default, we optimistically assume most 339 /// operations don't trap except for divide and remainder. 340 virtual bool canOpTrap(unsigned Op, EVT VT) const; 341 342 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 343 /// used by Targets can use this to indicate if there is a suitable 344 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 345 /// pool entry. 346 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 347 EVT VT) const { 348 return false; 349 } 350 351 /// getOperationAction - Return how this operation should be treated: either 352 /// it is legal, needs to be promoted to a larger size, needs to be 353 /// expanded to some other code sequence, or the target has a custom expander 354 /// for it. 355 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 356 if (VT.isExtended()) return Expand; 357 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 358 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 359 return (LegalizeAction)OpActions[I][Op]; 360 } 361 362 /// isOperationLegalOrCustom - Return true if the specified operation is 363 /// legal on this target or can be made legal with custom lowering. This 364 /// is used to help guide high-level lowering decisions. 365 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 366 return (VT == MVT::Other || isTypeLegal(VT)) && 367 (getOperationAction(Op, VT) == Legal || 368 getOperationAction(Op, VT) == Custom); 369 } 370 371 /// isOperationLegal - Return true if the specified operation is legal on this 372 /// target. 373 bool isOperationLegal(unsigned Op, EVT VT) const { 374 return (VT == MVT::Other || isTypeLegal(VT)) && 375 getOperationAction(Op, VT) == Legal; 376 } 377 378 /// getLoadExtAction - Return how this load with extension should be treated: 379 /// either it is legal, needs to be promoted to a larger size, needs to be 380 /// expanded to some other code sequence, or the target has a custom expander 381 /// for it. 382 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 383 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 384 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 385 "Table isn't big enough!"); 386 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 387 } 388 389 /// isLoadExtLegal - Return true if the specified load with extension is legal 390 /// on this target. 391 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 392 return VT.isSimple() && 393 (getLoadExtAction(ExtType, VT) == Legal || 394 getLoadExtAction(ExtType, VT) == Custom); 395 } 396 397 /// getTruncStoreAction - Return how this store with truncation should be 398 /// treated: either it is legal, needs to be promoted to a larger size, needs 399 /// to be expanded to some other code sequence, or the target has a custom 400 /// expander for it. 401 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 402 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 403 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 404 "Table isn't big enough!"); 405 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 406 [MemVT.getSimpleVT().SimpleTy]; 407 } 408 409 /// isTruncStoreLegal - Return true if the specified store with truncation is 410 /// legal on this target. 411 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 412 return isTypeLegal(ValVT) && MemVT.isSimple() && 413 (getTruncStoreAction(ValVT, MemVT) == Legal || 414 getTruncStoreAction(ValVT, MemVT) == Custom); 415 } 416 417 /// getIndexedLoadAction - Return how the indexed load should be treated: 418 /// either it is legal, needs to be promoted to a larger size, needs to be 419 /// expanded to some other code sequence, or the target has a custom expander 420 /// for it. 421 LegalizeAction 422 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 423 assert( IdxMode < ISD::LAST_INDEXED_MODE && 424 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 425 "Table isn't big enough!"); 426 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 427 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 428 } 429 430 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 431 /// on this target. 432 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 433 return VT.isSimple() && 434 (getIndexedLoadAction(IdxMode, VT) == Legal || 435 getIndexedLoadAction(IdxMode, VT) == Custom); 436 } 437 438 /// getIndexedStoreAction - Return how the indexed store should be treated: 439 /// either it is legal, needs to be promoted to a larger size, needs to be 440 /// expanded to some other code sequence, or the target has a custom expander 441 /// for it. 442 LegalizeAction 443 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 444 assert( IdxMode < ISD::LAST_INDEXED_MODE && 445 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 446 "Table isn't big enough!"); 447 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 448 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 449 } 450 451 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 452 /// on this target. 453 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 454 return VT.isSimple() && 455 (getIndexedStoreAction(IdxMode, VT) == Legal || 456 getIndexedStoreAction(IdxMode, VT) == Custom); 457 } 458 459 /// getCondCodeAction - Return how the condition code should be treated: 460 /// either it is legal, needs to be expanded to some other code sequence, 461 /// or the target has a custom expander for it. 462 LegalizeAction 463 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 464 assert((unsigned)CC < array_lengthof(CondCodeActions) && 465 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 466 "Table isn't big enough!"); 467 LegalizeAction Action = (LegalizeAction) 468 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 469 assert(Action != Promote && "Can't promote condition code!"); 470 return Action; 471 } 472 473 /// isCondCodeLegal - Return true if the specified condition code is legal 474 /// on this target. 475 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 476 return getCondCodeAction(CC, VT) == Legal || 477 getCondCodeAction(CC, VT) == Custom; 478 } 479 480 481 /// getTypeToPromoteTo - If the action for this operation is to promote, this 482 /// method returns the ValueType to promote to. 483 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 484 assert(getOperationAction(Op, VT) == Promote && 485 "This operation isn't promoted!"); 486 487 // See if this has an explicit type specified. 488 std::map<std::pair<unsigned, MVT::SimpleValueType>, 489 MVT::SimpleValueType>::const_iterator PTTI = 490 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 491 if (PTTI != PromoteToType.end()) return PTTI->second; 492 493 assert((VT.isInteger() || VT.isFloatingPoint()) && 494 "Cannot autopromote this type, add it with AddPromotedToType."); 495 496 EVT NVT = VT; 497 do { 498 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 499 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 500 "Didn't find type to promote to!"); 501 } while (!isTypeLegal(NVT) || 502 getOperationAction(Op, NVT) == Promote); 503 return NVT; 504 } 505 506 /// getValueType - Return the EVT corresponding to this LLVM type. 507 /// This is fixed by the LLVM operations except for the pointer size. If 508 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 509 /// counterpart (e.g. structs), otherwise it will assert. 510 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 511 EVT VT = EVT::getEVT(Ty, AllowUnknown); 512 return VT == MVT::iPTR ? PointerTy : VT; 513 } 514 515 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 516 /// function arguments in the caller parameter area. This is the actual 517 /// alignment, not its logarithm. 518 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 519 520 /// getRegisterType - Return the type of registers that this ValueType will 521 /// eventually require. 522 EVT getRegisterType(MVT VT) const { 523 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 524 return RegisterTypeForVT[VT.SimpleTy]; 525 } 526 527 /// getRegisterType - Return the type of registers that this ValueType will 528 /// eventually require. 529 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 530 if (VT.isSimple()) { 531 assert((unsigned)VT.getSimpleVT().SimpleTy < 532 array_lengthof(RegisterTypeForVT)); 533 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 534 } 535 if (VT.isVector()) { 536 EVT VT1, RegisterVT; 537 unsigned NumIntermediates; 538 (void)getVectorTypeBreakdown(Context, VT, VT1, 539 NumIntermediates, RegisterVT); 540 return RegisterVT; 541 } 542 if (VT.isInteger()) { 543 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 544 } 545 assert(0 && "Unsupported extended type!"); 546 return EVT(MVT::Other); // Not reached 547 } 548 549 /// getNumRegisters - Return the number of registers that this ValueType will 550 /// eventually require. This is one for any types promoted to live in larger 551 /// registers, but may be more than one for types (like i64) that are split 552 /// into pieces. For types like i140, which are first promoted then expanded, 553 /// it is the number of registers needed to hold all the bits of the original 554 /// type. For an i140 on a 32 bit machine this means 5 registers. 555 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 556 if (VT.isSimple()) { 557 assert((unsigned)VT.getSimpleVT().SimpleTy < 558 array_lengthof(NumRegistersForVT)); 559 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 560 } 561 if (VT.isVector()) { 562 EVT VT1, VT2; 563 unsigned NumIntermediates; 564 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 565 } 566 if (VT.isInteger()) { 567 unsigned BitWidth = VT.getSizeInBits(); 568 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 569 return (BitWidth + RegWidth - 1) / RegWidth; 570 } 571 assert(0 && "Unsupported extended type!"); 572 return 0; // Not reached 573 } 574 575 /// ShouldShrinkFPConstant - If true, then instruction selection should 576 /// seek to shrink the FP constant of the specified type to a smaller type 577 /// in order to save space and / or reduce runtime. 578 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 579 580 /// hasTargetDAGCombine - If true, the target has custom DAG combine 581 /// transformations that it can perform for the specified node. 582 bool hasTargetDAGCombine(ISD::NodeType NT) const { 583 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 584 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 585 } 586 587 /// This function returns the maximum number of store operations permitted 588 /// to replace a call to llvm.memset. The value is set by the target at the 589 /// performance threshold for such a replacement. 590 /// @brief Get maximum # of store operations permitted for llvm.memset 591 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 592 593 /// This function returns the maximum number of store operations permitted 594 /// to replace a call to llvm.memcpy. The value is set by the target at the 595 /// performance threshold for such a replacement. 596 /// @brief Get maximum # of store operations permitted for llvm.memcpy 597 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 598 599 /// This function returns the maximum number of store operations permitted 600 /// to replace a call to llvm.memmove. The value is set by the target at the 601 /// performance threshold for such a replacement. 602 /// @brief Get maximum # of store operations permitted for llvm.memmove 603 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 604 605 /// This function returns true if the target allows unaligned memory accesses. 606 /// of the specified type. This is used, for example, in situations where an 607 /// array copy/move/set is converted to a sequence of store operations. It's 608 /// use helps to ensure that such replacements don't generate code that causes 609 /// an alignment error (trap) on the target machine. 610 /// @brief Determine if the target supports unaligned memory accesses. 611 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 612 return false; 613 } 614 615 /// This function returns true if the target would benefit from code placement 616 /// optimization. 617 /// @brief Determine if the target should perform code placement optimization. 618 bool shouldOptimizeCodePlacement() const { 619 return benefitFromCodePlacementOpt; 620 } 621 622 /// getOptimalMemOpType - Returns the target specific optimal type for load 623 /// and store operations as a result of memset, memcpy, and memmove 624 /// lowering. If DstAlign is zero that means it's safe to destination 625 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 626 /// means there isn't a need to check it against alignment requirement, 627 /// probably because the source does not need to be loaded. If 628 /// 'NonScalarIntSafe' is true, that means it's safe to return a 629 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 630 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 631 /// constant so it does not need to be loaded. 632 /// It returns EVT::Other if the type should be determined using generic 633 /// target-independent logic. 634 virtual EVT getOptimalMemOpType(uint64_t Size, 635 unsigned DstAlign, unsigned SrcAlign, 636 bool NonScalarIntSafe, bool MemcpyStrSrc, 637 MachineFunction &MF) const { 638 return MVT::Other; 639 } 640 641 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 642 /// to implement llvm.setjmp. 643 bool usesUnderscoreSetJmp() const { 644 return UseUnderscoreSetJmp; 645 } 646 647 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 648 /// to implement llvm.longjmp. 649 bool usesUnderscoreLongJmp() const { 650 return UseUnderscoreLongJmp; 651 } 652 653 /// getStackPointerRegisterToSaveRestore - If a physical register, this 654 /// specifies the register that llvm.savestack/llvm.restorestack should save 655 /// and restore. 656 unsigned getStackPointerRegisterToSaveRestore() const { 657 return StackPointerRegisterToSaveRestore; 658 } 659 660 /// getExceptionAddressRegister - If a physical register, this returns 661 /// the register that receives the exception address on entry to a landing 662 /// pad. 663 unsigned getExceptionAddressRegister() const { 664 return ExceptionPointerRegister; 665 } 666 667 /// getExceptionSelectorRegister - If a physical register, this returns 668 /// the register that receives the exception typeid on entry to a landing 669 /// pad. 670 unsigned getExceptionSelectorRegister() const { 671 return ExceptionSelectorRegister; 672 } 673 674 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 675 /// set, the default is 200) 676 unsigned getJumpBufSize() const { 677 return JumpBufSize; 678 } 679 680 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 681 /// (if never set, the default is 0) 682 unsigned getJumpBufAlignment() const { 683 return JumpBufAlignment; 684 } 685 686 /// getPrefLoopAlignment - return the preferred loop alignment. 687 /// 688 unsigned getPrefLoopAlignment() const { 689 return PrefLoopAlignment; 690 } 691 692 /// getShouldFoldAtomicFences - return whether the combiner should fold 693 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 694 /// 695 bool getShouldFoldAtomicFences() const { 696 return ShouldFoldAtomicFences; 697 } 698 699 /// getPreIndexedAddressParts - returns true by value, base pointer and 700 /// offset pointer and addressing mode by reference if the node's address 701 /// can be legally represented as pre-indexed load / store address. 702 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 703 SDValue &Offset, 704 ISD::MemIndexedMode &AM, 705 SelectionDAG &DAG) const { 706 return false; 707 } 708 709 /// getPostIndexedAddressParts - returns true by value, base pointer and 710 /// offset pointer and addressing mode by reference if this node can be 711 /// combined with a load / store to form a post-indexed load / store. 712 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 713 SDValue &Base, SDValue &Offset, 714 ISD::MemIndexedMode &AM, 715 SelectionDAG &DAG) const { 716 return false; 717 } 718 719 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 720 /// current function. The returned value is a member of the 721 /// MachineJumpTableInfo::JTEntryKind enum. 722 virtual unsigned getJumpTableEncoding() const; 723 724 virtual const MCExpr * 725 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 726 const MachineBasicBlock *MBB, unsigned uid, 727 MCContext &Ctx) const { 728 assert(0 && "Need to implement this hook if target has custom JTIs"); 729 return 0; 730 } 731 732 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 733 /// jumptable. 734 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 735 SelectionDAG &DAG) const; 736 737 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 738 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 739 /// MCExpr. 740 virtual const MCExpr * 741 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 742 unsigned JTI, MCContext &Ctx) const; 743 744 /// isOffsetFoldingLegal - Return true if folding a constant offset 745 /// with the given GlobalAddress is legal. It is frequently not legal in 746 /// PIC relocation models. 747 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 748 749 /// getFunctionAlignment - Return the Log2 alignment of this function. 750 virtual unsigned getFunctionAlignment(const Function *) const = 0; 751 752 /// getStackCookieLocation - Return true if the target stores stack 753 /// protector cookies at a fixed offset in some non-standard address 754 /// space, and populates the address space and offset as 755 /// appropriate. 756 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const { 757 return false; 758 } 759 760 //===--------------------------------------------------------------------===// 761 // TargetLowering Optimization Methods 762 // 763 764 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 765 /// SDValues for returning information from TargetLowering to its clients 766 /// that want to combine 767 struct TargetLoweringOpt { 768 SelectionDAG &DAG; 769 bool LegalTys; 770 bool LegalOps; 771 SDValue Old; 772 SDValue New; 773 774 explicit TargetLoweringOpt(SelectionDAG &InDAG, 775 bool LT, bool LO) : 776 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 777 778 bool LegalTypes() const { return LegalTys; } 779 bool LegalOperations() const { return LegalOps; } 780 781 bool CombineTo(SDValue O, SDValue N) { 782 Old = O; 783 New = N; 784 return true; 785 } 786 787 /// ShrinkDemandedConstant - Check to see if the specified operand of the 788 /// specified instruction is a constant integer. If so, check to see if 789 /// there are any bits set in the constant that are not demanded. If so, 790 /// shrink the constant and return true. 791 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 792 793 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 794 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 795 /// cast, but it could be generalized for targets with other types of 796 /// implicit widening casts. 797 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 798 DebugLoc dl); 799 }; 800 801 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 802 /// DemandedMask bits of the result of Op are ever used downstream. If we can 803 /// use this information to simplify Op, create a new simplified DAG node and 804 /// return true, returning the original and new nodes in Old and New. 805 /// Otherwise, analyze the expression and return a mask of KnownOne and 806 /// KnownZero bits for the expression (used to simplify the caller). 807 /// The KnownZero/One bits may only be accurate for those bits in the 808 /// DemandedMask. 809 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 810 APInt &KnownZero, APInt &KnownOne, 811 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 812 813 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 814 /// Mask are known to be either zero or one and return them in the 815 /// KnownZero/KnownOne bitsets. 816 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 817 const APInt &Mask, 818 APInt &KnownZero, 819 APInt &KnownOne, 820 const SelectionDAG &DAG, 821 unsigned Depth = 0) const; 822 823 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 824 /// targets that want to expose additional information about sign bits to the 825 /// DAG Combiner. 826 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 827 unsigned Depth = 0) const; 828 829 struct DAGCombinerInfo { 830 void *DC; // The DAG Combiner object. 831 bool BeforeLegalize; 832 bool BeforeLegalizeOps; 833 bool CalledByLegalizer; 834 public: 835 SelectionDAG &DAG; 836 837 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 838 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 839 CalledByLegalizer(cl), DAG(dag) {} 840 841 bool isBeforeLegalize() const { return BeforeLegalize; } 842 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 843 bool isCalledByLegalizer() const { return CalledByLegalizer; } 844 845 void AddToWorklist(SDNode *N); 846 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 847 bool AddTo = true); 848 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 849 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 850 851 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 852 }; 853 854 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 855 /// and cc. If it is unable to simplify it, return a null SDValue. 856 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 857 ISD::CondCode Cond, bool foldBooleans, 858 DAGCombinerInfo &DCI, DebugLoc dl) const; 859 860 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 861 /// node is a GlobalAddress + offset. 862 virtual bool 863 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 864 865 /// PerformDAGCombine - This method will be invoked for all target nodes and 866 /// for any target-independent nodes that the target has registered with 867 /// invoke it for. 868 /// 869 /// The semantics are as follows: 870 /// Return Value: 871 /// SDValue.Val == 0 - No change was made 872 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 873 /// otherwise - N should be replaced by the returned Operand. 874 /// 875 /// In addition, methods provided by DAGCombinerInfo may be used to perform 876 /// more complex transformations. 877 /// 878 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 879 880 /// isTypeDesirableForOp - Return true if the target has native support for 881 /// the specified value type and it is 'desirable' to use the type for the 882 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 883 /// instruction encodings are longer and some i16 instructions are slow. 884 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const { 885 // By default, assume all legal types are desirable. 886 return isTypeLegal(VT); 887 } 888 889 /// IsDesirableToPromoteOp - This method query the target whether it is 890 /// beneficial for dag combiner to promote the specified node. If true, it 891 /// should return the desired promotion type by reference. 892 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 893 return false; 894 } 895 896 //===--------------------------------------------------------------------===// 897 // TargetLowering Configuration Methods - These methods should be invoked by 898 // the derived class constructor to configure this object for the target. 899 // 900 901protected: 902 /// setShiftAmountType - Describe the type that should be used for shift 903 /// amounts. This type defaults to the pointer type. 904 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 905 906 /// setBooleanContents - Specify how the target extends the result of a 907 /// boolean value from i1 to a wider type. See getBooleanContents. 908 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 909 910 /// setSchedulingPreference - Specify the target scheduling preference. 911 void setSchedulingPreference(Sched::Preference Pref) { 912 SchedPreferenceInfo = Pref; 913 } 914 915 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 916 /// use _setjmp to implement llvm.setjmp or the non _ version. 917 /// Defaults to false. 918 void setUseUnderscoreSetJmp(bool Val) { 919 UseUnderscoreSetJmp = Val; 920 } 921 922 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 923 /// use _longjmp to implement llvm.longjmp or the non _ version. 924 /// Defaults to false. 925 void setUseUnderscoreLongJmp(bool Val) { 926 UseUnderscoreLongJmp = Val; 927 } 928 929 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 930 /// specifies the register that llvm.savestack/llvm.restorestack should save 931 /// and restore. 932 void setStackPointerRegisterToSaveRestore(unsigned R) { 933 StackPointerRegisterToSaveRestore = R; 934 } 935 936 /// setExceptionPointerRegister - If set to a physical register, this sets 937 /// the register that receives the exception address on entry to a landing 938 /// pad. 939 void setExceptionPointerRegister(unsigned R) { 940 ExceptionPointerRegister = R; 941 } 942 943 /// setExceptionSelectorRegister - If set to a physical register, this sets 944 /// the register that receives the exception typeid on entry to a landing 945 /// pad. 946 void setExceptionSelectorRegister(unsigned R) { 947 ExceptionSelectorRegister = R; 948 } 949 950 /// SelectIsExpensive - Tells the code generator not to expand operations 951 /// into sequences that use the select operations if possible. 952 void setSelectIsExpensive() { SelectIsExpensive = true; } 953 954 /// setIntDivIsCheap - Tells the code generator that integer divide is 955 /// expensive, and if possible, should be replaced by an alternate sequence 956 /// of instructions not containing an integer divide. 957 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 958 959 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 960 /// srl/add/sra for a signed divide by power of two, and let the target handle 961 /// it. 962 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 963 964 /// addRegisterClass - Add the specified register class as an available 965 /// regclass for the specified value type. This indicates the selector can 966 /// handle values of that class natively. 967 void addRegisterClass(EVT VT, TargetRegisterClass *RC, 968 bool isSynthesizable = true) { 969 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 970 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 971 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 972 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable; 973 } 974 975 /// computeRegisterProperties - Once all of the register classes are added, 976 /// this allows us to compute derived properties we expose. 977 void computeRegisterProperties(); 978 979 /// setOperationAction - Indicate that the specified operation does not work 980 /// with the specified type and indicate what to do about it. 981 void setOperationAction(unsigned Op, MVT VT, 982 LegalizeAction Action) { 983 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 984 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 985 } 986 987 /// setLoadExtAction - Indicate that the specified load with extension does 988 /// not work with the specified type and indicate what to do about it. 989 void setLoadExtAction(unsigned ExtType, MVT VT, 990 LegalizeAction Action) { 991 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 992 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 993 "Table isn't big enough!"); 994 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 995 } 996 997 /// setTruncStoreAction - Indicate that the specified truncating store does 998 /// not work with the specified type and indicate what to do about it. 999 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1000 LegalizeAction Action) { 1001 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE && 1002 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE && 1003 "Table isn't big enough!"); 1004 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1005 } 1006 1007 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1008 /// does not work with the specified type and indicate what to do abort 1009 /// it. NOTE: All indexed mode loads are initialized to Expand in 1010 /// TargetLowering.cpp 1011 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1012 LegalizeAction Action) { 1013 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1014 IdxMode < ISD::LAST_INDEXED_MODE && 1015 (unsigned)Action < 0xf && 1016 "Table isn't big enough!"); 1017 // Load action are kept in the upper half. 1018 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1019 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1020 } 1021 1022 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1023 /// does not work with the specified type and indicate what to do about 1024 /// it. NOTE: All indexed mode stores are initialized to Expand in 1025 /// TargetLowering.cpp 1026 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1027 LegalizeAction Action) { 1028 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1029 IdxMode < ISD::LAST_INDEXED_MODE && 1030 (unsigned)Action < 0xf && 1031 "Table isn't big enough!"); 1032 // Store action are kept in the lower half. 1033 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1034 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1035 } 1036 1037 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1038 /// supported on the target and indicate what to do about it. 1039 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1040 LegalizeAction Action) { 1041 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1042 (unsigned)CC < array_lengthof(CondCodeActions) && 1043 "Table isn't big enough!"); 1044 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1045 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1046 } 1047 1048 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1049 /// promotion code defaults to trying a larger integer/fp until it can find 1050 /// one that works. If that default is insufficient, this method can be used 1051 /// by the target to override the default. 1052 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1053 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1054 } 1055 1056 /// setTargetDAGCombine - Targets should invoke this method for each target 1057 /// independent node that they want to provide a custom DAG combiner for by 1058 /// implementing the PerformDAGCombine virtual method. 1059 void setTargetDAGCombine(ISD::NodeType NT) { 1060 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1061 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1062 } 1063 1064 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1065 /// bytes); default is 200 1066 void setJumpBufSize(unsigned Size) { 1067 JumpBufSize = Size; 1068 } 1069 1070 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1071 /// alignment (in bytes); default is 0 1072 void setJumpBufAlignment(unsigned Align) { 1073 JumpBufAlignment = Align; 1074 } 1075 1076 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1077 /// alignment is zero, it means the target does not care about loop alignment. 1078 void setPrefLoopAlignment(unsigned Align) { 1079 PrefLoopAlignment = Align; 1080 } 1081 1082 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1083 /// atomic operation intrinsics includes locking. Default is false. 1084 void setShouldFoldAtomicFences(bool fold) { 1085 ShouldFoldAtomicFences = fold; 1086 } 1087 1088public: 1089 //===--------------------------------------------------------------------===// 1090 // Lowering methods - These methods must be implemented by targets so that 1091 // the SelectionDAGLowering code knows how to lower these. 1092 // 1093 1094 /// LowerFormalArguments - This hook must be implemented to lower the 1095 /// incoming (formal) arguments, described by the Ins array, into the 1096 /// specified DAG. The implementation should fill in the InVals array 1097 /// with legal-type argument values, and return the resulting token 1098 /// chain value. 1099 /// 1100 virtual SDValue 1101 LowerFormalArguments(SDValue Chain, 1102 CallingConv::ID CallConv, bool isVarArg, 1103 const SmallVectorImpl<ISD::InputArg> &Ins, 1104 DebugLoc dl, SelectionDAG &DAG, 1105 SmallVectorImpl<SDValue> &InVals) const { 1106 assert(0 && "Not Implemented"); 1107 return SDValue(); // this is here to silence compiler errors 1108 } 1109 1110 /// LowerCallTo - This function lowers an abstract call to a function into an 1111 /// actual call. This returns a pair of operands. The first element is the 1112 /// return value for the function (if RetTy is not VoidTy). The second 1113 /// element is the outgoing token chain. It calls LowerCall to do the actual 1114 /// lowering. 1115 struct ArgListEntry { 1116 SDValue Node; 1117 const Type* Ty; 1118 bool isSExt : 1; 1119 bool isZExt : 1; 1120 bool isInReg : 1; 1121 bool isSRet : 1; 1122 bool isNest : 1; 1123 bool isByVal : 1; 1124 uint16_t Alignment; 1125 1126 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1127 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1128 }; 1129 typedef std::vector<ArgListEntry> ArgListTy; 1130 std::pair<SDValue, SDValue> 1131 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1132 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1133 CallingConv::ID CallConv, bool isTailCall, 1134 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1135 SelectionDAG &DAG, DebugLoc dl) const; 1136 1137 /// LowerCall - This hook must be implemented to lower calls into the 1138 /// the specified DAG. The outgoing arguments to the call are described 1139 /// by the Outs array, and the values to be returned by the call are 1140 /// described by the Ins array. The implementation should fill in the 1141 /// InVals array with legal-type return values from the call, and return 1142 /// the resulting token chain value. 1143 virtual SDValue 1144 LowerCall(SDValue Chain, SDValue Callee, 1145 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 1146 const SmallVectorImpl<ISD::OutputArg> &Outs, 1147 const SmallVectorImpl<ISD::InputArg> &Ins, 1148 DebugLoc dl, SelectionDAG &DAG, 1149 SmallVectorImpl<SDValue> &InVals) const { 1150 assert(0 && "Not Implemented"); 1151 return SDValue(); // this is here to silence compiler errors 1152 } 1153 1154 /// CanLowerReturn - This hook should be implemented to check whether the 1155 /// return values described by the Outs array can fit into the return 1156 /// registers. If false is returned, an sret-demotion is performed. 1157 /// 1158 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1159 const SmallVectorImpl<EVT> &OutTys, 1160 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1161 SelectionDAG &DAG) const 1162 { 1163 // Return true by default to get preexisting behavior. 1164 return true; 1165 } 1166 1167 /// LowerReturn - This hook must be implemented to lower outgoing 1168 /// return values, described by the Outs array, into the specified 1169 /// DAG. The implementation should return the resulting token chain 1170 /// value. 1171 /// 1172 virtual SDValue 1173 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1174 const SmallVectorImpl<ISD::OutputArg> &Outs, 1175 DebugLoc dl, SelectionDAG &DAG) const { 1176 assert(0 && "Not Implemented"); 1177 return SDValue(); // this is here to silence compiler errors 1178 } 1179 1180 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1181 /// to legalize nodes with an illegal operand type but legal result types. 1182 /// It replaces the LowerOperation callback in the type Legalizer. 1183 /// The reason we can not do away with LowerOperation entirely is that 1184 /// LegalizeDAG isn't yet ready to use this callback. 1185 /// TODO: Consider merging with ReplaceNodeResults. 1186 1187 /// The target places new result values for the node in Results (their number 1188 /// and types must exactly match those of the original return values of 1189 /// the node), or leaves Results empty, which indicates that the node is not 1190 /// to be custom lowered after all. 1191 /// The default implementation calls LowerOperation. 1192 virtual void LowerOperationWrapper(SDNode *N, 1193 SmallVectorImpl<SDValue> &Results, 1194 SelectionDAG &DAG) const; 1195 1196 /// LowerOperation - This callback is invoked for operations that are 1197 /// unsupported by the target, which are registered to use 'custom' lowering, 1198 /// and whose defined values are all legal. 1199 /// If the target has no operations that require custom lowering, it need not 1200 /// implement this. The default implementation of this aborts. 1201 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1202 1203 /// ReplaceNodeResults - This callback is invoked when a node result type is 1204 /// illegal for the target, and the operation was registered to use 'custom' 1205 /// lowering for that result type. The target places new result values for 1206 /// the node in Results (their number and types must exactly match those of 1207 /// the original return values of the node), or leaves Results empty, which 1208 /// indicates that the node is not to be custom lowered after all. 1209 /// 1210 /// If the target has no operations that require custom lowering, it need not 1211 /// implement this. The default implementation aborts. 1212 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1213 SelectionDAG &DAG) const { 1214 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1215 } 1216 1217 /// getTargetNodeName() - This method returns the name of a target specific 1218 /// DAG node. 1219 virtual const char *getTargetNodeName(unsigned Opcode) const; 1220 1221 /// createFastISel - This method returns a target specific FastISel object, 1222 /// or null if the target does not support "fast" ISel. 1223 virtual FastISel * 1224 createFastISel(MachineFunction &, 1225 DenseMap<const Value *, unsigned> &, 1226 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1227 DenseMap<const AllocaInst *, int> &, 1228 std::vector<std::pair<MachineInstr*, unsigned> > & 1229#ifndef NDEBUG 1230 , SmallSet<const Instruction *, 8> &CatchInfoLost 1231#endif 1232 ) const { 1233 return 0; 1234 } 1235 1236 //===--------------------------------------------------------------------===// 1237 // Inline Asm Support hooks 1238 // 1239 1240 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1241 /// call to be explicit llvm code if it wants to. This is useful for 1242 /// turning simple inline asms into LLVM intrinsics, which gives the 1243 /// compiler more information about the behavior of the code. 1244 virtual bool ExpandInlineAsm(CallInst *CI) const { 1245 return false; 1246 } 1247 1248 enum ConstraintType { 1249 C_Register, // Constraint represents specific register(s). 1250 C_RegisterClass, // Constraint represents any of register(s) in class. 1251 C_Memory, // Memory constraint. 1252 C_Other, // Something else. 1253 C_Unknown // Unsupported constraint. 1254 }; 1255 1256 /// AsmOperandInfo - This contains information for each constraint that we are 1257 /// lowering. 1258 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1259 /// ConstraintCode - This contains the actual string for the code, like "m". 1260 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1261 /// most closely matches the operand. 1262 std::string ConstraintCode; 1263 1264 /// ConstraintType - Information about the constraint code, e.g. Register, 1265 /// RegisterClass, Memory, Other, Unknown. 1266 TargetLowering::ConstraintType ConstraintType; 1267 1268 /// CallOperandval - If this is the result output operand or a 1269 /// clobber, this is null, otherwise it is the incoming operand to the 1270 /// CallInst. This gets modified as the asm is processed. 1271 Value *CallOperandVal; 1272 1273 /// ConstraintVT - The ValueType for the operand value. 1274 EVT ConstraintVT; 1275 1276 /// isMatchingInputConstraint - Return true of this is an input operand that 1277 /// is a matching constraint like "4". 1278 bool isMatchingInputConstraint() const; 1279 1280 /// getMatchedOperand - If this is an input matching constraint, this method 1281 /// returns the output operand it matches. 1282 unsigned getMatchedOperand() const; 1283 1284 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1285 : InlineAsm::ConstraintInfo(info), 1286 ConstraintType(TargetLowering::C_Unknown), 1287 CallOperandVal(0), ConstraintVT(MVT::Other) { 1288 } 1289 }; 1290 1291 /// ComputeConstraintToUse - Determines the constraint code and constraint 1292 /// type to use for the specific AsmOperandInfo, setting 1293 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1294 /// being passed in is available, it can be passed in as Op, otherwise an 1295 /// empty SDValue can be passed. 1296 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1297 SDValue Op, 1298 SelectionDAG *DAG = 0) const; 1299 1300 /// getConstraintType - Given a constraint, return the type of constraint it 1301 /// is for this target. 1302 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1303 1304 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1305 /// return a list of registers that can be used to satisfy the constraint. 1306 /// This should only be used for C_RegisterClass constraints. 1307 virtual std::vector<unsigned> 1308 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1309 EVT VT) const; 1310 1311 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1312 /// {edx}), return the register number and the register class for the 1313 /// register. 1314 /// 1315 /// Given a register class constraint, like 'r', if this corresponds directly 1316 /// to an LLVM register class, return a register of 0 and the register class 1317 /// pointer. 1318 /// 1319 /// This should only be used for C_Register constraints. On error, 1320 /// this returns a register number of 0 and a null register class pointer.. 1321 virtual std::pair<unsigned, const TargetRegisterClass*> 1322 getRegForInlineAsmConstraint(const std::string &Constraint, 1323 EVT VT) const; 1324 1325 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1326 /// with another that has more specific requirements based on the type of the 1327 /// corresponding operand. This returns null if there is no replacement to 1328 /// make. 1329 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1330 1331 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1332 /// vector. If it is invalid, don't add anything to Ops. 1333 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1334 std::vector<SDValue> &Ops, 1335 SelectionDAG &DAG) const; 1336 1337 //===--------------------------------------------------------------------===// 1338 // Instruction Emitting Hooks 1339 // 1340 1341 // EmitInstrWithCustomInserter - This method should be implemented by targets 1342 // that mark instructions with the 'usesCustomInserter' flag. These 1343 // instructions are special in various ways, which require special support to 1344 // insert. The specified MachineInstr is created but not inserted into any 1345 // basic blocks, and this method is called to expand it into a sequence of 1346 // instructions, potentially also creating new basic blocks and control flow. 1347 virtual MachineBasicBlock * 1348 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1349 1350 //===--------------------------------------------------------------------===// 1351 // Addressing mode description hooks (used by LSR etc). 1352 // 1353 1354 /// AddrMode - This represents an addressing mode of: 1355 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1356 /// If BaseGV is null, there is no BaseGV. 1357 /// If BaseOffs is zero, there is no base offset. 1358 /// If HasBaseReg is false, there is no base register. 1359 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1360 /// no scale. 1361 /// 1362 struct AddrMode { 1363 GlobalValue *BaseGV; 1364 int64_t BaseOffs; 1365 bool HasBaseReg; 1366 int64_t Scale; 1367 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1368 }; 1369 1370 /// isLegalAddressingMode - Return true if the addressing mode represented by 1371 /// AM is legal for this target, for a load/store of the specified type. 1372 /// The type may be VoidTy, in which case only return true if the addressing 1373 /// mode is legal for a load/store of any legal type. 1374 /// TODO: Handle pre/postinc as well. 1375 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1376 1377 /// isTruncateFree - Return true if it's free to truncate a value of 1378 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1379 /// register EAX to i16 by referencing its sub-register AX. 1380 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1381 return false; 1382 } 1383 1384 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1385 return false; 1386 } 1387 1388 /// isZExtFree - Return true if any actual instruction that defines a 1389 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1390 /// register. This does not necessarily include registers defined in 1391 /// unknown ways, such as incoming arguments, or copies from unknown 1392 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1393 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1394 /// all instructions that define 32-bit values implicit zero-extend the 1395 /// result out to 64 bits. 1396 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1397 return false; 1398 } 1399 1400 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1401 return false; 1402 } 1403 1404 /// isNarrowingProfitable - Return true if it's profitable to narrow 1405 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1406 /// from i32 to i8 but not from i32 to i16. 1407 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1408 return false; 1409 } 1410 1411 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1412 /// icmp immediate, that is the target has icmp instructions which can compare 1413 /// a register against the immediate without having to materialize the 1414 /// immediate into a register. 1415 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1416 return true; 1417 } 1418 1419 //===--------------------------------------------------------------------===// 1420 // Div utility functions 1421 // 1422 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1423 std::vector<SDNode*>* Created) const; 1424 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1425 std::vector<SDNode*>* Created) const; 1426 1427 1428 //===--------------------------------------------------------------------===// 1429 // Runtime Library hooks 1430 // 1431 1432 /// setLibcallName - Rename the default libcall routine name for the specified 1433 /// libcall. 1434 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1435 LibcallRoutineNames[Call] = Name; 1436 } 1437 1438 /// getLibcallName - Get the libcall routine name for the specified libcall. 1439 /// 1440 const char *getLibcallName(RTLIB::Libcall Call) const { 1441 return LibcallRoutineNames[Call]; 1442 } 1443 1444 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1445 /// result of the comparison libcall against zero. 1446 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1447 CmpLibcallCCs[Call] = CC; 1448 } 1449 1450 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1451 /// the comparison libcall against zero. 1452 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1453 return CmpLibcallCCs[Call]; 1454 } 1455 1456 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1457 /// specified libcall. 1458 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1459 LibcallCallingConvs[Call] = CC; 1460 } 1461 1462 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1463 /// specified libcall. 1464 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1465 return LibcallCallingConvs[Call]; 1466 } 1467 1468private: 1469 const TargetMachine &TM; 1470 const TargetData *TD; 1471 const TargetLoweringObjectFile &TLOF; 1472 1473 /// PointerTy - The type to use for pointers, usually i32 or i64. 1474 /// 1475 MVT PointerTy; 1476 1477 /// IsLittleEndian - True if this is a little endian target. 1478 /// 1479 bool IsLittleEndian; 1480 1481 /// SelectIsExpensive - Tells the code generator not to expand operations 1482 /// into sequences that use the select operations if possible. 1483 bool SelectIsExpensive; 1484 1485 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1486 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1487 /// a real cost model is in place. If we ever optimize for size, this will be 1488 /// set to true unconditionally. 1489 bool IntDivIsCheap; 1490 1491 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1492 /// srl/add/sra for a signed divide by power of two, and let the target handle 1493 /// it. 1494 bool Pow2DivIsCheap; 1495 1496 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1497 /// llvm.setjmp. Defaults to false. 1498 bool UseUnderscoreSetJmp; 1499 1500 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1501 /// llvm.longjmp. Defaults to false. 1502 bool UseUnderscoreLongJmp; 1503 1504 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1505 /// PointerTy is. 1506 MVT ShiftAmountTy; 1507 1508 /// BooleanContents - Information about the contents of the high-bits in 1509 /// boolean values held in a type wider than i1. See getBooleanContents. 1510 BooleanContent BooleanContents; 1511 1512 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1513 /// total cycles or lowest register usage. 1514 Sched::Preference SchedPreferenceInfo; 1515 1516 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1517 unsigned JumpBufSize; 1518 1519 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1520 /// buffers 1521 unsigned JumpBufAlignment; 1522 1523 /// PrefLoopAlignment - The perferred loop alignment. 1524 /// 1525 unsigned PrefLoopAlignment; 1526 1527 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1528 /// be folded into the enclosed atomic intrinsic instruction by the 1529 /// combiner. 1530 bool ShouldFoldAtomicFences; 1531 1532 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1533 /// specifies the register that llvm.savestack/llvm.restorestack should save 1534 /// and restore. 1535 unsigned StackPointerRegisterToSaveRestore; 1536 1537 /// ExceptionPointerRegister - If set to a physical register, this specifies 1538 /// the register that receives the exception address on entry to a landing 1539 /// pad. 1540 unsigned ExceptionPointerRegister; 1541 1542 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1543 /// the register that receives the exception typeid on entry to a landing 1544 /// pad. 1545 unsigned ExceptionSelectorRegister; 1546 1547 /// RegClassForVT - This indicates the default register class to use for 1548 /// each ValueType the target supports natively. 1549 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1550 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1551 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1552 1553 /// Synthesizable indicates whether it is OK for the compiler to create new 1554 /// operations using this type. All Legal types are Synthesizable except 1555 /// MMX types on X86. Non-Legal types are not Synthesizable. 1556 bool Synthesizable[MVT::LAST_VALUETYPE]; 1557 1558 /// TransformToType - For any value types we are promoting or expanding, this 1559 /// contains the value type that we are changing to. For Expanded types, this 1560 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1561 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1562 /// by the system, this holds the same type (e.g. i32 -> i32). 1563 EVT TransformToType[MVT::LAST_VALUETYPE]; 1564 1565 /// OpActions - For each operation and each value type, keep a LegalizeAction 1566 /// that indicates how instruction selection should deal with the operation. 1567 /// Most operations are Legal (aka, supported natively by the target), but 1568 /// operations that are not should be described. Note that operations on 1569 /// non-legal value types are not described here. 1570 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1571 1572 /// LoadExtActions - For each load extension type and each value type, 1573 /// keep a LegalizeAction that indicates how instruction selection should deal 1574 /// with a load of a specific value type and extension type. 1575 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1576 1577 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1578 /// indicates whether a truncating store of a specific value type and 1579 /// truncating type is legal. 1580 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1581 1582 /// IndexedModeActions - For each indexed mode and each value type, 1583 /// keep a pair of LegalizeAction that indicates how instruction 1584 /// selection should deal with the load / store. The first dimension is the 1585 /// value_type for the reference. The second dimension represents the various 1586 /// modes for load store. 1587 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1588 1589 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1590 /// LegalizeAction that indicates how instruction selection should 1591 /// deal with the condition code. 1592 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1593 1594 ValueTypeActionImpl ValueTypeActions; 1595 1596 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1597 1598 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1599 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1600 /// which sets a bit in this array. 1601 unsigned char 1602 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1603 1604 /// PromoteToType - For operations that must be promoted to a specific type, 1605 /// this holds the destination type. This map should be sparse, so don't hold 1606 /// it as an array. 1607 /// 1608 /// Targets add entries to this map with AddPromotedToType(..), clients access 1609 /// this with getTypeToPromoteTo(..). 1610 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1611 PromoteToType; 1612 1613 /// LibcallRoutineNames - Stores the name each libcall. 1614 /// 1615 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1616 1617 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1618 /// of each of the comparison libcall against zero. 1619 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1620 1621 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1622 /// libcall. 1623 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1624 1625protected: 1626 /// When lowering \@llvm.memset this field specifies the maximum number of 1627 /// store operations that may be substituted for the call to memset. Targets 1628 /// must set this value based on the cost threshold for that target. Targets 1629 /// should assume that the memset will be done using as many of the largest 1630 /// store operations first, followed by smaller ones, if necessary, per 1631 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1632 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1633 /// store. This only applies to setting a constant array of a constant size. 1634 /// @brief Specify maximum number of store instructions per memset call. 1635 unsigned maxStoresPerMemset; 1636 1637 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1638 /// store operations that may be substituted for a call to memcpy. Targets 1639 /// must set this value based on the cost threshold for that target. Targets 1640 /// should assume that the memcpy will be done using as many of the largest 1641 /// store operations first, followed by smaller ones, if necessary, per 1642 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1643 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1644 /// and one 1-byte store. This only applies to copying a constant array of 1645 /// constant size. 1646 /// @brief Specify maximum bytes of store instructions per memcpy call. 1647 unsigned maxStoresPerMemcpy; 1648 1649 /// When lowering \@llvm.memmove this field specifies the maximum number of 1650 /// store instructions that may be substituted for a call to memmove. Targets 1651 /// must set this value based on the cost threshold for that target. Targets 1652 /// should assume that the memmove will be done using as many of the largest 1653 /// store operations first, followed by smaller ones, if necessary, per 1654 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1655 /// with 8-bit alignment would result in nine 1-byte stores. This only 1656 /// applies to copying a constant array of constant size. 1657 /// @brief Specify maximum bytes of store instructions per memmove call. 1658 unsigned maxStoresPerMemmove; 1659 1660 /// This field specifies whether the target can benefit from code placement 1661 /// optimization. 1662 bool benefitFromCodePlacementOpt; 1663}; 1664} // end llvm namespace 1665 1666#endif 1667