TargetLowering.h revision fb2e752e4175920d0531f2afc93a23d0cdf4db14
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/CodeGen/SelectionDAGNodes.h" 28#include "llvm/CodeGen/RuntimeLibcalls.h" 29#include "llvm/ADT/APFloat.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallSet.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/STLExtras.h" 34#include "llvm/Support/DebugLoc.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class AllocaInst; 42 class CallInst; 43 class Function; 44 class FastISel; 45 class MachineBasicBlock; 46 class MachineFunction; 47 class MachineFrameInfo; 48 class MachineInstr; 49 class MachineModuleInfo; 50 class DwarfWriter; 51 class SDNode; 52 class SDValue; 53 class SelectionDAG; 54 class TargetData; 55 class TargetMachine; 56 class TargetRegisterClass; 57 class TargetSubtarget; 58 class TargetLoweringObjectFile; 59 class Value; 60 61 // FIXME: should this be here? 62 namespace TLSModel { 63 enum Model { 64 GeneralDynamic, 65 LocalDynamic, 66 InitialExec, 67 LocalExec 68 }; 69 } 70 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 71 72 73//===----------------------------------------------------------------------===// 74/// TargetLowering - This class defines information used to lower LLVM code to 75/// legal SelectionDAG operators that the target instruction selector can accept 76/// natively. 77/// 78/// This class also defines callbacks that targets must implement to lower 79/// target-specific constructs to SelectionDAG operators. 80/// 81class TargetLowering { 82 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 83 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 84public: 85 /// LegalizeAction - This enum indicates whether operations are valid for a 86 /// target, and if not, what action should be used to make them valid. 87 enum LegalizeAction { 88 Legal, // The target natively supports this operation. 89 Promote, // This operation should be executed in a larger type. 90 Expand, // Try to expand this to other ops, otherwise use a libcall. 91 Custom // Use the LowerOperation hook to implement custom lowering. 92 }; 93 94 enum BooleanContent { // How the target represents true/false values. 95 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 96 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 97 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 98 }; 99 100 enum SchedPreference { 101 SchedulingForLatency, // Scheduling for shortest total latency. 102 SchedulingForRegPressure // Scheduling for lowest register pressure. 103 }; 104 105 /// NOTE: The constructor takes ownership of TLOF. 106 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF); 107 virtual ~TargetLowering(); 108 109 TargetMachine &getTargetMachine() const { return TM; } 110 const TargetData *getTargetData() const { return TD; } 111 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 112 113 bool isBigEndian() const { return !IsLittleEndian; } 114 bool isLittleEndian() const { return IsLittleEndian; } 115 MVT getPointerTy() const { return PointerTy; } 116 MVT getShiftAmountTy() const { return ShiftAmountTy; } 117 118 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 119 /// codegen. 120 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 121 122 /// isSelectExpensive - Return true if the select operation is expensive for 123 /// this target. 124 bool isSelectExpensive() const { return SelectIsExpensive; } 125 126 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 127 /// a sequence of several shifts, adds, and multiplies for this target. 128 bool isIntDivCheap() const { return IntDivIsCheap; } 129 130 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 131 /// srl/add/sra. 132 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 133 134 /// getSetCCResultType - Return the ValueType of the result of SETCC 135 /// operations. Also used to obtain the target's preferred type for 136 /// the condition operand of SELECT and BRCOND nodes. In the case of 137 /// BRCOND the argument passed is MVT::Other since there are no other 138 /// operands to get a type hint from. 139 virtual 140 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 141 142 /// getBooleanContents - For targets without i1 registers, this gives the 143 /// nature of the high-bits of boolean values held in types wider than i1. 144 /// "Boolean values" are special true/false values produced by nodes like 145 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 146 /// Not to be confused with general values promoted from i1. 147 BooleanContent getBooleanContents() const { return BooleanContents;} 148 149 /// getSchedulingPreference - Return target scheduling preference. 150 SchedPreference getSchedulingPreference() const { 151 return SchedPreferenceInfo; 152 } 153 154 /// getRegClassFor - Return the register class that should be used for the 155 /// specified value type. This may only be called on legal types. 156 TargetRegisterClass *getRegClassFor(EVT VT) const { 157 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 158 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 159 assert(RC && "This value type is not natively supported!"); 160 return RC; 161 } 162 163 /// isTypeLegal - Return true if the target has native support for the 164 /// specified value type. This means that it has a register that directly 165 /// holds it without promotions or expansions. 166 bool isTypeLegal(EVT VT) const { 167 assert(!VT.isSimple() || 168 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 169 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 170 } 171 172 class ValueTypeActionImpl { 173 /// ValueTypeActions - This is a bitvector that contains two bits for each 174 /// value type, where the two bits correspond to the LegalizeAction enum. 175 /// This can be queried with "getTypeAction(VT)". 176 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2 177 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2]; 178 public: 179 ValueTypeActionImpl() { 180 ValueTypeActions[0] = ValueTypeActions[1] = 0; 181 ValueTypeActions[2] = ValueTypeActions[3] = 0; 182 } 183 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 184 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 185 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 186 ValueTypeActions[2] = RHS.ValueTypeActions[2]; 187 ValueTypeActions[3] = RHS.ValueTypeActions[3]; 188 } 189 190 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 191 if (VT.isExtended()) { 192 if (VT.isVector()) { 193 return VT.isPow2VectorType() ? Expand : Promote; 194 } 195 if (VT.isInteger()) 196 // First promote to a power-of-two size, then expand if necessary. 197 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote; 198 assert(0 && "Unsupported extended type!"); 199 return Legal; 200 } 201 unsigned I = VT.getSimpleVT().SimpleTy; 202 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 203 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 204 } 205 void setTypeAction(EVT VT, LegalizeAction Action) { 206 unsigned I = VT.getSimpleVT().SimpleTy; 207 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 208 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 209 } 210 }; 211 212 const ValueTypeActionImpl &getValueTypeActions() const { 213 return ValueTypeActions; 214 } 215 216 /// getTypeAction - Return how we should legalize values of this type, either 217 /// it is already legal (return 'Legal') or we need to promote it to a larger 218 /// type (return 'Promote'), or we need to expand it into multiple registers 219 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 220 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 221 return ValueTypeActions.getTypeAction(Context, VT); 222 } 223 224 /// getTypeToTransformTo - For types supported by the target, this is an 225 /// identity function. For types that must be promoted to larger types, this 226 /// returns the larger type to promote to. For integer types that are larger 227 /// than the largest integer register, this contains one step in the expansion 228 /// to get to the smaller register. For illegal floating point types, this 229 /// returns the integer type to transform to. 230 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 231 if (VT.isSimple()) { 232 assert((unsigned)VT.getSimpleVT().SimpleTy < 233 array_lengthof(TransformToType)); 234 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 235 assert(getTypeAction(Context, NVT) != Promote && 236 "Promote may not follow Expand or Promote"); 237 return NVT; 238 } 239 240 if (VT.isVector()) { 241 EVT NVT = VT.getPow2VectorType(Context); 242 if (NVT == VT) { 243 // Vector length is a power of 2 - split to half the size. 244 unsigned NumElts = VT.getVectorNumElements(); 245 EVT EltVT = VT.getVectorElementType(); 246 return (NumElts == 1) ? 247 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 248 } 249 // Promote to a power of two size, avoiding multi-step promotion. 250 return getTypeAction(Context, NVT) == Promote ? 251 getTypeToTransformTo(Context, NVT) : NVT; 252 } else if (VT.isInteger()) { 253 EVT NVT = VT.getRoundIntegerType(Context); 254 if (NVT == VT) 255 // Size is a power of two - expand to half the size. 256 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 257 else 258 // Promote to a power of two size, avoiding multi-step promotion. 259 return getTypeAction(Context, NVT) == Promote ? 260 getTypeToTransformTo(Context, NVT) : NVT; 261 } 262 assert(0 && "Unsupported extended type!"); 263 return MVT(MVT::Other); // Not reached 264 } 265 266 /// getTypeToExpandTo - For types supported by the target, this is an 267 /// identity function. For types that must be expanded (i.e. integer types 268 /// that are larger than the largest integer register or illegal floating 269 /// point types), this returns the largest legal type it will be expanded to. 270 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 271 assert(!VT.isVector()); 272 while (true) { 273 switch (getTypeAction(Context, VT)) { 274 case Legal: 275 return VT; 276 case Expand: 277 VT = getTypeToTransformTo(Context, VT); 278 break; 279 default: 280 assert(false && "Type is not legal nor is it to be expanded!"); 281 return VT; 282 } 283 } 284 return VT; 285 } 286 287 /// getVectorTypeBreakdown - Vector types are broken down into some number of 288 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 289 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 290 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 291 /// 292 /// This method returns the number of registers needed, and the VT for each 293 /// register. It also returns the VT and quantity of the intermediate values 294 /// before they are promoted/expanded. 295 /// 296 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 297 EVT &IntermediateVT, 298 unsigned &NumIntermediates, 299 EVT &RegisterVT) const; 300 301 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 302 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 303 /// this is the case, it returns true and store the intrinsic 304 /// information into the IntrinsicInfo that was passed to the function. 305 typedef struct IntrinsicInfo { 306 unsigned opc; // target opcode 307 EVT memVT; // memory VT 308 const Value* ptrVal; // value representing memory location 309 int offset; // offset off of ptrVal 310 unsigned align; // alignment 311 bool vol; // is volatile? 312 bool readMem; // reads memory? 313 bool writeMem; // writes memory? 314 } IntrinisicInfo; 315 316 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 317 CallInst &I, unsigned Intrinsic) { 318 return false; 319 } 320 321 /// getWidenVectorType: given a vector type, returns the type to widen to 322 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 323 /// If there is no vector type that we want to widen to, returns MVT::Other 324 /// When and were to widen is target dependent based on the cost of 325 /// scalarizing vs using the wider vector type. 326 virtual EVT getWidenVectorType(EVT VT) const; 327 328 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 329 legal_fpimm_iterator legal_fpimm_begin() const { 330 return LegalFPImmediates.begin(); 331 } 332 legal_fpimm_iterator legal_fpimm_end() const { 333 return LegalFPImmediates.end(); 334 } 335 336 /// isShuffleMaskLegal - Targets can use this to indicate that they only 337 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 338 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 339 /// are assumed to be legal. 340 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 341 EVT VT) const { 342 return true; 343 } 344 345 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 346 /// used by Targets can use this to indicate if there is a suitable 347 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 348 /// pool entry. 349 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 350 EVT VT) const { 351 return false; 352 } 353 354 /// getOperationAction - Return how this operation should be treated: either 355 /// it is legal, needs to be promoted to a larger size, needs to be 356 /// expanded to some other code sequence, or the target has a custom expander 357 /// for it. 358 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 359 if (VT.isExtended()) return Expand; 360 assert(Op < array_lengthof(OpActions[0]) && 361 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 && 362 "Table isn't big enough!"); 363 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 364 unsigned J = I & 31; 365 I = I >> 5; 366 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3); 367 } 368 369 /// isOperationLegalOrCustom - Return true if the specified operation is 370 /// legal on this target or can be made legal with custom lowering. This 371 /// is used to help guide high-level lowering decisions. 372 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 373 return (VT == MVT::Other || isTypeLegal(VT)) && 374 (getOperationAction(Op, VT) == Legal || 375 getOperationAction(Op, VT) == Custom); 376 } 377 378 /// isOperationLegal - Return true if the specified operation is legal on this 379 /// target. 380 bool isOperationLegal(unsigned Op, EVT VT) const { 381 return (VT == MVT::Other || isTypeLegal(VT)) && 382 getOperationAction(Op, VT) == Legal; 383 } 384 385 /// getLoadExtAction - Return how this load with extension should be treated: 386 /// either it is legal, needs to be promoted to a larger size, needs to be 387 /// expanded to some other code sequence, or the target has a custom expander 388 /// for it. 389 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const { 390 assert(LType < array_lengthof(LoadExtActions) && 391 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 && 392 "Table isn't big enough!"); 393 return (LegalizeAction)((LoadExtActions[LType] >> 394 (2*VT.getSimpleVT().SimpleTy)) & 3); 395 } 396 397 /// isLoadExtLegal - Return true if the specified load with extension is legal 398 /// on this target. 399 bool isLoadExtLegal(unsigned LType, EVT VT) const { 400 return VT.isSimple() && 401 (getLoadExtAction(LType, VT) == Legal || 402 getLoadExtAction(LType, VT) == Custom); 403 } 404 405 /// getTruncStoreAction - Return how this store with truncation should be 406 /// treated: either it is legal, needs to be promoted to a larger size, needs 407 /// to be expanded to some other code sequence, or the target has a custom 408 /// expander for it. 409 LegalizeAction getTruncStoreAction(EVT ValVT, 410 EVT MemVT) const { 411 assert((unsigned)ValVT.getSimpleVT().SimpleTy < 412 array_lengthof(TruncStoreActions) && 413 (unsigned)MemVT.getSimpleVT().SimpleTy < 414 sizeof(TruncStoreActions[0])*4 && 415 "Table isn't big enough!"); 416 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >> 417 (2*MemVT.getSimpleVT().SimpleTy)) & 3); 418 } 419 420 /// isTruncStoreLegal - Return true if the specified store with truncation is 421 /// legal on this target. 422 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 423 return isTypeLegal(ValVT) && MemVT.isSimple() && 424 (getTruncStoreAction(ValVT, MemVT) == Legal || 425 getTruncStoreAction(ValVT, MemVT) == Custom); 426 } 427 428 /// getIndexedLoadAction - Return how the indexed load should be treated: 429 /// either it is legal, needs to be promoted to a larger size, needs to be 430 /// expanded to some other code sequence, or the target has a custom expander 431 /// for it. 432 LegalizeAction 433 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 434 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) && 435 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 436 "Table isn't big enough!"); 437 return (LegalizeAction)((IndexedModeActions[ 438 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode])); 439 } 440 441 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 442 /// on this target. 443 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 444 return VT.isSimple() && 445 (getIndexedLoadAction(IdxMode, VT) == Legal || 446 getIndexedLoadAction(IdxMode, VT) == Custom); 447 } 448 449 /// getIndexedStoreAction - Return how the indexed store should be treated: 450 /// either it is legal, needs to be promoted to a larger size, needs to be 451 /// expanded to some other code sequence, or the target has a custom expander 452 /// for it. 453 LegalizeAction 454 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 455 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) && 456 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 457 "Table isn't big enough!"); 458 return (LegalizeAction)((IndexedModeActions[ 459 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode])); 460 } 461 462 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 463 /// on this target. 464 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 465 return VT.isSimple() && 466 (getIndexedStoreAction(IdxMode, VT) == Legal || 467 getIndexedStoreAction(IdxMode, VT) == Custom); 468 } 469 470 /// getConvertAction - Return how the conversion should be treated: 471 /// either it is legal, needs to be promoted to a larger size, needs to be 472 /// expanded to some other code sequence, or the target has a custom expander 473 /// for it. 474 LegalizeAction 475 getConvertAction(EVT FromVT, EVT ToVT) const { 476 assert((unsigned)FromVT.getSimpleVT().SimpleTy < 477 array_lengthof(ConvertActions) && 478 (unsigned)ToVT.getSimpleVT().SimpleTy < 479 sizeof(ConvertActions[0])*4 && 480 "Table isn't big enough!"); 481 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >> 482 (2*ToVT.getSimpleVT().SimpleTy)) & 3); 483 } 484 485 /// isConvertLegal - Return true if the specified conversion is legal 486 /// on this target. 487 bool isConvertLegal(EVT FromVT, EVT ToVT) const { 488 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 489 (getConvertAction(FromVT, ToVT) == Legal || 490 getConvertAction(FromVT, ToVT) == Custom); 491 } 492 493 /// getCondCodeAction - Return how the condition code should be treated: 494 /// either it is legal, needs to be expanded to some other code sequence, 495 /// or the target has a custom expander for it. 496 LegalizeAction 497 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 498 assert((unsigned)CC < array_lengthof(CondCodeActions) && 499 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 500 "Table isn't big enough!"); 501 LegalizeAction Action = (LegalizeAction) 502 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 503 assert(Action != Promote && "Can't promote condition code!"); 504 return Action; 505 } 506 507 /// isCondCodeLegal - Return true if the specified condition code is legal 508 /// on this target. 509 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 510 return getCondCodeAction(CC, VT) == Legal || 511 getCondCodeAction(CC, VT) == Custom; 512 } 513 514 515 /// getTypeToPromoteTo - If the action for this operation is to promote, this 516 /// method returns the ValueType to promote to. 517 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 518 assert(getOperationAction(Op, VT) == Promote && 519 "This operation isn't promoted!"); 520 521 // See if this has an explicit type specified. 522 std::map<std::pair<unsigned, MVT::SimpleValueType>, 523 MVT::SimpleValueType>::const_iterator PTTI = 524 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 525 if (PTTI != PromoteToType.end()) return PTTI->second; 526 527 assert((VT.isInteger() || VT.isFloatingPoint()) && 528 "Cannot autopromote this type, add it with AddPromotedToType."); 529 530 EVT NVT = VT; 531 do { 532 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 533 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 534 "Didn't find type to promote to!"); 535 } while (!isTypeLegal(NVT) || 536 getOperationAction(Op, NVT) == Promote); 537 return NVT; 538 } 539 540 /// getValueType - Return the EVT corresponding to this LLVM type. 541 /// This is fixed by the LLVM operations except for the pointer size. If 542 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 543 /// counterpart (e.g. structs), otherwise it will assert. 544 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 545 EVT VT = EVT::getEVT(Ty, AllowUnknown); 546 return VT == MVT:: iPTR ? PointerTy : VT; 547 } 548 549 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 550 /// function arguments in the caller parameter area. This is the actual 551 /// alignment, not its logarithm. 552 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 553 554 /// getRegisterType - Return the type of registers that this ValueType will 555 /// eventually require. 556 EVT getRegisterType(MVT VT) const { 557 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 558 return RegisterTypeForVT[VT.SimpleTy]; 559 } 560 561 /// getRegisterType - Return the type of registers that this ValueType will 562 /// eventually require. 563 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 564 if (VT.isSimple()) { 565 assert((unsigned)VT.getSimpleVT().SimpleTy < 566 array_lengthof(RegisterTypeForVT)); 567 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 568 } 569 if (VT.isVector()) { 570 EVT VT1, RegisterVT; 571 unsigned NumIntermediates; 572 (void)getVectorTypeBreakdown(Context, VT, VT1, 573 NumIntermediates, RegisterVT); 574 return RegisterVT; 575 } 576 if (VT.isInteger()) { 577 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 578 } 579 assert(0 && "Unsupported extended type!"); 580 return EVT(MVT::Other); // Not reached 581 } 582 583 /// getNumRegisters - Return the number of registers that this ValueType will 584 /// eventually require. This is one for any types promoted to live in larger 585 /// registers, but may be more than one for types (like i64) that are split 586 /// into pieces. For types like i140, which are first promoted then expanded, 587 /// it is the number of registers needed to hold all the bits of the original 588 /// type. For an i140 on a 32 bit machine this means 5 registers. 589 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 590 if (VT.isSimple()) { 591 assert((unsigned)VT.getSimpleVT().SimpleTy < 592 array_lengthof(NumRegistersForVT)); 593 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 594 } 595 if (VT.isVector()) { 596 EVT VT1, VT2; 597 unsigned NumIntermediates; 598 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 599 } 600 if (VT.isInteger()) { 601 unsigned BitWidth = VT.getSizeInBits(); 602 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 603 return (BitWidth + RegWidth - 1) / RegWidth; 604 } 605 assert(0 && "Unsupported extended type!"); 606 return 0; // Not reached 607 } 608 609 /// ShouldShrinkFPConstant - If true, then instruction selection should 610 /// seek to shrink the FP constant of the specified type to a smaller type 611 /// in order to save space and / or reduce runtime. 612 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 613 614 /// hasTargetDAGCombine - If true, the target has custom DAG combine 615 /// transformations that it can perform for the specified node. 616 bool hasTargetDAGCombine(ISD::NodeType NT) const { 617 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 618 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 619 } 620 621 /// This function returns the maximum number of store operations permitted 622 /// to replace a call to llvm.memset. The value is set by the target at the 623 /// performance threshold for such a replacement. 624 /// @brief Get maximum # of store operations permitted for llvm.memset 625 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 626 627 /// This function returns the maximum number of store operations permitted 628 /// to replace a call to llvm.memcpy. The value is set by the target at the 629 /// performance threshold for such a replacement. 630 /// @brief Get maximum # of store operations permitted for llvm.memcpy 631 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 632 633 /// This function returns the maximum number of store operations permitted 634 /// to replace a call to llvm.memmove. The value is set by the target at the 635 /// performance threshold for such a replacement. 636 /// @brief Get maximum # of store operations permitted for llvm.memmove 637 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 638 639 /// This function returns true if the target allows unaligned memory accesses. 640 /// of the specified type. This is used, for example, in situations where an 641 /// array copy/move/set is converted to a sequence of store operations. It's 642 /// use helps to ensure that such replacements don't generate code that causes 643 /// an alignment error (trap) on the target machine. 644 /// @brief Determine if the target supports unaligned memory accesses. 645 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 646 return false; 647 } 648 649 /// This function returns true if the target would benefit from code placement 650 /// optimization. 651 /// @brief Determine if the target should perform code placement optimization. 652 bool shouldOptimizeCodePlacement() const { 653 return benefitFromCodePlacementOpt; 654 } 655 656 /// getOptimalMemOpType - Returns the target specific optimal type for load 657 /// and store operations as a result of memset, memcpy, and memmove lowering. 658 /// It returns EVT::iAny if SelectionDAG should be responsible for 659 /// determining it. 660 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 661 bool isSrcConst, bool isSrcStr, 662 SelectionDAG &DAG) const { 663 return MVT::iAny; 664 } 665 666 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 667 /// to implement llvm.setjmp. 668 bool usesUnderscoreSetJmp() const { 669 return UseUnderscoreSetJmp; 670 } 671 672 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 673 /// to implement llvm.longjmp. 674 bool usesUnderscoreLongJmp() const { 675 return UseUnderscoreLongJmp; 676 } 677 678 /// getStackPointerRegisterToSaveRestore - If a physical register, this 679 /// specifies the register that llvm.savestack/llvm.restorestack should save 680 /// and restore. 681 unsigned getStackPointerRegisterToSaveRestore() const { 682 return StackPointerRegisterToSaveRestore; 683 } 684 685 /// getExceptionAddressRegister - If a physical register, this returns 686 /// the register that receives the exception address on entry to a landing 687 /// pad. 688 unsigned getExceptionAddressRegister() const { 689 return ExceptionPointerRegister; 690 } 691 692 /// getExceptionSelectorRegister - If a physical register, this returns 693 /// the register that receives the exception typeid on entry to a landing 694 /// pad. 695 unsigned getExceptionSelectorRegister() const { 696 return ExceptionSelectorRegister; 697 } 698 699 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 700 /// set, the default is 200) 701 unsigned getJumpBufSize() const { 702 return JumpBufSize; 703 } 704 705 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 706 /// (if never set, the default is 0) 707 unsigned getJumpBufAlignment() const { 708 return JumpBufAlignment; 709 } 710 711 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 712 /// limit. Any block whose size is greater should not be predicated. 713 unsigned getIfCvtBlockSizeLimit() const { 714 return IfCvtBlockSizeLimit; 715 } 716 717 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 718 /// block to be considered for duplication. Any block whose size is greater 719 /// should not be duplicated to facilitate its predication. 720 unsigned getIfCvtDupBlockSizeLimit() const { 721 return IfCvtDupBlockSizeLimit; 722 } 723 724 /// getPrefLoopAlignment - return the preferred loop alignment. 725 /// 726 unsigned getPrefLoopAlignment() const { 727 return PrefLoopAlignment; 728 } 729 730 /// getPreIndexedAddressParts - returns true by value, base pointer and 731 /// offset pointer and addressing mode by reference if the node's address 732 /// can be legally represented as pre-indexed load / store address. 733 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 734 SDValue &Offset, 735 ISD::MemIndexedMode &AM, 736 SelectionDAG &DAG) const { 737 return false; 738 } 739 740 /// getPostIndexedAddressParts - returns true by value, base pointer and 741 /// offset pointer and addressing mode by reference if this node can be 742 /// combined with a load / store to form a post-indexed load / store. 743 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 744 SDValue &Base, SDValue &Offset, 745 ISD::MemIndexedMode &AM, 746 SelectionDAG &DAG) const { 747 return false; 748 } 749 750 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 751 /// jumptable. 752 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 753 SelectionDAG &DAG) const; 754 755 /// isOffsetFoldingLegal - Return true if folding a constant offset 756 /// with the given GlobalAddress is legal. It is frequently not legal in 757 /// PIC relocation models. 758 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 759 760 /// getFunctionAlignment - Return the Log2 alignment of this function. 761 virtual unsigned getFunctionAlignment(const Function *) const = 0; 762 763 //===--------------------------------------------------------------------===// 764 // TargetLowering Optimization Methods 765 // 766 767 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 768 /// SDValues for returning information from TargetLowering to its clients 769 /// that want to combine 770 struct TargetLoweringOpt { 771 SelectionDAG &DAG; 772 SDValue Old; 773 SDValue New; 774 775 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 776 777 bool CombineTo(SDValue O, SDValue N) { 778 Old = O; 779 New = N; 780 return true; 781 } 782 783 /// ShrinkDemandedConstant - Check to see if the specified operand of the 784 /// specified instruction is a constant integer. If so, check to see if 785 /// there are any bits set in the constant that are not demanded. If so, 786 /// shrink the constant and return true. 787 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 788 789 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 790 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 791 /// cast, but it could be generalized for targets with other types of 792 /// implicit widening casts. 793 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 794 DebugLoc dl); 795 }; 796 797 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 798 /// DemandedMask bits of the result of Op are ever used downstream. If we can 799 /// use this information to simplify Op, create a new simplified DAG node and 800 /// return true, returning the original and new nodes in Old and New. 801 /// Otherwise, analyze the expression and return a mask of KnownOne and 802 /// KnownZero bits for the expression (used to simplify the caller). 803 /// The KnownZero/One bits may only be accurate for those bits in the 804 /// DemandedMask. 805 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 806 APInt &KnownZero, APInt &KnownOne, 807 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 808 809 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 810 /// Mask are known to be either zero or one and return them in the 811 /// KnownZero/KnownOne bitsets. 812 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 813 const APInt &Mask, 814 APInt &KnownZero, 815 APInt &KnownOne, 816 const SelectionDAG &DAG, 817 unsigned Depth = 0) const; 818 819 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 820 /// targets that want to expose additional information about sign bits to the 821 /// DAG Combiner. 822 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 823 unsigned Depth = 0) const; 824 825 struct DAGCombinerInfo { 826 void *DC; // The DAG Combiner object. 827 bool BeforeLegalize; 828 bool BeforeLegalizeOps; 829 bool CalledByLegalizer; 830 public: 831 SelectionDAG &DAG; 832 833 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 834 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 835 CalledByLegalizer(cl), DAG(dag) {} 836 837 bool isBeforeLegalize() const { return BeforeLegalize; } 838 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 839 bool isCalledByLegalizer() const { return CalledByLegalizer; } 840 841 void AddToWorklist(SDNode *N); 842 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 843 bool AddTo = true); 844 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 845 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 846 847 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 848 }; 849 850 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 851 /// and cc. If it is unable to simplify it, return a null SDValue. 852 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 853 ISD::CondCode Cond, bool foldBooleans, 854 DAGCombinerInfo &DCI, DebugLoc dl) const; 855 856 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 857 /// node is a GlobalAddress + offset. 858 virtual bool 859 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 860 861 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 862 /// location that is 'Dist' units away from the location that the 'Base' load 863 /// is loading from. 864 bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, 865 int Dist, const MachineFrameInfo *MFI) const; 866 867 /// PerformDAGCombine - This method will be invoked for all target nodes and 868 /// for any target-independent nodes that the target has registered with 869 /// invoke it for. 870 /// 871 /// The semantics are as follows: 872 /// Return Value: 873 /// SDValue.Val == 0 - No change was made 874 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 875 /// otherwise - N should be replaced by the returned Operand. 876 /// 877 /// In addition, methods provided by DAGCombinerInfo may be used to perform 878 /// more complex transformations. 879 /// 880 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 881 882 //===--------------------------------------------------------------------===// 883 // TargetLowering Configuration Methods - These methods should be invoked by 884 // the derived class constructor to configure this object for the target. 885 // 886 887protected: 888 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 889 /// GOT for PC-relative code. 890 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 891 892 /// setShiftAmountType - Describe the type that should be used for shift 893 /// amounts. This type defaults to the pointer type. 894 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 895 896 /// setBooleanContents - Specify how the target extends the result of a 897 /// boolean value from i1 to a wider type. See getBooleanContents. 898 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 899 900 /// setSchedulingPreference - Specify the target scheduling preference. 901 void setSchedulingPreference(SchedPreference Pref) { 902 SchedPreferenceInfo = Pref; 903 } 904 905 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 906 /// use _setjmp to implement llvm.setjmp or the non _ version. 907 /// Defaults to false. 908 void setUseUnderscoreSetJmp(bool Val) { 909 UseUnderscoreSetJmp = Val; 910 } 911 912 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 913 /// use _longjmp to implement llvm.longjmp or the non _ version. 914 /// Defaults to false. 915 void setUseUnderscoreLongJmp(bool Val) { 916 UseUnderscoreLongJmp = Val; 917 } 918 919 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 920 /// specifies the register that llvm.savestack/llvm.restorestack should save 921 /// and restore. 922 void setStackPointerRegisterToSaveRestore(unsigned R) { 923 StackPointerRegisterToSaveRestore = R; 924 } 925 926 /// setExceptionPointerRegister - If set to a physical register, this sets 927 /// the register that receives the exception address on entry to a landing 928 /// pad. 929 void setExceptionPointerRegister(unsigned R) { 930 ExceptionPointerRegister = R; 931 } 932 933 /// setExceptionSelectorRegister - If set to a physical register, this sets 934 /// the register that receives the exception typeid on entry to a landing 935 /// pad. 936 void setExceptionSelectorRegister(unsigned R) { 937 ExceptionSelectorRegister = R; 938 } 939 940 /// SelectIsExpensive - Tells the code generator not to expand operations 941 /// into sequences that use the select operations if possible. 942 void setSelectIsExpensive() { SelectIsExpensive = true; } 943 944 /// setIntDivIsCheap - Tells the code generator that integer divide is 945 /// expensive, and if possible, should be replaced by an alternate sequence 946 /// of instructions not containing an integer divide. 947 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 948 949 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 950 /// srl/add/sra for a signed divide by power of two, and let the target handle 951 /// it. 952 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 953 954 /// addRegisterClass - Add the specified register class as an available 955 /// regclass for the specified value type. This indicates the selector can 956 /// handle values of that class natively. 957 void addRegisterClass(EVT VT, TargetRegisterClass *RC) { 958 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 959 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 960 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 961 } 962 963 /// computeRegisterProperties - Once all of the register classes are added, 964 /// this allows us to compute derived properties we expose. 965 void computeRegisterProperties(); 966 967 /// setOperationAction - Indicate that the specified operation does not work 968 /// with the specified type and indicate what to do about it. 969 void setOperationAction(unsigned Op, MVT VT, 970 LegalizeAction Action) { 971 unsigned I = (unsigned)VT.SimpleTy; 972 unsigned J = I & 31; 973 I = I >> 5; 974 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2)); 975 OpActions[I][Op] |= (uint64_t)Action << (J*2); 976 } 977 978 /// setLoadExtAction - Indicate that the specified load with extension does 979 /// not work with the with specified type and indicate what to do about it. 980 void setLoadExtAction(unsigned ExtType, MVT VT, 981 LegalizeAction Action) { 982 assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 && 983 ExtType < array_lengthof(LoadExtActions) && 984 "Table isn't big enough!"); 985 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 986 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2; 987 } 988 989 /// setTruncStoreAction - Indicate that the specified truncating store does 990 /// not work with the with specified type and indicate what to do about it. 991 void setTruncStoreAction(MVT ValVT, MVT MemVT, 992 LegalizeAction Action) { 993 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) && 994 (unsigned)MemVT.SimpleTy < sizeof(TruncStoreActions[0])*4 && 995 "Table isn't big enough!"); 996 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2); 997 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2; 998 } 999 1000 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1001 /// does not work with the with specified type and indicate what to do abort 1002 /// it. NOTE: All indexed mode loads are initialized to Expand in 1003 /// TargetLowering.cpp 1004 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1005 LegalizeAction Action) { 1006 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1007 IdxMode < array_lengthof(IndexedModeActions[0][0]) && 1008 "Table isn't big enough!"); 1009 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action; 1010 } 1011 1012 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1013 /// does not work with the with specified type and indicate what to do about 1014 /// it. NOTE: All indexed mode stores are initialized to Expand in 1015 /// TargetLowering.cpp 1016 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1017 LegalizeAction Action) { 1018 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1019 IdxMode < array_lengthof(IndexedModeActions[0][1] ) && 1020 "Table isn't big enough!"); 1021 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action; 1022 } 1023 1024 /// setConvertAction - Indicate that the specified conversion does or does 1025 /// not work with the with specified type and indicate what to do about it. 1026 void setConvertAction(MVT FromVT, MVT ToVT, 1027 LegalizeAction Action) { 1028 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) && 1029 (unsigned)ToVT.SimpleTy < sizeof(ConvertActions[0])*4 && 1030 "Table isn't big enough!"); 1031 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2); 1032 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2; 1033 } 1034 1035 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1036 /// supported on the target and indicate what to do about it. 1037 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1038 LegalizeAction Action) { 1039 assert((unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 && 1040 (unsigned)CC < array_lengthof(CondCodeActions) && 1041 "Table isn't big enough!"); 1042 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1043 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1044 } 1045 1046 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1047 /// promotion code defaults to trying a larger integer/fp until it can find 1048 /// one that works. If that default is insufficient, this method can be used 1049 /// by the target to override the default. 1050 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1051 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1052 } 1053 1054 /// addLegalFPImmediate - Indicate that this target can instruction select 1055 /// the specified FP immediate natively. 1056 void addLegalFPImmediate(const APFloat& Imm) { 1057 LegalFPImmediates.push_back(Imm); 1058 } 1059 1060 /// setTargetDAGCombine - Targets should invoke this method for each target 1061 /// independent node that they want to provide a custom DAG combiner for by 1062 /// implementing the PerformDAGCombine virtual method. 1063 void setTargetDAGCombine(ISD::NodeType NT) { 1064 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1065 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1066 } 1067 1068 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1069 /// bytes); default is 200 1070 void setJumpBufSize(unsigned Size) { 1071 JumpBufSize = Size; 1072 } 1073 1074 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1075 /// alignment (in bytes); default is 0 1076 void setJumpBufAlignment(unsigned Align) { 1077 JumpBufAlignment = Align; 1078 } 1079 1080 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1081 /// limit (in number of instructions); default is 2. 1082 void setIfCvtBlockSizeLimit(unsigned Limit) { 1083 IfCvtBlockSizeLimit = Limit; 1084 } 1085 1086 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1087 /// of instructions) to be considered for code duplication during 1088 /// if-conversion; default is 2. 1089 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1090 IfCvtDupBlockSizeLimit = Limit; 1091 } 1092 1093 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1094 /// alignment is zero, it means the target does not care about loop alignment. 1095 void setPrefLoopAlignment(unsigned Align) { 1096 PrefLoopAlignment = Align; 1097 } 1098 1099public: 1100 1101 virtual const TargetSubtarget *getSubtarget() { 1102 assert(0 && "Not Implemented"); 1103 return NULL; // this is here to silence compiler errors 1104 } 1105 1106 //===--------------------------------------------------------------------===// 1107 // Lowering methods - These methods must be implemented by targets so that 1108 // the SelectionDAGLowering code knows how to lower these. 1109 // 1110 1111 /// LowerFormalArguments - This hook must be implemented to lower the 1112 /// incoming (formal) arguments, described by the Ins array, into the 1113 /// specified DAG. The implementation should fill in the InVals array 1114 /// with legal-type argument values, and return the resulting token 1115 /// chain value. 1116 /// 1117 virtual SDValue 1118 LowerFormalArguments(SDValue Chain, 1119 CallingConv::ID CallConv, bool isVarArg, 1120 const SmallVectorImpl<ISD::InputArg> &Ins, 1121 DebugLoc dl, SelectionDAG &DAG, 1122 SmallVectorImpl<SDValue> &InVals) { 1123 assert(0 && "Not Implemented"); 1124 return SDValue(); // this is here to silence compiler errors 1125 } 1126 1127 /// LowerCallTo - This function lowers an abstract call to a function into an 1128 /// actual call. This returns a pair of operands. The first element is the 1129 /// return value for the function (if RetTy is not VoidTy). The second 1130 /// element is the outgoing token chain. It calls LowerCall to do the actual 1131 /// lowering. 1132 struct ArgListEntry { 1133 SDValue Node; 1134 const Type* Ty; 1135 bool isSExt : 1; 1136 bool isZExt : 1; 1137 bool isInReg : 1; 1138 bool isSRet : 1; 1139 bool isNest : 1; 1140 bool isByVal : 1; 1141 uint16_t Alignment; 1142 1143 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1144 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1145 }; 1146 typedef std::vector<ArgListEntry> ArgListTy; 1147 std::pair<SDValue, SDValue> 1148 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1149 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1150 CallingConv::ID CallConv, bool isTailCall, 1151 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1152 SelectionDAG &DAG, DebugLoc dl); 1153 1154 /// LowerCall - This hook must be implemented to lower calls into the 1155 /// the specified DAG. The outgoing arguments to the call are described 1156 /// by the Outs array, and the values to be returned by the call are 1157 /// described by the Ins array. The implementation should fill in the 1158 /// InVals array with legal-type return values from the call, and return 1159 /// the resulting token chain value. 1160 /// 1161 /// The isTailCall flag here is normative. If it is true, the 1162 /// implementation must emit a tail call. The 1163 /// IsEligibleForTailCallOptimization hook should be used to catch 1164 /// cases that cannot be handled. 1165 /// 1166 virtual SDValue 1167 LowerCall(SDValue Chain, SDValue Callee, 1168 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 1169 const SmallVectorImpl<ISD::OutputArg> &Outs, 1170 const SmallVectorImpl<ISD::InputArg> &Ins, 1171 DebugLoc dl, SelectionDAG &DAG, 1172 SmallVectorImpl<SDValue> &InVals) { 1173 assert(0 && "Not Implemented"); 1174 return SDValue(); // this is here to silence compiler errors 1175 } 1176 1177 /// LowerReturn - This hook must be implemented to lower outgoing 1178 /// return values, described by the Outs array, into the specified 1179 /// DAG. The implementation should return the resulting token chain 1180 /// value. 1181 /// 1182 virtual SDValue 1183 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1184 const SmallVectorImpl<ISD::OutputArg> &Outs, 1185 DebugLoc dl, SelectionDAG &DAG) { 1186 assert(0 && "Not Implemented"); 1187 return SDValue(); // this is here to silence compiler errors 1188 } 1189 1190 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1191 /// memcpy. This can be used by targets to provide code sequences for cases 1192 /// that don't fit the target's parameters for simple loads/stores and can be 1193 /// more efficient than using a library call. This function can return a null 1194 /// SDValue if the target declines to use custom code and a different 1195 /// lowering strategy should be used. 1196 /// 1197 /// If AlwaysInline is true, the size is constant and the target should not 1198 /// emit any calls and is strongly encouraged to attempt to emit inline code 1199 /// even if it is beyond the usual threshold because this intrinsic is being 1200 /// expanded in a place where calls are not feasible (e.g. within the prologue 1201 /// for another call). If the target chooses to decline an AlwaysInline 1202 /// request here, legalize will resort to using simple loads and stores. 1203 virtual SDValue 1204 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1205 SDValue Chain, 1206 SDValue Op1, SDValue Op2, 1207 SDValue Op3, unsigned Align, 1208 bool AlwaysInline, 1209 const Value *DstSV, uint64_t DstOff, 1210 const Value *SrcSV, uint64_t SrcOff) { 1211 return SDValue(); 1212 } 1213 1214 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1215 /// memmove. This can be used by targets to provide code sequences for cases 1216 /// that don't fit the target's parameters for simple loads/stores and can be 1217 /// more efficient than using a library call. This function can return a null 1218 /// SDValue if the target declines to use custom code and a different 1219 /// lowering strategy should be used. 1220 virtual SDValue 1221 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1222 SDValue Chain, 1223 SDValue Op1, SDValue Op2, 1224 SDValue Op3, unsigned Align, 1225 const Value *DstSV, uint64_t DstOff, 1226 const Value *SrcSV, uint64_t SrcOff) { 1227 return SDValue(); 1228 } 1229 1230 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1231 /// memset. This can be used by targets to provide code sequences for cases 1232 /// that don't fit the target's parameters for simple stores and can be more 1233 /// efficient than using a library call. This function can return a null 1234 /// SDValue if the target declines to use custom code and a different 1235 /// lowering strategy should be used. 1236 virtual SDValue 1237 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1238 SDValue Chain, 1239 SDValue Op1, SDValue Op2, 1240 SDValue Op3, unsigned Align, 1241 const Value *DstSV, uint64_t DstOff) { 1242 return SDValue(); 1243 } 1244 1245 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1246 /// to legalize nodes with an illegal operand type but legal result types. 1247 /// It replaces the LowerOperation callback in the type Legalizer. 1248 /// The reason we can not do away with LowerOperation entirely is that 1249 /// LegalizeDAG isn't yet ready to use this callback. 1250 /// TODO: Consider merging with ReplaceNodeResults. 1251 1252 /// The target places new result values for the node in Results (their number 1253 /// and types must exactly match those of the original return values of 1254 /// the node), or leaves Results empty, which indicates that the node is not 1255 /// to be custom lowered after all. 1256 /// The default implementation calls LowerOperation. 1257 virtual void LowerOperationWrapper(SDNode *N, 1258 SmallVectorImpl<SDValue> &Results, 1259 SelectionDAG &DAG); 1260 1261 /// LowerOperation - This callback is invoked for operations that are 1262 /// unsupported by the target, which are registered to use 'custom' lowering, 1263 /// and whose defined values are all legal. 1264 /// If the target has no operations that require custom lowering, it need not 1265 /// implement this. The default implementation of this aborts. 1266 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1267 1268 /// ReplaceNodeResults - This callback is invoked when a node result type is 1269 /// illegal for the target, and the operation was registered to use 'custom' 1270 /// lowering for that result type. The target places new result values for 1271 /// the node in Results (their number and types must exactly match those of 1272 /// the original return values of the node), or leaves Results empty, which 1273 /// indicates that the node is not to be custom lowered after all. 1274 /// 1275 /// If the target has no operations that require custom lowering, it need not 1276 /// implement this. The default implementation aborts. 1277 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1278 SelectionDAG &DAG) { 1279 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1280 } 1281 1282 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1283 /// tail call optimization. Targets which want to do tail call optimization 1284 /// should override this function. 1285 virtual bool 1286 IsEligibleForTailCallOptimization(SDValue Callee, 1287 CallingConv::ID CalleeCC, 1288 bool isVarArg, 1289 const SmallVectorImpl<ISD::InputArg> &Ins, 1290 SelectionDAG& DAG) const { 1291 // Conservative default: no calls are eligible. 1292 return false; 1293 } 1294 1295 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1296 /// it exists. Skip a possible ISD::TokenFactor. 1297 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1298 unsigned TailCallNodeOpCode) { 1299 if (Chain.getOpcode() == TailCallNodeOpCode) { 1300 return Chain; 1301 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1302 if (Chain.getNumOperands() && 1303 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1304 return Chain.getOperand(0); 1305 } 1306 return Chain; 1307 } 1308 1309 /// getTargetNodeName() - This method returns the name of a target specific 1310 /// DAG node. 1311 virtual const char *getTargetNodeName(unsigned Opcode) const; 1312 1313 /// createFastISel - This method returns a target specific FastISel object, 1314 /// or null if the target does not support "fast" ISel. 1315 virtual FastISel * 1316 createFastISel(MachineFunction &, 1317 MachineModuleInfo *, DwarfWriter *, 1318 DenseMap<const Value *, unsigned> &, 1319 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1320 DenseMap<const AllocaInst *, int> & 1321#ifndef NDEBUG 1322 , SmallSet<Instruction*, 8> &CatchInfoLost 1323#endif 1324 ) { 1325 return 0; 1326 } 1327 1328 //===--------------------------------------------------------------------===// 1329 // Inline Asm Support hooks 1330 // 1331 1332 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1333 /// call to be explicit llvm code if it wants to. This is useful for 1334 /// turning simple inline asms into LLVM intrinsics, which gives the 1335 /// compiler more information about the behavior of the code. 1336 virtual bool ExpandInlineAsm(CallInst *CI) const { 1337 return false; 1338 } 1339 1340 enum ConstraintType { 1341 C_Register, // Constraint represents specific register(s). 1342 C_RegisterClass, // Constraint represents any of register(s) in class. 1343 C_Memory, // Memory constraint. 1344 C_Other, // Something else. 1345 C_Unknown // Unsupported constraint. 1346 }; 1347 1348 /// AsmOperandInfo - This contains information for each constraint that we are 1349 /// lowering. 1350 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1351 /// ConstraintCode - This contains the actual string for the code, like "m". 1352 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1353 /// most closely matches the operand. 1354 std::string ConstraintCode; 1355 1356 /// ConstraintType - Information about the constraint code, e.g. Register, 1357 /// RegisterClass, Memory, Other, Unknown. 1358 TargetLowering::ConstraintType ConstraintType; 1359 1360 /// CallOperandval - If this is the result output operand or a 1361 /// clobber, this is null, otherwise it is the incoming operand to the 1362 /// CallInst. This gets modified as the asm is processed. 1363 Value *CallOperandVal; 1364 1365 /// ConstraintVT - The ValueType for the operand value. 1366 EVT ConstraintVT; 1367 1368 /// isMatchingInputConstraint - Return true of this is an input operand that 1369 /// is a matching constraint like "4". 1370 bool isMatchingInputConstraint() const; 1371 1372 /// getMatchedOperand - If this is an input matching constraint, this method 1373 /// returns the output operand it matches. 1374 unsigned getMatchedOperand() const; 1375 1376 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1377 : InlineAsm::ConstraintInfo(info), 1378 ConstraintType(TargetLowering::C_Unknown), 1379 CallOperandVal(0), ConstraintVT(MVT::Other) { 1380 } 1381 }; 1382 1383 /// ComputeConstraintToUse - Determines the constraint code and constraint 1384 /// type to use for the specific AsmOperandInfo, setting 1385 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1386 /// being passed in is available, it can be passed in as Op, otherwise an 1387 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1388 /// constraint of the inline asm instruction being processed is 'm'. 1389 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1390 SDValue Op, 1391 bool hasMemory, 1392 SelectionDAG *DAG = 0) const; 1393 1394 /// getConstraintType - Given a constraint, return the type of constraint it 1395 /// is for this target. 1396 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1397 1398 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1399 /// return a list of registers that can be used to satisfy the constraint. 1400 /// This should only be used for C_RegisterClass constraints. 1401 virtual std::vector<unsigned> 1402 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1403 EVT VT) const; 1404 1405 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1406 /// {edx}), return the register number and the register class for the 1407 /// register. 1408 /// 1409 /// Given a register class constraint, like 'r', if this corresponds directly 1410 /// to an LLVM register class, return a register of 0 and the register class 1411 /// pointer. 1412 /// 1413 /// This should only be used for C_Register constraints. On error, 1414 /// this returns a register number of 0 and a null register class pointer.. 1415 virtual std::pair<unsigned, const TargetRegisterClass*> 1416 getRegForInlineAsmConstraint(const std::string &Constraint, 1417 EVT VT) const; 1418 1419 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1420 /// with another that has more specific requirements based on the type of the 1421 /// corresponding operand. This returns null if there is no replacement to 1422 /// make. 1423 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1424 1425 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1426 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1427 /// it means one of the asm constraint of the inline asm instruction being 1428 /// processed is 'm'. 1429 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1430 bool hasMemory, 1431 std::vector<SDValue> &Ops, 1432 SelectionDAG &DAG) const; 1433 1434 //===--------------------------------------------------------------------===// 1435 // Scheduler hooks 1436 // 1437 1438 // EmitInstrWithCustomInserter - This method should be implemented by targets 1439 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1440 // instructions are special in various ways, which require special support to 1441 // insert. The specified MachineInstr is created but not inserted into any 1442 // basic blocks, and the scheduler passes ownership of it to this method. 1443 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1444 MachineBasicBlock *MBB, 1445 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 1446 1447 //===--------------------------------------------------------------------===// 1448 // Addressing mode description hooks (used by LSR etc). 1449 // 1450 1451 /// AddrMode - This represents an addressing mode of: 1452 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1453 /// If BaseGV is null, there is no BaseGV. 1454 /// If BaseOffs is zero, there is no base offset. 1455 /// If HasBaseReg is false, there is no base register. 1456 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1457 /// no scale. 1458 /// 1459 struct AddrMode { 1460 GlobalValue *BaseGV; 1461 int64_t BaseOffs; 1462 bool HasBaseReg; 1463 int64_t Scale; 1464 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1465 }; 1466 1467 /// isLegalAddressingMode - Return true if the addressing mode represented by 1468 /// AM is legal for this target, for a load/store of the specified type. 1469 /// The type may be VoidTy, in which case only return true if the addressing 1470 /// mode is legal for a load/store of any legal type. 1471 /// TODO: Handle pre/postinc as well. 1472 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1473 1474 /// isTruncateFree - Return true if it's free to truncate a value of 1475 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1476 /// register EAX to i16 by referencing its sub-register AX. 1477 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1478 return false; 1479 } 1480 1481 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1482 return false; 1483 } 1484 1485 /// isZExtFree - Return true if any actual instruction that defines a 1486 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 1487 /// register. This does not necessarily include registers defined in 1488 /// unknown ways, such as incoming arguments, or copies from unknown 1489 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1490 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1491 /// all instructions that define 32-bit values implicit zero-extend the 1492 /// result out to 64 bits. 1493 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1494 return false; 1495 } 1496 1497 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1498 return false; 1499 } 1500 1501 /// isNarrowingProfitable - Return true if it's profitable to narrow 1502 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1503 /// from i32 to i8 but not from i32 to i16. 1504 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1505 return false; 1506 } 1507 1508 //===--------------------------------------------------------------------===// 1509 // Div utility functions 1510 // 1511 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1512 std::vector<SDNode*>* Created) const; 1513 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1514 std::vector<SDNode*>* Created) const; 1515 1516 1517 //===--------------------------------------------------------------------===// 1518 // Runtime Library hooks 1519 // 1520 1521 /// setLibcallName - Rename the default libcall routine name for the specified 1522 /// libcall. 1523 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1524 LibcallRoutineNames[Call] = Name; 1525 } 1526 1527 /// getLibcallName - Get the libcall routine name for the specified libcall. 1528 /// 1529 const char *getLibcallName(RTLIB::Libcall Call) const { 1530 return LibcallRoutineNames[Call]; 1531 } 1532 1533 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1534 /// result of the comparison libcall against zero. 1535 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1536 CmpLibcallCCs[Call] = CC; 1537 } 1538 1539 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1540 /// the comparison libcall against zero. 1541 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1542 return CmpLibcallCCs[Call]; 1543 } 1544 1545 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1546 /// specified libcall. 1547 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1548 LibcallCallingConvs[Call] = CC; 1549 } 1550 1551 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1552 /// specified libcall. 1553 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1554 return LibcallCallingConvs[Call]; 1555 } 1556 1557private: 1558 TargetMachine &TM; 1559 const TargetData *TD; 1560 TargetLoweringObjectFile &TLOF; 1561 1562 /// PointerTy - The type to use for pointers, usually i32 or i64. 1563 /// 1564 MVT PointerTy; 1565 1566 /// IsLittleEndian - True if this is a little endian target. 1567 /// 1568 bool IsLittleEndian; 1569 1570 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1571 /// 1572 bool UsesGlobalOffsetTable; 1573 1574 /// SelectIsExpensive - Tells the code generator not to expand operations 1575 /// into sequences that use the select operations if possible. 1576 bool SelectIsExpensive; 1577 1578 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1579 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1580 /// a real cost model is in place. If we ever optimize for size, this will be 1581 /// set to true unconditionally. 1582 bool IntDivIsCheap; 1583 1584 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1585 /// srl/add/sra for a signed divide by power of two, and let the target handle 1586 /// it. 1587 bool Pow2DivIsCheap; 1588 1589 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1590 /// llvm.setjmp. Defaults to false. 1591 bool UseUnderscoreSetJmp; 1592 1593 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1594 /// llvm.longjmp. Defaults to false. 1595 bool UseUnderscoreLongJmp; 1596 1597 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1598 /// PointerTy is. 1599 MVT ShiftAmountTy; 1600 1601 /// BooleanContents - Information about the contents of the high-bits in 1602 /// boolean values held in a type wider than i1. See getBooleanContents. 1603 BooleanContent BooleanContents; 1604 1605 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1606 /// total cycles or lowest register usage. 1607 SchedPreference SchedPreferenceInfo; 1608 1609 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1610 unsigned JumpBufSize; 1611 1612 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1613 /// buffers 1614 unsigned JumpBufAlignment; 1615 1616 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1617 /// if-converted. 1618 unsigned IfCvtBlockSizeLimit; 1619 1620 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1621 /// duplicated during if-conversion. 1622 unsigned IfCvtDupBlockSizeLimit; 1623 1624 /// PrefLoopAlignment - The perferred loop alignment. 1625 /// 1626 unsigned PrefLoopAlignment; 1627 1628 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1629 /// specifies the register that llvm.savestack/llvm.restorestack should save 1630 /// and restore. 1631 unsigned StackPointerRegisterToSaveRestore; 1632 1633 /// ExceptionPointerRegister - If set to a physical register, this specifies 1634 /// the register that receives the exception address on entry to a landing 1635 /// pad. 1636 unsigned ExceptionPointerRegister; 1637 1638 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1639 /// the register that receives the exception typeid on entry to a landing 1640 /// pad. 1641 unsigned ExceptionSelectorRegister; 1642 1643 /// RegClassForVT - This indicates the default register class to use for 1644 /// each ValueType the target supports natively. 1645 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1646 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1647 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1648 1649 /// TransformToType - For any value types we are promoting or expanding, this 1650 /// contains the value type that we are changing to. For Expanded types, this 1651 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1652 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1653 /// by the system, this holds the same type (e.g. i32 -> i32). 1654 EVT TransformToType[MVT::LAST_VALUETYPE]; 1655 1656 /// OpActions - For each operation and each value type, keep a LegalizeAction 1657 /// that indicates how instruction selection should deal with the operation. 1658 /// Most operations are Legal (aka, supported natively by the target), but 1659 /// operations that are not should be described. Note that operations on 1660 /// non-legal value types are not described here. 1661 /// This array is accessed using VT.getSimpleVT(), so it is subject to 1662 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits. 1663 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END]; 1664 1665 /// LoadExtActions - For each load of load extension type and each value type, 1666 /// keep a LegalizeAction that indicates how instruction selection should deal 1667 /// with the load. 1668 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1669 1670 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1671 /// indicates how instruction selection should deal with the store. 1672 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1673 1674 /// IndexedModeActions - For each indexed mode and each value type, 1675 /// keep a pair of LegalizeAction that indicates how instruction 1676 /// selection should deal with the load / store. The first 1677 /// dimension is now the value_type for the reference. The second 1678 /// dimension is the load [0] vs. store[1]. The third dimension 1679 /// represents the various modes for load store. 1680 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE]; 1681 1682 /// ConvertActions - For each conversion from source type to destination type, 1683 /// keep a LegalizeAction that indicates how instruction selection should 1684 /// deal with the conversion. 1685 /// Currently, this is used only for floating->floating conversions 1686 /// (FP_EXTEND and FP_ROUND). 1687 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1688 1689 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1690 /// LegalizeAction that indicates how instruction selection should 1691 /// deal with the condition code. 1692 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1693 1694 ValueTypeActionImpl ValueTypeActions; 1695 1696 std::vector<APFloat> LegalFPImmediates; 1697 1698 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1699 1700 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1701 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1702 /// which sets a bit in this array. 1703 unsigned char 1704 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1705 1706 /// PromoteToType - For operations that must be promoted to a specific type, 1707 /// this holds the destination type. This map should be sparse, so don't hold 1708 /// it as an array. 1709 /// 1710 /// Targets add entries to this map with AddPromotedToType(..), clients access 1711 /// this with getTypeToPromoteTo(..). 1712 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1713 PromoteToType; 1714 1715 /// LibcallRoutineNames - Stores the name each libcall. 1716 /// 1717 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1718 1719 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1720 /// of each of the comparison libcall against zero. 1721 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1722 1723 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1724 /// libcall. 1725 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1726 1727protected: 1728 /// When lowering \@llvm.memset this field specifies the maximum number of 1729 /// store operations that may be substituted for the call to memset. Targets 1730 /// must set this value based on the cost threshold for that target. Targets 1731 /// should assume that the memset will be done using as many of the largest 1732 /// store operations first, followed by smaller ones, if necessary, per 1733 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1734 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1735 /// store. This only applies to setting a constant array of a constant size. 1736 /// @brief Specify maximum number of store instructions per memset call. 1737 unsigned maxStoresPerMemset; 1738 1739 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1740 /// store operations that may be substituted for a call to memcpy. Targets 1741 /// must set this value based on the cost threshold for that target. Targets 1742 /// should assume that the memcpy will be done using as many of the largest 1743 /// store operations first, followed by smaller ones, if necessary, per 1744 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1745 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1746 /// and one 1-byte store. This only applies to copying a constant array of 1747 /// constant size. 1748 /// @brief Specify maximum bytes of store instructions per memcpy call. 1749 unsigned maxStoresPerMemcpy; 1750 1751 /// When lowering \@llvm.memmove this field specifies the maximum number of 1752 /// store instructions that may be substituted for a call to memmove. Targets 1753 /// must set this value based on the cost threshold for that target. Targets 1754 /// should assume that the memmove will be done using as many of the largest 1755 /// store operations first, followed by smaller ones, if necessary, per 1756 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1757 /// with 8-bit alignment would result in nine 1-byte stores. This only 1758 /// applies to copying a constant array of constant size. 1759 /// @brief Specify maximum bytes of store instructions per memmove call. 1760 unsigned maxStoresPerMemmove; 1761 1762 /// This field specifies whether the target can benefit from code placement 1763 /// optimization. 1764 bool benefitFromCodePlacementOpt; 1765}; 1766} // end llvm namespace 1767 1768#endif 1769