TargetMachine.h revision 3813d8adf3788dd01a4cb9db01c122cd5e6a13b9
1//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TargetMachine and LLVMTargetMachine classes. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETMACHINE_H 15#define LLVM_TARGET_TARGETMACHINE_H 16 17#include "llvm/Target/TargetInstrItineraries.h" 18#include <cassert> 19#include <string> 20 21namespace llvm { 22 23class Target; 24class MCAsmInfo; 25class TargetData; 26class TargetSubtarget; 27class TargetInstrInfo; 28class TargetIntrinsicInfo; 29class TargetJITInfo; 30class TargetLowering; 31class TargetFrameInfo; 32class JITCodeEmitter; 33class TargetRegisterInfo; 34class PassManagerBase; 35class PassManager; 36class Pass; 37class TargetELFWriterInfo; 38class formatted_raw_ostream; 39 40// Relocation model types. 41namespace Reloc { 42 enum Model { 43 Default, 44 Static, 45 PIC_, // Cannot be named PIC due to collision with -DPIC 46 DynamicNoPIC 47 }; 48} 49 50// Code model types. 51namespace CodeModel { 52 enum Model { 53 Default, 54 Small, 55 Kernel, 56 Medium, 57 Large 58 }; 59} 60 61// Code generation optimization level. 62namespace CodeGenOpt { 63 enum Level { 64 None, // -O0 65 Less, // -O1 66 Default, // -O2, -Os 67 Aggressive // -O3 68 }; 69} 70 71// Specify if we should encode the LSDA pointer in the FDE as 4- or 8-bytes. 72namespace DwarfLSDAEncoding { 73 enum Encoding { 74 Default, 75 FourByte, 76 EightByte 77 }; 78} 79 80//===----------------------------------------------------------------------===// 81/// 82/// TargetMachine - Primary interface to the complete machine description for 83/// the target machine. All target-specific information should be accessible 84/// through this interface. 85/// 86class TargetMachine { 87 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT 88 void operator=(const TargetMachine &); // DO NOT IMPLEMENT 89protected: // Can only create subclasses. 90 TargetMachine(const Target &); 91 92 /// getSubtargetImpl - virtual method implemented by subclasses that returns 93 /// a reference to that target's TargetSubtarget-derived member variable. 94 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; } 95 96 /// TheTarget - The Target that this machine was created for. 97 const Target &TheTarget; 98 99 /// AsmInfo - Contains target specific asm information. 100 /// 101 const MCAsmInfo *AsmInfo; 102 103public: 104 virtual ~TargetMachine(); 105 106 const Target &getTarget() const { return TheTarget; } 107 108 // Interfaces to the major aspects of target machine information: 109 // -- Instruction opcode and operand information 110 // -- Pipelines and scheduling information 111 // -- Stack frame information 112 // -- Selection DAG lowering information 113 // 114 virtual const TargetInstrInfo *getInstrInfo() const { return 0; } 115 virtual const TargetFrameInfo *getFrameInfo() const { return 0; } 116 virtual TargetLowering *getTargetLowering() const { return 0; } 117 virtual const TargetData *getTargetData() const { return 0; } 118 119 /// getMCAsmInfo - Return target specific asm information. 120 /// 121 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } 122 123 /// getSubtarget - This method returns a pointer to the specified type of 124 /// TargetSubtarget. In debug builds, it verifies that the object being 125 /// returned is of the correct type. 126 template<typename STC> const STC &getSubtarget() const { 127 return *static_cast<const STC*>(getSubtargetImpl()); 128 } 129 130 /// getRegisterInfo - If register information is available, return it. If 131 /// not, return null. This is kept separate from RegInfo until RegInfo has 132 /// details of graph coloring register allocation removed from it. 133 /// 134 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } 135 136 /// getIntrinsicInfo - If intrinsic information is available, return it. If 137 /// not, return null. 138 /// 139 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } 140 141 /// getJITInfo - If this target supports a JIT, return information for it, 142 /// otherwise return null. 143 /// 144 virtual TargetJITInfo *getJITInfo() { return 0; } 145 146 /// getInstrItineraryData - Returns instruction itinerary data for the target 147 /// or specific subtarget. 148 /// 149 virtual const InstrItineraryData getInstrItineraryData() const { 150 return InstrItineraryData(); 151 } 152 153 /// getELFWriterInfo - If this target supports an ELF writer, return 154 /// information for it, otherwise return null. 155 /// 156 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; } 157 158 /// getRelocationModel - Returns the code generation relocation model. The 159 /// choices are static, PIC, and dynamic-no-pic, and target default. 160 static Reloc::Model getRelocationModel(); 161 162 /// setRelocationModel - Sets the code generation relocation model. 163 /// 164 static void setRelocationModel(Reloc::Model Model); 165 166 /// getCodeModel - Returns the code model. The choices are small, kernel, 167 /// medium, large, and target default. 168 static CodeModel::Model getCodeModel(); 169 170 /// setCodeModel - Sets the code model. 171 /// 172 static void setCodeModel(CodeModel::Model Model); 173 174 /// getAsmVerbosityDefault - Returns the default value of asm verbosity. 175 /// 176 static bool getAsmVerbosityDefault(); 177 178 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default 179 /// is false. 180 static void setAsmVerbosityDefault(bool); 181 182 /// getLSDAEncoding - Returns the LSDA pointer encoding. The choices are 183 /// 4-byte, 8-byte, and target default. The CIE is hard-coded to indicate that 184 /// the LSDA pointer in the FDE section is an "sdata4", and should be encoded 185 /// as a 4-byte pointer by default. However, some systems may require a 186 /// different size due to bugs or other conditions. We will default to a 187 /// 4-byte encoding unless the system tells us otherwise. 188 /// 189 /// FIXME: This call-back isn't good! We should be using the correct encoding 190 /// regardless of the system. However, there are some systems which have bugs 191 /// that prevent this from occuring. 192 virtual DwarfLSDAEncoding::Encoding getLSDAEncoding() const { 193 return DwarfLSDAEncoding::Default; 194 } 195 196 /// CodeGenFileType - These enums are meant to be passed into 197 /// addPassesToEmitFile to indicate what type of file to emit, and returned by 198 /// it to indicate what type of file could actually be made. 199 enum CodeGenFileType { 200 CGFT_AssemblyFile, 201 CGFT_ObjectFile, 202 CGFT_DynamicLibrary, 203 CGFT_ErrorOccurred 204 }; 205 206 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 207 /// on this target. User flag overrides. 208 virtual bool getEnableTailMergeDefault() const { return true; } 209 210 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 211 /// specified file emitted. Typically this will involve several steps of code 212 /// generation. 213 /// This method should return InvalidFile if emission of this file type 214 /// is not supported. 215 /// 216 virtual CodeGenFileType addPassesToEmitFile(PassManagerBase &, 217 formatted_raw_ostream &, 218 CodeGenFileType Filetype, 219 CodeGenOpt::Level) { 220 return CGFT_ErrorOccurred; 221 } 222 223 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 224 /// get machine code emitted. This uses a JITCodeEmitter object to handle 225 /// actually outputting the machine code and resolving things like the address 226 /// of functions. This method returns true if machine code emission is 227 /// not supported. 228 /// 229 virtual bool addPassesToEmitMachineCode(PassManagerBase &, 230 JITCodeEmitter &, 231 CodeGenOpt::Level) { 232 return true; 233 } 234 235 /// addPassesToEmitWholeFile - This method can be implemented by targets that 236 /// require having the entire module at once. This is not recommended, do not 237 /// use this. 238 virtual bool WantsWholeFile() const { return false; } 239 virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &, 240 CodeGenFileType, 241 CodeGenOpt::Level) { 242 return true; 243 } 244}; 245 246/// LLVMTargetMachine - This class describes a target machine that is 247/// implemented with the LLVM target-independent code generator. 248/// 249class LLVMTargetMachine : public TargetMachine { 250protected: // Can only create subclasses. 251 LLVMTargetMachine(const Target &T, const std::string &TargetTriple); 252 253 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for 254 /// both emitting to assembly files or machine code output. 255 /// 256 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level); 257 258private: 259 virtual void setCodeModelForJIT(); 260 virtual void setCodeModelForStatic(); 261 262public: 263 264 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 265 /// specified file emitted. Typically this will involve several steps of code 266 /// generation. If OptLevel is None, the code generator should emit code as 267 /// fast as possible, though the generated code may be less efficient. This 268 /// method should return CGFT_ErrorOccurred if emission of this file type is 269 /// not supported. 270 /// 271 /// The default implementation of this method adds components from the 272 /// LLVM retargetable code generator, invoking the methods below to get 273 /// target-specific passes in standard locations. 274 /// 275 virtual CodeGenFileType addPassesToEmitFile(PassManagerBase &PM, 276 formatted_raw_ostream &Out, 277 CodeGenFileType FileType, 278 CodeGenOpt::Level); 279 280 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 281 /// get machine code emitted. This uses a JITCodeEmitter object to handle 282 /// actually outputting the machine code and resolving things like the address 283 /// of functions. This method returns true if machine code emission is 284 /// not supported. 285 /// 286 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, 287 JITCodeEmitter &MCE, 288 CodeGenOpt::Level); 289 290 /// Target-Independent Code Generator Pass Configuration Options. 291 292 /// addInstSelector - This method should add any "last minute" LLVM->LLVM 293 /// passes, then install an instruction selector pass, which converts from 294 /// LLVM code to machine instructions. 295 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { 296 return true; 297 } 298 299 /// addPreRegAlloc - This method may be implemented by targets that want to 300 /// run passes immediately before register allocation. This should return 301 /// true if -print-machineinstrs should print after these passes. 302 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 303 return false; 304 } 305 306 /// addPostRegAlloc - This method may be implemented by targets that want 307 /// to run passes after register allocation but before prolog-epilog 308 /// insertion. This should return true if -print-machineinstrs should print 309 /// after these passes. 310 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 311 return false; 312 } 313 314 /// addPreSched2 - This method may be implemented by targets that want to 315 /// run passes after prolog-epilog insertion and before the second instruction 316 /// scheduling pass. This should return true if -print-machineinstrs should 317 /// print after these passes. 318 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) { 319 return false; 320 } 321 322 /// addPreEmitPass - This pass may be implemented by targets that want to run 323 /// passes immediately before machine code is emitted. This should return 324 /// true if -print-machineinstrs should print out the code after the passes. 325 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { 326 return false; 327 } 328 329 330 /// addCodeEmitter - This pass should be overridden by the target to add a 331 /// code emitter, if supported. If this is not supported, 'true' should be 332 /// returned. 333 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 334 JITCodeEmitter &) { 335 return true; 336 } 337 338 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 339 /// on this target. User flag overrides. 340 virtual bool getEnableTailMergeDefault() const { return true; } 341}; 342 343} // End llvm namespace 344 345#endif 346