TargetMachine.h revision 4db361395b762b1de6059827a6fabb1952373f98
1//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TargetMachine and LLVMTargetMachine classes. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETMACHINE_H 15#define LLVM_TARGET_TARGETMACHINE_H 16 17#include "llvm/Target/TargetInstrItineraries.h" 18#include <cassert> 19#include <string> 20 21namespace llvm { 22 23class Target; 24class MCAsmInfo; 25class TargetData; 26class TargetSubtarget; 27class TargetInstrInfo; 28class TargetIntrinsicInfo; 29class TargetJITInfo; 30class TargetLowering; 31class TargetFrameInfo; 32class MachineCodeEmitter; 33class JITCodeEmitter; 34class ObjectCodeEmitter; 35class TargetRegisterInfo; 36class PassManagerBase; 37class PassManager; 38class Pass; 39class TargetELFWriterInfo; 40class formatted_raw_ostream; 41 42// Relocation model types. 43namespace Reloc { 44 enum Model { 45 Default, 46 Static, 47 PIC_, // Cannot be named PIC due to collision with -DPIC 48 DynamicNoPIC 49 }; 50} 51 52// Code model types. 53namespace CodeModel { 54 enum Model { 55 Default, 56 Small, 57 Kernel, 58 Medium, 59 Large 60 }; 61} 62 63namespace FileModel { 64 enum Model { 65 Error, 66 None, 67 AsmFile, 68 MachOFile, 69 ElfFile 70 }; 71} 72 73// Code generation optimization level. 74namespace CodeGenOpt { 75 enum Level { 76 None, // -O0 77 Less, // -O1 78 Default, // -O2, -Os 79 Aggressive // -O3 80 }; 81} 82 83// Specify if we should encode the LSDA pointer in the FDE as 4- or 8-bytes. 84namespace DwarfLSDAEncoding { 85 enum Encoding { 86 Default, 87 FourByte, 88 EightByte 89 }; 90} 91 92//===----------------------------------------------------------------------===// 93/// 94/// TargetMachine - Primary interface to the complete machine description for 95/// the target machine. All target-specific information should be accessible 96/// through this interface. 97/// 98class TargetMachine { 99 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT 100 void operator=(const TargetMachine &); // DO NOT IMPLEMENT 101protected: // Can only create subclasses. 102 TargetMachine(const Target &); 103 104 /// getSubtargetImpl - virtual method implemented by subclasses that returns 105 /// a reference to that target's TargetSubtarget-derived member variable. 106 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; } 107 108 /// TheTarget - The Target that this machine was created for. 109 const Target &TheTarget; 110 111 /// AsmInfo - Contains target specific asm information. 112 /// 113 const MCAsmInfo *AsmInfo; 114 115public: 116 virtual ~TargetMachine(); 117 118 const Target &getTarget() const { return TheTarget; } 119 120 // Interfaces to the major aspects of target machine information: 121 // -- Instruction opcode and operand information 122 // -- Pipelines and scheduling information 123 // -- Stack frame information 124 // -- Selection DAG lowering information 125 // 126 virtual const TargetInstrInfo *getInstrInfo() const { return 0; } 127 virtual const TargetFrameInfo *getFrameInfo() const { return 0; } 128 virtual TargetLowering *getTargetLowering() const { return 0; } 129 virtual const TargetData *getTargetData() const { return 0; } 130 131 /// getMCAsmInfo - Return target specific asm information. 132 /// 133 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } 134 135 /// getSubtarget - This method returns a pointer to the specified type of 136 /// TargetSubtarget. In debug builds, it verifies that the object being 137 /// returned is of the correct type. 138 template<typename STC> const STC &getSubtarget() const { 139 return *static_cast<const STC*>(getSubtargetImpl()); 140 } 141 142 /// getRegisterInfo - If register information is available, return it. If 143 /// not, return null. This is kept separate from RegInfo until RegInfo has 144 /// details of graph coloring register allocation removed from it. 145 /// 146 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } 147 148 /// getIntrinsicInfo - If intrinsic information is available, return it. If 149 /// not, return null. 150 /// 151 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } 152 153 /// getJITInfo - If this target supports a JIT, return information for it, 154 /// otherwise return null. 155 /// 156 virtual TargetJITInfo *getJITInfo() { return 0; } 157 158 /// getInstrItineraryData - Returns instruction itinerary data for the target 159 /// or specific subtarget. 160 /// 161 virtual const InstrItineraryData getInstrItineraryData() const { 162 return InstrItineraryData(); 163 } 164 165 /// getELFWriterInfo - If this target supports an ELF writer, return 166 /// information for it, otherwise return null. 167 /// 168 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; } 169 170 /// getRelocationModel - Returns the code generation relocation model. The 171 /// choices are static, PIC, and dynamic-no-pic, and target default. 172 static Reloc::Model getRelocationModel(); 173 174 /// setRelocationModel - Sets the code generation relocation model. 175 /// 176 static void setRelocationModel(Reloc::Model Model); 177 178 /// getCodeModel - Returns the code model. The choices are small, kernel, 179 /// medium, large, and target default. 180 static CodeModel::Model getCodeModel(); 181 182 /// setCodeModel - Sets the code model. 183 /// 184 static void setCodeModel(CodeModel::Model Model); 185 186 /// getAsmVerbosityDefault - Returns the default value of asm verbosity. 187 /// 188 static bool getAsmVerbosityDefault(); 189 190 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default 191 /// is false. 192 static void setAsmVerbosityDefault(bool); 193 194 /// getLSDAEncoding - Returns the LSDA pointer encoding. The choices are 195 /// 4-byte, 8-byte, and target default. The CIE is hard-coded to indicate that 196 /// the LSDA pointer in the FDE section is an "sdata4", and should be encoded 197 /// as a 4-byte pointer by default. However, some systems may require a 198 /// different size due to bugs or other conditions. We will default to a 199 /// 4-byte encoding unless the system tells us otherwise. 200 /// 201 /// FIXME: This call-back isn't good! We should be using the correct encoding 202 /// regardless of the system. However, there are some systems which have bugs 203 /// that prevent this from occuring. 204 virtual DwarfLSDAEncoding::Encoding getLSDAEncoding() const { 205 return DwarfLSDAEncoding::Default; 206 } 207 208 /// CodeGenFileType - These enums are meant to be passed into 209 /// addPassesToEmitFile to indicate what type of file to emit. 210 enum CodeGenFileType { 211 AssemblyFile, ObjectFile, DynamicLibrary 212 }; 213 214 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 215 /// on this target. User flag overrides. 216 virtual bool getEnableTailMergeDefault() const { return true; } 217 218 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 219 /// specified file emitted. Typically this will involve several steps of code 220 /// generation. 221 /// This method should return FileModel::Error if emission of this file type 222 /// is not supported. 223 /// 224 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &, 225 formatted_raw_ostream &, 226 CodeGenFileType, 227 CodeGenOpt::Level) { 228 return FileModel::None; 229 } 230 231 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 232 /// get machine code emitted. This uses a MachineCodeEmitter object to handle 233 /// actually outputting the machine code and resolving things like the address 234 /// of functions. This method returns true if machine code emission is 235 /// not supported. 236 /// 237 virtual bool addPassesToEmitMachineCode(PassManagerBase &, 238 JITCodeEmitter &, 239 CodeGenOpt::Level) { 240 return true; 241 } 242 243 /// addPassesToEmitWholeFile - This method can be implemented by targets that 244 /// require having the entire module at once. This is not recommended, do not 245 /// use this. 246 virtual bool WantsWholeFile() const { return false; } 247 virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &, 248 CodeGenFileType, 249 CodeGenOpt::Level) { 250 return true; 251 } 252}; 253 254/// LLVMTargetMachine - This class describes a target machine that is 255/// implemented with the LLVM target-independent code generator. 256/// 257class LLVMTargetMachine : public TargetMachine { 258protected: // Can only create subclasses. 259 LLVMTargetMachine(const Target &T, const std::string &TargetTriple); 260 261 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for 262 /// both emitting to assembly files or machine code output. 263 /// 264 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level); 265 266private: 267 virtual void setCodeModelForJIT(); 268 virtual void setCodeModelForStatic(); 269 270public: 271 272 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 273 /// specified file emitted. Typically this will involve several steps of code 274 /// generation. If OptLevel is None, the code generator should emit code as fast 275 /// as possible, though the generated code may be less efficient. This method 276 /// should return FileModel::Error if emission of this file type is not 277 /// supported. 278 /// 279 /// The default implementation of this method adds components from the 280 /// LLVM retargetable code generator, invoking the methods below to get 281 /// target-specific passes in standard locations. 282 /// 283 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM, 284 formatted_raw_ostream &Out, 285 CodeGenFileType FileType, 286 CodeGenOpt::Level); 287 288 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 289 /// get machine code emitted. This uses a MachineCodeEmitter object to handle 290 /// actually outputting the machine code and resolving things like the address 291 /// of functions. This method returns true if machine code emission is 292 /// not supported. 293 /// 294 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, 295 JITCodeEmitter &MCE, 296 CodeGenOpt::Level); 297 298 /// Target-Independent Code Generator Pass Configuration Options. 299 300 /// addInstSelector - This method should add any "last minute" LLVM->LLVM 301 /// passes, then install an instruction selector pass, which converts from 302 /// LLVM code to machine instructions. 303 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { 304 return true; 305 } 306 307 /// addPreRegAlloc - This method may be implemented by targets that want to 308 /// run passes immediately before register allocation. This should return 309 /// true if -print-machineinstrs should print after these passes. 310 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 311 return false; 312 } 313 314 /// addPostRegAlloc - This method may be implemented by targets that want 315 /// to run passes after register allocation but before prolog-epilog 316 /// insertion. This should return true if -print-machineinstrs should print 317 /// after these passes. 318 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 319 return false; 320 } 321 322 /// addPreSched2 - This method may be implemented by targets that want to 323 /// run passes after prolog-epilog insertion and before the second instruction 324 /// scheduling pass. This should return true if -print-machineinstrs should 325 /// print after these passes. 326 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) { 327 return false; 328 } 329 330 /// addPreEmitPass - This pass may be implemented by targets that want to run 331 /// passes immediately before machine code is emitted. This should return 332 /// true if -print-machineinstrs should print out the code after the passes. 333 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { 334 return false; 335 } 336 337 338 /// addCodeEmitter - This pass should be overridden by the target to add a 339 /// code emitter, if supported. If this is not supported, 'true' should be 340 /// returned. 341 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 342 MachineCodeEmitter &) { 343 return true; 344 } 345 346 /// addCodeEmitter - This pass should be overridden by the target to add a 347 /// code emitter, if supported. If this is not supported, 'true' should be 348 /// returned. 349 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 350 JITCodeEmitter &) { 351 return true; 352 } 353 354 /// addSimpleCodeEmitter - This pass should be overridden by the target to add 355 /// a code emitter (without setting flags), if supported. If this is not 356 /// supported, 'true' should be returned. 357 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 358 MachineCodeEmitter &) { 359 return true; 360 } 361 362 /// addSimpleCodeEmitter - This pass should be overridden by the target to add 363 /// a code emitter (without setting flags), if supported. If this is not 364 /// supported, 'true' should be returned. 365 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 366 JITCodeEmitter &) { 367 return true; 368 } 369 370 /// addSimpleCodeEmitter - This pass should be overridden by the target to add 371 /// a code emitter (without setting flags), if supported. If this is not 372 /// supported, 'true' should be returned. 373 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 374 ObjectCodeEmitter &) { 375 return true; 376 } 377 378 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 379 /// on this target. User flag overrides. 380 virtual bool getEnableTailMergeDefault() const { return true; } 381}; 382 383} // End llvm namespace 384 385#endif 386