TargetMachine.h revision 70017e44cdba1946cc478ce1856a3e855a767e28
1//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TargetMachine and LLVMTargetMachine classes. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETMACHINE_H 15#define LLVM_TARGET_TARGETMACHINE_H 16 17#include "llvm/Target/TargetInstrItineraries.h" 18#include <cassert> 19#include <string> 20 21namespace llvm { 22 23class Target; 24class MCAsmInfo; 25class TargetData; 26class TargetSubtarget; 27class TargetInstrInfo; 28class TargetIntrinsicInfo; 29class TargetJITInfo; 30class TargetLowering; 31class TargetSelectionDAGInfo; 32class TargetFrameInfo; 33class JITCodeEmitter; 34class MCContext; 35class TargetRegisterInfo; 36class PassManagerBase; 37class PassManager; 38class Pass; 39class TargetELFWriterInfo; 40class formatted_raw_ostream; 41 42// Relocation model types. 43namespace Reloc { 44 enum Model { 45 Default, 46 Static, 47 PIC_, // Cannot be named PIC due to collision with -DPIC 48 DynamicNoPIC 49 }; 50} 51 52// Code model types. 53namespace CodeModel { 54 enum Model { 55 Default, 56 Small, 57 Kernel, 58 Medium, 59 Large 60 }; 61} 62 63// Code generation optimization level. 64namespace CodeGenOpt { 65 enum Level { 66 None, // -O0 67 Less, // -O1 68 Default, // -O2, -Os 69 Aggressive // -O3 70 }; 71} 72 73namespace Sched { 74 enum Preference { 75 None, // No preference 76 Latency, // Scheduling for shortest total latency. 77 RegPressure, // Scheduling for lowest register pressure. 78 Hybrid, // Scheduling for both latency and register pressure. 79 ILP // Scheduling for ILP in low register pressure mode. 80 }; 81} 82 83//===----------------------------------------------------------------------===// 84/// 85/// TargetMachine - Primary interface to the complete machine description for 86/// the target machine. All target-specific information should be accessible 87/// through this interface. 88/// 89class TargetMachine { 90 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT 91 void operator=(const TargetMachine &); // DO NOT IMPLEMENT 92protected: // Can only create subclasses. 93 TargetMachine(const Target &); 94 95 /// getSubtargetImpl - virtual method implemented by subclasses that returns 96 /// a reference to that target's TargetSubtarget-derived member variable. 97 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; } 98 99 /// TheTarget - The Target that this machine was created for. 100 const Target &TheTarget; 101 102 /// AsmInfo - Contains target specific asm information. 103 /// 104 const MCAsmInfo *AsmInfo; 105 106 unsigned MCRelaxAll : 1; 107 108public: 109 virtual ~TargetMachine(); 110 111 const Target &getTarget() const { return TheTarget; } 112 113 // Interfaces to the major aspects of target machine information: 114 // -- Instruction opcode and operand information 115 // -- Pipelines and scheduling information 116 // -- Stack frame information 117 // -- Selection DAG lowering information 118 // 119 virtual const TargetInstrInfo *getInstrInfo() const { return 0; } 120 virtual const TargetFrameInfo *getFrameInfo() const { return 0; } 121 virtual const TargetLowering *getTargetLowering() const { return 0; } 122 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; } 123 virtual const TargetData *getTargetData() const { return 0; } 124 125 /// getMCAsmInfo - Return target specific asm information. 126 /// 127 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } 128 129 /// getSubtarget - This method returns a pointer to the specified type of 130 /// TargetSubtarget. In debug builds, it verifies that the object being 131 /// returned is of the correct type. 132 template<typename STC> const STC &getSubtarget() const { 133 return *static_cast<const STC*>(getSubtargetImpl()); 134 } 135 136 /// getRegisterInfo - If register information is available, return it. If 137 /// not, return null. This is kept separate from RegInfo until RegInfo has 138 /// details of graph coloring register allocation removed from it. 139 /// 140 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } 141 142 /// getIntrinsicInfo - If intrinsic information is available, return it. If 143 /// not, return null. 144 /// 145 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } 146 147 /// getJITInfo - If this target supports a JIT, return information for it, 148 /// otherwise return null. 149 /// 150 virtual TargetJITInfo *getJITInfo() { return 0; } 151 152 /// getInstrItineraryData - Returns instruction itinerary data for the target 153 /// or specific subtarget. 154 /// 155 virtual const InstrItineraryData getInstrItineraryData() const { 156 return InstrItineraryData(); 157 } 158 159 /// getELFWriterInfo - If this target supports an ELF writer, return 160 /// information for it, otherwise return null. 161 /// 162 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; } 163 164 /// hasMCRelaxAll - Check whether all machine code instructions should be 165 /// relaxed. 166 bool hasMCRelaxAll() const { return MCRelaxAll; } 167 168 /// setMCRelaxAll - Set whether all machine code instructions should be 169 /// relaxed. 170 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; } 171 172 /// getRelocationModel - Returns the code generation relocation model. The 173 /// choices are static, PIC, and dynamic-no-pic, and target default. 174 static Reloc::Model getRelocationModel(); 175 176 /// setRelocationModel - Sets the code generation relocation model. 177 /// 178 static void setRelocationModel(Reloc::Model Model); 179 180 /// getCodeModel - Returns the code model. The choices are small, kernel, 181 /// medium, large, and target default. 182 static CodeModel::Model getCodeModel(); 183 184 /// setCodeModel - Sets the code model. 185 /// 186 static void setCodeModel(CodeModel::Model Model); 187 188 /// getAsmVerbosityDefault - Returns the default value of asm verbosity. 189 /// 190 static bool getAsmVerbosityDefault(); 191 192 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default 193 /// is false. 194 static void setAsmVerbosityDefault(bool); 195 196 /// getDataSections - Return true if data objects should be emitted into their 197 /// own section, corresponds to -fdata-sections. 198 static bool getDataSections(); 199 200 /// getFunctionSections - Return true if functions should be emitted into 201 /// their own section, corresponding to -ffunction-sections. 202 static bool getFunctionSections(); 203 204 /// setDataSections - Set if the data are emit into separate sections. 205 static void setDataSections(bool); 206 207 /// setFunctionSections - Set if the functions are emit into separate 208 /// sections. 209 static void setFunctionSections(bool); 210 211 /// CodeGenFileType - These enums are meant to be passed into 212 /// addPassesToEmitFile to indicate what type of file to emit, and returned by 213 /// it to indicate what type of file could actually be made. 214 enum CodeGenFileType { 215 CGFT_AssemblyFile, 216 CGFT_ObjectFile, 217 CGFT_Null // Do not emit any output. 218 }; 219 220 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 221 /// on this target. User flag overrides. 222 virtual bool getEnableTailMergeDefault() const { return true; } 223 224 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 225 /// specified file emitted. Typically this will involve several steps of code 226 /// generation. This method should return true if emission of this file type 227 /// is not supported, or false on success. 228 virtual bool addPassesToEmitFile(PassManagerBase &, 229 formatted_raw_ostream &, 230 CodeGenFileType, 231 CodeGenOpt::Level, 232 bool = true) { 233 return true; 234 } 235 236 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 237 /// get machine code emitted. This uses a JITCodeEmitter object to handle 238 /// actually outputting the machine code and resolving things like the address 239 /// of functions. This method returns true if machine code emission is 240 /// not supported. 241 /// 242 virtual bool addPassesToEmitMachineCode(PassManagerBase &, 243 JITCodeEmitter &, 244 CodeGenOpt::Level, 245 bool = true) { 246 return true; 247 } 248 249 /// addPassesToEmitMC - Add passes to the specified pass manager to get 250 /// machine code emitted with the MCJIT. This method returns true if machine 251 /// code is not supported. It fills the MCContext Ctx pointer which can be 252 /// used to build custom MCStreamer. 253 /// 254 virtual bool addPassesToEmitMC(PassManagerBase &, 255 MCContext *&, 256 CodeGenOpt::Level, 257 bool = true) { 258 return true; 259 } 260}; 261 262/// LLVMTargetMachine - This class describes a target machine that is 263/// implemented with the LLVM target-independent code generator. 264/// 265class LLVMTargetMachine : public TargetMachine { 266 std::string TargetTriple; 267 268protected: // Can only create subclasses. 269 LLVMTargetMachine(const Target &T, const std::string &TargetTriple); 270 271private: 272 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for 273 /// both emitting to assembly files or machine code output. 274 /// 275 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level, 276 bool DisableVerify, MCContext *&OutCtx); 277 278 virtual void setCodeModelForJIT(); 279 virtual void setCodeModelForStatic(); 280 281public: 282 283 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 284 /// specified file emitted. Typically this will involve several steps of code 285 /// generation. If OptLevel is None, the code generator should emit code as 286 /// fast as possible, though the generated code may be less efficient. 287 virtual bool addPassesToEmitFile(PassManagerBase &PM, 288 formatted_raw_ostream &Out, 289 CodeGenFileType FileType, 290 CodeGenOpt::Level, 291 bool DisableVerify = true); 292 293 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 294 /// get machine code emitted. This uses a JITCodeEmitter object to handle 295 /// actually outputting the machine code and resolving things like the address 296 /// of functions. This method returns true if machine code emission is 297 /// not supported. 298 /// 299 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, 300 JITCodeEmitter &MCE, 301 CodeGenOpt::Level, 302 bool DisableVerify = true); 303 304 /// addPassesToEmitMC - Add passes to the specified pass manager to get 305 /// machine code emitted with the MCJIT. This method returns true if machine 306 /// code is not supported. It fills the MCContext Ctx pointer which can be 307 /// used to build custom MCStreamer. 308 /// 309 virtual bool addPassesToEmitMC(PassManagerBase &PM, 310 MCContext *&Ctx, 311 CodeGenOpt::Level OptLevel, 312 bool DisableVerify = true); 313 314 /// Target-Independent Code Generator Pass Configuration Options. 315 316 /// addInstSelector - This method should add any "last minute" LLVM->LLVM 317 /// passes, then install an instruction selector pass, which converts from 318 /// LLVM code to machine instructions. 319 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { 320 return true; 321 } 322 323 /// addPreRegAlloc - This method may be implemented by targets that want to 324 /// run passes immediately before register allocation. This should return 325 /// true if -print-machineinstrs should print after these passes. 326 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 327 return false; 328 } 329 330 /// addPostRegAlloc - This method may be implemented by targets that want 331 /// to run passes after register allocation but before prolog-epilog 332 /// insertion. This should return true if -print-machineinstrs should print 333 /// after these passes. 334 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 335 return false; 336 } 337 338 /// addPreSched2 - This method may be implemented by targets that want to 339 /// run passes after prolog-epilog insertion and before the second instruction 340 /// scheduling pass. This should return true if -print-machineinstrs should 341 /// print after these passes. 342 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) { 343 return false; 344 } 345 346 /// addPreEmitPass - This pass may be implemented by targets that want to run 347 /// passes immediately before machine code is emitted. This should return 348 /// true if -print-machineinstrs should print out the code after the passes. 349 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { 350 return false; 351 } 352 353 354 /// addCodeEmitter - This pass should be overridden by the target to add a 355 /// code emitter, if supported. If this is not supported, 'true' should be 356 /// returned. 357 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 358 JITCodeEmitter &) { 359 return true; 360 } 361 362 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 363 /// on this target. User flag overrides. 364 virtual bool getEnableTailMergeDefault() const { return true; } 365}; 366 367} // End llvm namespace 368 369#endif 370