TargetRegisterInfo.h revision 255f89faee13dc491cb64fbeae3c763e7e2ea4e6
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/ADT/ArrayRef.h" 20#include "llvm/CallingConv.h" 21#include "llvm/CodeGen/MachineBasicBlock.h" 22#include "llvm/CodeGen/ValueTypes.h" 23#include "llvm/MC/MCRegisterInfo.h" 24#include <cassert> 25#include <functional> 26 27namespace llvm { 28 29class BitVector; 30class MachineFunction; 31class RegScavenger; 32template<class T> class SmallVectorImpl; 33class raw_ostream; 34 35class TargetRegisterClass { 36public: 37 typedef const MCPhysReg* iterator; 38 typedef const MCPhysReg* const_iterator; 39 typedef const MVT::SimpleValueType* vt_iterator; 40 typedef const TargetRegisterClass* const * sc_iterator; 41 42 // Instance variables filled by tablegen, do not use! 43 const MCRegisterClass *MC; 44 const vt_iterator VTs; 45 const uint32_t *SubClassMask; 46 const uint16_t *SuperRegIndices; 47 const sc_iterator SuperClasses; 48 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&); 49 50 /// getID() - Return the register class ID number. 51 /// 52 unsigned getID() const { return MC->getID(); } 53 54 /// getName() - Return the register class name for debugging. 55 /// 56 const char *getName() const { return MC->getName(); } 57 58 /// begin/end - Return all of the registers in this class. 59 /// 60 iterator begin() const { return MC->begin(); } 61 iterator end() const { return MC->end(); } 62 63 /// getNumRegs - Return the number of registers in this class. 64 /// 65 unsigned getNumRegs() const { return MC->getNumRegs(); } 66 67 /// getRegister - Return the specified register in the class. 68 /// 69 unsigned getRegister(unsigned i) const { 70 return MC->getRegister(i); 71 } 72 73 /// contains - Return true if the specified register is included in this 74 /// register class. This does not include virtual registers. 75 bool contains(unsigned Reg) const { 76 return MC->contains(Reg); 77 } 78 79 /// contains - Return true if both registers are in this class. 80 bool contains(unsigned Reg1, unsigned Reg2) const { 81 return MC->contains(Reg1, Reg2); 82 } 83 84 /// getSize - Return the size of the register in bytes, which is also the size 85 /// of a stack slot allocated to hold a spilled copy of this register. 86 unsigned getSize() const { return MC->getSize(); } 87 88 /// getAlignment - Return the minimum required alignment for a register of 89 /// this class. 90 unsigned getAlignment() const { return MC->getAlignment(); } 91 92 /// getCopyCost - Return the cost of copying a value between two registers in 93 /// this class. A negative number means the register class is very expensive 94 /// to copy e.g. status flag register classes. 95 int getCopyCost() const { return MC->getCopyCost(); } 96 97 /// isAllocatable - Return true if this register class may be used to create 98 /// virtual registers. 99 bool isAllocatable() const { return MC->isAllocatable(); } 100 101 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 102 /// 103 bool hasType(EVT vt) const { 104 for(int i = 0; VTs[i] != MVT::Other; ++i) 105 if (EVT(VTs[i]) == vt) 106 return true; 107 return false; 108 } 109 110 /// vt_begin / vt_end - Loop over all of the value types that can be 111 /// represented by values in this register class. 112 vt_iterator vt_begin() const { 113 return VTs; 114 } 115 116 vt_iterator vt_end() const { 117 vt_iterator I = VTs; 118 while (*I != MVT::Other) ++I; 119 return I; 120 } 121 122 /// hasSubClass - return true if the specified TargetRegisterClass 123 /// is a proper sub-class of this TargetRegisterClass. 124 bool hasSubClass(const TargetRegisterClass *RC) const { 125 return RC != this && hasSubClassEq(RC); 126 } 127 128 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 129 /// class. 130 bool hasSubClassEq(const TargetRegisterClass *RC) const { 131 unsigned ID = RC->getID(); 132 return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 133 } 134 135 /// hasSuperClass - return true if the specified TargetRegisterClass is a 136 /// proper super-class of this TargetRegisterClass. 137 bool hasSuperClass(const TargetRegisterClass *RC) const { 138 return RC->hasSubClass(this); 139 } 140 141 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 142 /// class. 143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 144 return RC->hasSubClassEq(this); 145 } 146 147 /// getSubClassMask - Returns a bit vector of subclasses, including this one. 148 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 149 /// use it. 150 const uint32_t *getSubClassMask() const { 151 return SubClassMask; 152 } 153 154 /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices 155 /// that project some super-register class into this register class. The list 156 /// has an entry for each Idx such that: 157 /// 158 /// There exists SuperRC where: 159 /// For all Reg in SuperRC: 160 /// this->contains(Reg:Idx) 161 /// 162 const uint16_t *getSuperRegIndices() const { 163 return SuperRegIndices; 164 } 165 166 /// getSuperClasses - Returns a NULL terminated list of super-classes. The 167 /// classes are ordered by ID which is also a topological ordering from large 168 /// to small classes. The list does NOT include the current class. 169 sc_iterator getSuperClasses() const { 170 return SuperClasses; 171 } 172 173 /// isASubClass - return true if this TargetRegisterClass is a subset 174 /// class of at least one other TargetRegisterClass. 175 bool isASubClass() const { 176 return SuperClasses[0] != 0; 177 } 178 179 /// getRawAllocationOrder - Returns the preferred order for allocating 180 /// registers from this register class in MF. The raw order comes directly 181 /// from the .td file and may include reserved registers that are not 182 /// allocatable. Register allocators should also make sure to allocate 183 /// callee-saved registers only after all the volatiles are used. The 184 /// RegisterClassInfo class provides filtered allocation orders with 185 /// callee-saved registers moved to the end. 186 /// 187 /// The MachineFunction argument can be used to tune the allocatable 188 /// registers based on the characteristics of the function, subtarget, or 189 /// other criteria. 190 /// 191 /// By default, this method returns all registers in the class. 192 /// 193 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { 194 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 195 } 196}; 197 198/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 199/// registers. These are used by codegen, not by MC. 200struct TargetRegisterInfoDesc { 201 unsigned CostPerUse; // Extra cost of instructions using register. 202 bool inAllocatableClass; // Register belongs to an allocatable regclass. 203}; 204 205/// Each TargetRegisterClass has a per register weight, and weight 206/// limit which must be less than the limits of its pressure sets. 207struct RegClassWeight { 208 unsigned RegWeight; 209 unsigned WeightLimit; 210}; 211 212/// TargetRegisterInfo base class - We assume that the target defines a static 213/// array of TargetRegisterDesc objects that represent all of the machine 214/// registers that the target has. As such, we simply have to track a pointer 215/// to this array so that we can turn register number into a register 216/// descriptor. 217/// 218class TargetRegisterInfo : public MCRegisterInfo { 219public: 220 typedef const TargetRegisterClass * const * regclass_iterator; 221private: 222 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 223 const char *const *SubRegIndexNames; // Names of subreg indexes. 224 // Pointer to array of lane masks, one per sub-reg index. 225 const unsigned *SubRegIndexLaneMasks; 226 227 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 228 229protected: 230 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 231 regclass_iterator RegClassBegin, 232 regclass_iterator RegClassEnd, 233 const char *const *SRINames, 234 const unsigned *SRILaneMasks); 235 virtual ~TargetRegisterInfo(); 236public: 237 238 // Register numbers can represent physical registers, virtual registers, and 239 // sometimes stack slots. The unsigned values are divided into these ranges: 240 // 241 // 0 Not a register, can be used as a sentinel. 242 // [1;2^30) Physical registers assigned by TableGen. 243 // [2^30;2^31) Stack slots. (Rarely used.) 244 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 245 // 246 // Further sentinels can be allocated from the small negative integers. 247 // DenseMapInfo<unsigned> uses -1u and -2u. 248 249 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 250 /// frame index in a variable that normally holds a register. isStackSlot() 251 /// returns true if Reg is in the range used for stack slots. 252 /// 253 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 254 /// slots, so if a variable may contains a stack slot, always check 255 /// isStackSlot() first. 256 /// 257 static bool isStackSlot(unsigned Reg) { 258 return int(Reg) >= (1 << 30); 259 } 260 261 /// stackSlot2Index - Compute the frame index from a register value 262 /// representing a stack slot. 263 static int stackSlot2Index(unsigned Reg) { 264 assert(isStackSlot(Reg) && "Not a stack slot"); 265 return int(Reg - (1u << 30)); 266 } 267 268 /// index2StackSlot - Convert a non-negative frame index to a stack slot 269 /// register value. 270 static unsigned index2StackSlot(int FI) { 271 assert(FI >= 0 && "Cannot hold a negative frame index."); 272 return FI + (1u << 30); 273 } 274 275 /// isPhysicalRegister - Return true if the specified register number is in 276 /// the physical register namespace. 277 static bool isPhysicalRegister(unsigned Reg) { 278 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 279 return int(Reg) > 0; 280 } 281 282 /// isVirtualRegister - Return true if the specified register number is in 283 /// the virtual register namespace. 284 static bool isVirtualRegister(unsigned Reg) { 285 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 286 return int(Reg) < 0; 287 } 288 289 /// virtReg2Index - Convert a virtual register number to a 0-based index. 290 /// The first virtual register in a function will get the index 0. 291 static unsigned virtReg2Index(unsigned Reg) { 292 assert(isVirtualRegister(Reg) && "Not a virtual register"); 293 return Reg & ~(1u << 31); 294 } 295 296 /// index2VirtReg - Convert a 0-based index to a virtual register number. 297 /// This is the inverse operation of VirtReg2IndexFunctor below. 298 static unsigned index2VirtReg(unsigned Index) { 299 return Index | (1u << 31); 300 } 301 302 /// getMinimalPhysRegClass - Returns the Register Class of a physical 303 /// register of the given type, picking the most sub register class of 304 /// the right type that contains this physreg. 305 const TargetRegisterClass * 306 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 307 308 /// getAllocatableClass - Return the maximal subclass of the given register 309 /// class that is alloctable, or NULL. 310 const TargetRegisterClass * 311 getAllocatableClass(const TargetRegisterClass *RC) const; 312 313 /// getAllocatableSet - Returns a bitset indexed by register number 314 /// indicating if a register is allocatable or not. If a register class is 315 /// specified, returns the subset for the class. 316 BitVector getAllocatableSet(const MachineFunction &MF, 317 const TargetRegisterClass *RC = NULL) const; 318 319 /// getCostPerUse - Return the additional cost of using this register instead 320 /// of other registers in its class. 321 unsigned getCostPerUse(unsigned RegNo) const { 322 return InfoDesc[RegNo].CostPerUse; 323 } 324 325 /// isInAllocatableClass - Return true if the register is in the allocation 326 /// of any register class. 327 bool isInAllocatableClass(unsigned RegNo) const { 328 return InfoDesc[RegNo].inAllocatableClass; 329 } 330 331 /// getSubRegIndexName - Return the human-readable symbolic target-specific 332 /// name for the specified SubRegIndex. 333 const char *getSubRegIndexName(unsigned SubIdx) const { 334 assert(SubIdx && SubIdx < getNumSubRegIndices() && 335 "This is not a subregister index"); 336 return SubRegIndexNames[SubIdx-1]; 337 } 338 339 /// getSubRegIndexLaneMask - Return a bitmask representing the parts of a 340 /// register that are covered by SubIdx. 341 /// 342 /// Lane masks for sub-register indices are similar to register units for 343 /// physical registers. The individual bits in a lane mask can't be assigned 344 /// any specific meaning. They can be used to check if two sub-register 345 /// indices overlap. 346 /// 347 /// If the target has a register such that: 348 /// 349 /// getSubReg(Reg, A) overlaps getSubReg(Reg, B) 350 /// 351 /// then: 352 /// 353 /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0 354 /// 355 /// The converse is not necessarily true. If two lane masks have a common 356 /// bit, the corresponding sub-registers may not overlap, but it can be 357 /// assumed that they usually will. 358 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { 359 // SubIdx == 0 is allowed, it has the lane mask ~0u. 360 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 361 return SubRegIndexLaneMasks[SubIdx]; 362 } 363 364 /// regsOverlap - Returns true if the two registers are equal or alias each 365 /// other. The registers may be virtual register. 366 bool regsOverlap(unsigned regA, unsigned regB) const { 367 if (regA == regB) return true; 368 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 369 return false; 370 371 // Regunits are numerically ordered. Find a common unit. 372 MCRegUnitIterator RUA(regA, this); 373 MCRegUnitIterator RUB(regB, this); 374 do { 375 if (*RUA == *RUB) return true; 376 if (*RUA < *RUB) ++RUA; 377 else ++RUB; 378 } while (RUA.isValid() && RUB.isValid()); 379 return false; 380 } 381 382 /// hasRegUnit - Returns true if Reg contains RegUnit. 383 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { 384 for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) 385 if (*Units == RegUnit) 386 return true; 387 return false; 388 } 389 390 /// isSubRegister - Returns true if regB is a sub-register of regA. 391 /// 392 bool isSubRegister(unsigned regA, unsigned regB) const { 393 return isSuperRegister(regB, regA); 394 } 395 396 /// isSuperRegister - Returns true if regB is a super-register of regA. 397 /// 398 bool isSuperRegister(unsigned RegA, unsigned RegB) const { 399 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I) 400 if (*I == RegB) 401 return true; 402 return false; 403 } 404 405 /// getCalleeSavedRegs - Return a null-terminated list of all of the 406 /// callee saved registers on this target. The register should be in the 407 /// order of desired callee-save stack frame offset. The first register is 408 /// closest to the incoming stack pointer if stack grows down, and vice versa. 409 /// 410 virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0) 411 const = 0; 412 413 /// getCallPreservedMask - Return a mask of call-preserved registers for the 414 /// given calling convention on the current sub-target. The mask should 415 /// include all call-preserved aliases. This is used by the register 416 /// allocator to determine which registers can be live across a call. 417 /// 418 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 419 /// A set bit indicates that all bits of the corresponding register are 420 /// preserved across the function call. The bit mask is expected to be 421 /// sub-register complete, i.e. if A is preserved, so are all its 422 /// sub-registers. 423 /// 424 /// Bits are numbered from the LSB, so the bit for physical register Reg can 425 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 426 /// 427 /// A NULL pointer means that no register mask will be used, and call 428 /// instructions should use implicit-def operands to indicate call clobbered 429 /// registers. 430 /// 431 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 432 // The default mask clobbers everything. All targets should override. 433 return 0; 434 } 435 436 /// getReservedRegs - Returns a bitset indexed by physical register number 437 /// indicating if a register is a special register that has particular uses 438 /// and should be considered unavailable at all times, e.g. SP, RA. This is 439 /// used by register scavenger to determine what registers are free. 440 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 441 442 /// getMatchingSuperReg - Return a super-register of the specified register 443 /// Reg so its sub-register of index SubIdx is Reg. 444 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 445 const TargetRegisterClass *RC) const { 446 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 447 } 448 449 /// getMatchingSuperRegClass - Return a subclass of the specified register 450 /// class A so that each register in it has a sub-register of the 451 /// specified sub-register index which is in the specified register class B. 452 /// 453 /// TableGen will synthesize missing A sub-classes. 454 virtual const TargetRegisterClass * 455 getMatchingSuperRegClass(const TargetRegisterClass *A, 456 const TargetRegisterClass *B, unsigned Idx) const; 457 458 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 459 /// supports the sub-register index Idx. 460 /// If no such sub-class exists, return NULL. 461 /// If all registers in RC already have an Idx sub-register, return RC. 462 /// 463 /// TableGen generates a version of this function that is good enough in most 464 /// cases. Targets can override if they have constraints that TableGen 465 /// doesn't understand. For example, the x86 sub_8bit sub-register index is 466 /// supported by the full GR32 register class in 64-bit mode, but only by the 467 /// GR32_ABCD regiister class in 32-bit mode. 468 /// 469 /// TableGen will synthesize missing RC sub-classes. 470 virtual const TargetRegisterClass * 471 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 472 assert(Idx == 0 && "Target has no sub-registers"); 473 return RC; 474 } 475 476 /// composeSubRegIndices - Return the subregister index you get from composing 477 /// two subregister indices. 478 /// 479 /// The special null sub-register index composes as the identity. 480 /// 481 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 482 /// returns c. Note that composeSubRegIndices does not tell you about illegal 483 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 484 /// b, composeSubRegIndices doesn't tell you. 485 /// 486 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 487 /// ssub_0:S0 - ssub_3:S3 subregs. 488 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 489 /// 490 unsigned composeSubRegIndices(unsigned a, unsigned b) const { 491 if (!a) return b; 492 if (!b) return a; 493 return composeSubRegIndicesImpl(a, b); 494 } 495 496protected: 497 /// Overridden by TableGen in targets that have sub-registers. 498 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { 499 llvm_unreachable("Target has no sub-registers"); 500 } 501 502public: 503 /// getCommonSuperRegClass - Find a common super-register class if it exists. 504 /// 505 /// Find a register class, SuperRC and two sub-register indices, PreA and 506 /// PreB, such that: 507 /// 508 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and 509 /// 510 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 511 /// 512 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). 513 /// 514 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the 515 /// requirements, and there is no register class with a smaller spill size 516 /// that satisfies the requirements. 517 /// 518 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead. 519 /// 520 /// Either of the PreA and PreB sub-register indices may be returned as 0. In 521 /// that case, the returned register class will be a sub-class of the 522 /// corresponding argument register class. 523 /// 524 /// The function returns NULL if no register class can be found. 525 /// 526 const TargetRegisterClass* 527 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 528 const TargetRegisterClass *RCB, unsigned SubB, 529 unsigned &PreA, unsigned &PreB) const; 530 531 //===--------------------------------------------------------------------===// 532 // Register Class Information 533 // 534 535 /// Register class iterators 536 /// 537 regclass_iterator regclass_begin() const { return RegClassBegin; } 538 regclass_iterator regclass_end() const { return RegClassEnd; } 539 540 unsigned getNumRegClasses() const { 541 return (unsigned)(regclass_end()-regclass_begin()); 542 } 543 544 /// getRegClass - Returns the register class associated with the enumeration 545 /// value. See class MCOperandInfo. 546 const TargetRegisterClass *getRegClass(unsigned i) const { 547 assert(i < getNumRegClasses() && "Register Class ID out of range"); 548 return RegClassBegin[i]; 549 } 550 551 /// getCommonSubClass - find the largest common subclass of A and B. Return 552 /// NULL if there is no common subclass. 553 const TargetRegisterClass * 554 getCommonSubClass(const TargetRegisterClass *A, 555 const TargetRegisterClass *B) const; 556 557 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 558 /// values. If a target supports multiple different pointer register classes, 559 /// kind specifies which one is indicated. 560 virtual const TargetRegisterClass * 561 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const { 562 llvm_unreachable("Target didn't implement getPointerRegClass!"); 563 } 564 565 /// getCrossCopyRegClass - Returns a legal register class to copy a register 566 /// in the specified class to or from. If it is possible to copy the register 567 /// directly without using a cross register class copy, return the specified 568 /// RC. Returns NULL if it is not possible to copy between a two registers of 569 /// the specified class. 570 virtual const TargetRegisterClass * 571 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 572 return RC; 573 } 574 575 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 576 /// legal to use in the current sub-target and has the same spill size. 577 /// The returned register class can be used to create virtual registers which 578 /// means that all its registers can be copied and spilled. 579 virtual const TargetRegisterClass* 580 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 581 /// The default implementation is very conservative and doesn't allow the 582 /// register allocator to inflate register classes. 583 return RC; 584 } 585 586 /// getRegPressureLimit - Return the register pressure "high water mark" for 587 /// the specific register class. The scheduler is in high register pressure 588 /// mode (for the specific register class) if it goes over the limit. 589 /// 590 /// Note: this is the old register pressure model that relies on a manually 591 /// specified representative register class per value type. 592 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 593 MachineFunction &MF) const { 594 return 0; 595 } 596 597// Get the weight in units of pressure for this register class. 598 virtual const RegClassWeight &getRegClassWeight( 599 const TargetRegisterClass *RC) const = 0; 600 601 /// Get the number of dimensions of register pressure. 602 virtual unsigned getNumRegPressureSets() const = 0; 603 604 /// Get the name of this register unit pressure set. 605 virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 606 607 /// Get the register unit pressure limit for this dimension. 608 /// This limit must be adjusted dynamically for reserved registers. 609 virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; 610 611 /// Get the dimensions of register pressure impacted by this register class. 612 /// Returns a -1 terminated array of pressure set IDs. 613 virtual const int *getRegClassPressureSets( 614 const TargetRegisterClass *RC) const = 0; 615 616 /// getRawAllocationOrder - Returns the register allocation order for a 617 /// specified register class with a target-dependent hint. The returned list 618 /// may contain reserved registers that cannot be allocated. 619 /// 620 /// Register allocators need only call this function to resolve 621 /// target-dependent hints, but it should work without hinting as well. 622 virtual ArrayRef<MCPhysReg> 623 getRawAllocationOrder(const TargetRegisterClass *RC, 624 unsigned HintType, unsigned HintReg, 625 const MachineFunction &MF) const { 626 return RC->getRawAllocationOrder(MF); 627 } 628 629 /// ResolveRegAllocHint - Resolves the specified register allocation hint 630 /// to a physical register. Returns the physical register if it is successful. 631 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 632 const MachineFunction &MF) const { 633 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 634 return Reg; 635 return 0; 636 } 637 638 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 639 /// writing a register from RC in two consecutive instructions. 640 /// This can avoid pipeline stalls on certain architectures. 641 /// It does cause increased register pressure, though. 642 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 643 return false; 644 } 645 646 /// UpdateRegAllocHint - A callback to allow target a chance to update 647 /// register allocation hints when a register is "changed" (e.g. coalesced) 648 /// to another register. e.g. On ARM, some virtual registers should target 649 /// register pairs, if one of pair is coalesced to another register, the 650 /// allocation hint of the other half of the pair should be changed to point 651 /// to the new register. 652 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 653 MachineFunction &MF) const { 654 // Do nothing. 655 } 656 657 /// requiresRegisterScavenging - returns true if the target requires (and can 658 /// make use of) the register scavenger. 659 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 660 return false; 661 } 662 663 /// useFPForScavengingIndex - returns true if the target wants to use 664 /// frame pointer based accesses to spill to the scavenger emergency spill 665 /// slot. 666 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 667 return true; 668 } 669 670 /// requiresFrameIndexScavenging - returns true if the target requires post 671 /// PEI scavenging of registers for materializing frame index constants. 672 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 673 return false; 674 } 675 676 /// requiresVirtualBaseRegisters - Returns true if the target wants the 677 /// LocalStackAllocation pass to be run and virtual base registers 678 /// used for more efficient stack access. 679 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 680 return false; 681 } 682 683 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 684 /// the stack frame of the given function for the specified register. e.g. On 685 /// x86, if the frame register is required, the first fixed stack object is 686 /// reserved as its spill slot. This tells PEI not to create a new stack frame 687 /// object for the given register. It should be called only after 688 /// processFunctionBeforeCalleeSavedScan(). 689 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 690 int &FrameIdx) const { 691 return false; 692 } 693 694 /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked 695 /// after register allocation. 696 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 697 return false; 698 } 699 700 /// needsStackRealignment - true if storage within the function requires the 701 /// stack pointer to be aligned more than the normal calling convention calls 702 /// for. 703 virtual bool needsStackRealignment(const MachineFunction &MF) const { 704 return false; 705 } 706 707 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 708 /// index in the instruction, if there is one. 709 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 710 int Idx) const { 711 return 0; 712 } 713 714 /// needsFrameBaseReg - Returns true if the instruction's frame index 715 /// reference would be better served by a base register other than FP 716 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 717 /// references it should create new base registers for. 718 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 719 return false; 720 } 721 722 /// materializeFrameBaseRegister - Insert defining instruction(s) for 723 /// BaseReg to be a pointer to FrameIdx before insertion point I. 724 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 725 unsigned BaseReg, int FrameIdx, 726 int64_t Offset) const { 727 llvm_unreachable("materializeFrameBaseRegister does not exist on this " 728 "target"); 729 } 730 731 /// resolveFrameIndex - Resolve a frame index operand of an instruction 732 /// to reference the indicated base register plus offset instead. 733 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 734 unsigned BaseReg, int64_t Offset) const { 735 llvm_unreachable("resolveFrameIndex does not exist on this target"); 736 } 737 738 /// isFrameOffsetLegal - Determine whether a given offset immediate is 739 /// encodable to resolve a frame index. 740 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 741 int64_t Offset) const { 742 llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 743 } 744 745 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 746 /// code insertion to eliminate call frame setup and destroy pseudo 747 /// instructions (but only if the Target is using them). It is responsible 748 /// for eliminating these instructions, replacing them with concrete 749 /// instructions. This method need only be implemented if using call frame 750 /// setup/destroy pseudo instructions. 751 /// 752 virtual void 753 eliminateCallFramePseudoInstr(MachineFunction &MF, 754 MachineBasicBlock &MBB, 755 MachineBasicBlock::iterator MI) const { 756 llvm_unreachable("Call Frame Pseudo Instructions do not exist on this " 757 "target!"); 758 } 759 760 761 /// saveScavengerRegister - Spill the register so it can be used by the 762 /// register scavenger. Return true if the register was spilled, false 763 /// otherwise. If this function does not spill the register, the scavenger 764 /// will instead spill it to the emergency spill slot. 765 /// 766 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 767 MachineBasicBlock::iterator I, 768 MachineBasicBlock::iterator &UseMI, 769 const TargetRegisterClass *RC, 770 unsigned Reg) const { 771 return false; 772 } 773 774 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 775 /// frame indices from instructions which may use them. The instruction 776 /// referenced by the iterator contains an MO_FrameIndex operand which must be 777 /// eliminated by this method. This method may modify or replace the 778 /// specified instruction, as long as it keeps the iterator pointing at the 779 /// finished product. SPAdj is the SP adjustment due to call frame setup 780 /// instruction. 781 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 782 int SPAdj, RegScavenger *RS=NULL) const = 0; 783 784 //===--------------------------------------------------------------------===// 785 /// Debug information queries. 786 787 /// getFrameRegister - This method should return the register used as a base 788 /// for values allocated in the current stack frame. 789 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 790 791 /// getCompactUnwindRegNum - This function maps the register to the number for 792 /// compact unwind encoding. Return -1 if the register isn't valid. 793 virtual int getCompactUnwindRegNum(unsigned, bool) const { 794 return -1; 795 } 796}; 797 798 799//===----------------------------------------------------------------------===// 800// SuperRegClassIterator 801//===----------------------------------------------------------------------===// 802// 803// Iterate over the possible super-registers for a given register class. The 804// iterator will visit a list of pairs (Idx, Mask) corresponding to the 805// possible classes of super-registers. 806// 807// Each bit mask will have at least one set bit, and each set bit in Mask 808// corresponds to a SuperRC such that: 809// 810// For all Reg in SuperRC: Reg:Idx is in RC. 811// 812// The iterator can include (O, RC->getSubClassMask()) as the first entry which 813// also satisfies the above requirement, assuming Reg:0 == Reg. 814// 815class SuperRegClassIterator { 816 const unsigned RCMaskWords; 817 unsigned SubReg; 818 const uint16_t *Idx; 819 const uint32_t *Mask; 820 821public: 822 /// Create a SuperRegClassIterator that visits all the super-register classes 823 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry. 824 SuperRegClassIterator(const TargetRegisterClass *RC, 825 const TargetRegisterInfo *TRI, 826 bool IncludeSelf = false) 827 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32), 828 SubReg(0), 829 Idx(RC->getSuperRegIndices()), 830 Mask(RC->getSubClassMask()) { 831 if (!IncludeSelf) 832 ++*this; 833 } 834 835 /// Returns true if this iterator is still pointing at a valid entry. 836 bool isValid() const { return Idx; } 837 838 /// Returns the current sub-register index. 839 unsigned getSubReg() const { return SubReg; } 840 841 /// Returns the bit mask if register classes that getSubReg() projects into 842 /// RC. 843 const uint32_t *getMask() const { return Mask; } 844 845 /// Advance iterator to the next entry. 846 void operator++() { 847 assert(isValid() && "Cannot move iterator past end."); 848 Mask += RCMaskWords; 849 SubReg = *Idx++; 850 if (!SubReg) 851 Idx = 0; 852 } 853}; 854 855// This is useful when building IndexedMaps keyed on virtual registers 856struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 857 unsigned operator()(unsigned Reg) const { 858 return TargetRegisterInfo::virtReg2Index(Reg); 859 } 860}; 861 862/// PrintReg - Helper class for printing registers on a raw_ostream. 863/// Prints virtual and physical registers with or without a TRI instance. 864/// 865/// The format is: 866/// %noreg - NoRegister 867/// %vreg5 - a virtual register. 868/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 869/// %EAX - a physical register 870/// %physreg17 - a physical register when no TRI instance given. 871/// 872/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 873/// 874class PrintReg { 875 const TargetRegisterInfo *TRI; 876 unsigned Reg; 877 unsigned SubIdx; 878public: 879 explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, 880 unsigned subidx = 0) 881 : TRI(tri), Reg(reg), SubIdx(subidx) {} 882 void print(raw_ostream&) const; 883}; 884 885static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 886 PR.print(OS); 887 return OS; 888} 889 890/// PrintRegUnit - Helper class for printing register units on a raw_ostream. 891/// 892/// Register units are named after their root registers: 893/// 894/// AL - Single root. 895/// FP0~ST7 - Dual roots. 896/// 897/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; 898/// 899class PrintRegUnit { 900 const TargetRegisterInfo *TRI; 901 unsigned Unit; 902public: 903 PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri) 904 : TRI(tri), Unit(unit) {} 905 void print(raw_ostream&) const; 906}; 907 908static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) { 909 PR.print(OS); 910 return OS; 911} 912 913} // End llvm namespace 914 915#endif 916