TargetRegisterInfo.h revision 2c6ae095b8a944c8355377498b9ad11bb94af2d5
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/MC/MCRegisterInfo.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/ValueTypes.h" 22#include "llvm/ADT/ArrayRef.h" 23#include "llvm/CallingConv.h" 24#include <cassert> 25#include <functional> 26 27namespace llvm { 28 29class BitVector; 30class MachineFunction; 31class RegScavenger; 32template<class T> class SmallVectorImpl; 33class raw_ostream; 34 35class TargetRegisterClass { 36public: 37 typedef const unsigned* iterator; 38 typedef const unsigned* const_iterator; 39 typedef const MVT::SimpleValueType* vt_iterator; 40 typedef const TargetRegisterClass* const * sc_iterator; 41private: 42 virtual void anchor(); 43 const MCRegisterClass *MC; 44 const vt_iterator VTs; 45 const unsigned *SubClassMask; 46 const sc_iterator SuperClasses; 47 const sc_iterator SuperRegClasses; 48public: 49 TargetRegisterClass(const MCRegisterClass *MC, 50 const MVT::SimpleValueType *vts, 51 const unsigned *subcm, 52 const TargetRegisterClass * const *supcs, 53 const TargetRegisterClass * const *superregcs) 54 : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs), 55 SuperRegClasses(superregcs) {} 56 57 virtual ~TargetRegisterClass() {} // Allow subclasses 58 59 /// getID() - Return the register class ID number. 60 /// 61 unsigned getID() const { return MC->getID(); } 62 63 /// getName() - Return the register class name for debugging. 64 /// 65 const char *getName() const { return MC->getName(); } 66 67 /// begin/end - Return all of the registers in this class. 68 /// 69 iterator begin() const { return MC->begin(); } 70 iterator end() const { return MC->end(); } 71 72 /// getNumRegs - Return the number of registers in this class. 73 /// 74 unsigned getNumRegs() const { return MC->getNumRegs(); } 75 76 /// getRegister - Return the specified register in the class. 77 /// 78 unsigned getRegister(unsigned i) const { 79 return MC->getRegister(i); 80 } 81 82 /// contains - Return true if the specified register is included in this 83 /// register class. This does not include virtual registers. 84 bool contains(unsigned Reg) const { 85 return MC->contains(Reg); 86 } 87 88 /// contains - Return true if both registers are in this class. 89 bool contains(unsigned Reg1, unsigned Reg2) const { 90 return MC->contains(Reg1, Reg2); 91 } 92 93 /// getSize - Return the size of the register in bytes, which is also the size 94 /// of a stack slot allocated to hold a spilled copy of this register. 95 unsigned getSize() const { return MC->getSize(); } 96 97 /// getAlignment - Return the minimum required alignment for a register of 98 /// this class. 99 unsigned getAlignment() const { return MC->getAlignment(); } 100 101 /// getCopyCost - Return the cost of copying a value between two registers in 102 /// this class. A negative number means the register class is very expensive 103 /// to copy e.g. status flag register classes. 104 int getCopyCost() const { return MC->getCopyCost(); } 105 106 /// isAllocatable - Return true if this register class may be used to create 107 /// virtual registers. 108 bool isAllocatable() const { return MC->isAllocatable(); } 109 110 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 111 /// 112 bool hasType(EVT vt) const { 113 for(int i = 0; VTs[i] != MVT::Other; ++i) 114 if (EVT(VTs[i]) == vt) 115 return true; 116 return false; 117 } 118 119 /// vt_begin / vt_end - Loop over all of the value types that can be 120 /// represented by values in this register class. 121 vt_iterator vt_begin() const { 122 return VTs; 123 } 124 125 vt_iterator vt_end() const { 126 vt_iterator I = VTs; 127 while (*I != MVT::Other) ++I; 128 return I; 129 } 130 131 /// superregclasses_begin / superregclasses_end - Loop over all of 132 /// the superreg register classes of this register class. 133 sc_iterator superregclasses_begin() const { 134 return SuperRegClasses; 135 } 136 137 sc_iterator superregclasses_end() const { 138 sc_iterator I = SuperRegClasses; 139 while (*I != NULL) ++I; 140 return I; 141 } 142 143 /// hasSubClass - return true if the specified TargetRegisterClass 144 /// is a proper sub-class of this TargetRegisterClass. 145 bool hasSubClass(const TargetRegisterClass *RC) const { 146 return RC != this && hasSubClassEq(RC); 147 } 148 149 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 150 /// class. 151 bool hasSubClassEq(const TargetRegisterClass *RC) const { 152 unsigned ID = RC->getID(); 153 return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 154 } 155 156 /// hasSuperClass - return true if the specified TargetRegisterClass is a 157 /// proper super-class of this TargetRegisterClass. 158 bool hasSuperClass(const TargetRegisterClass *RC) const { 159 return RC->hasSubClass(this); 160 } 161 162 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 163 /// class. 164 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 165 return RC->hasSubClassEq(this); 166 } 167 168 /// getSubClassMask - Returns a bit vector of subclasses, including this one. 169 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 170 /// use it. 171 const unsigned *getSubClassMask() const { 172 return SubClassMask; 173 } 174 175 /// getSuperClasses - Returns a NULL terminated list of super-classes. The 176 /// classes are ordered by ID which is also a topological ordering from large 177 /// to small classes. The list does NOT include the current class. 178 sc_iterator getSuperClasses() const { 179 return SuperClasses; 180 } 181 182 /// isASubClass - return true if this TargetRegisterClass is a subset 183 /// class of at least one other TargetRegisterClass. 184 bool isASubClass() const { 185 return SuperClasses[0] != 0; 186 } 187 188 /// getRawAllocationOrder - Returns the preferred order for allocating 189 /// registers from this register class in MF. The raw order comes directly 190 /// from the .td file and may include reserved registers that are not 191 /// allocatable. Register allocators should also make sure to allocate 192 /// callee-saved registers only after all the volatiles are used. The 193 /// RegisterClassInfo class provides filtered allocation orders with 194 /// callee-saved registers moved to the end. 195 /// 196 /// The MachineFunction argument can be used to tune the allocatable 197 /// registers based on the characteristics of the function, subtarget, or 198 /// other criteria. 199 /// 200 /// By default, this method returns all registers in the class. 201 /// 202 virtual 203 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { 204 return makeArrayRef(begin(), getNumRegs()); 205 } 206}; 207 208/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 209/// registers. These are used by codegen, not by MC. 210struct TargetRegisterInfoDesc { 211 unsigned CostPerUse; // Extra cost of instructions using register. 212 bool inAllocatableClass; // Register belongs to an allocatable regclass. 213}; 214 215/// TargetRegisterInfo base class - We assume that the target defines a static 216/// array of TargetRegisterDesc objects that represent all of the machine 217/// registers that the target has. As such, we simply have to track a pointer 218/// to this array so that we can turn register number into a register 219/// descriptor. 220/// 221class TargetRegisterInfo : public MCRegisterInfo { 222public: 223 typedef const TargetRegisterClass * const * regclass_iterator; 224private: 225 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 226 const char *const *SubRegIndexNames; // Names of subreg indexes. 227 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 228 229protected: 230 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 231 regclass_iterator RegClassBegin, 232 regclass_iterator RegClassEnd, 233 const char *const *subregindexnames); 234 virtual ~TargetRegisterInfo(); 235public: 236 237 // Register numbers can represent physical registers, virtual registers, and 238 // sometimes stack slots. The unsigned values are divided into these ranges: 239 // 240 // 0 Not a register, can be used as a sentinel. 241 // [1;2^30) Physical registers assigned by TableGen. 242 // [2^30;2^31) Stack slots. (Rarely used.) 243 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 244 // 245 // Further sentinels can be allocated from the small negative integers. 246 // DenseMapInfo<unsigned> uses -1u and -2u. 247 248 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 249 /// frame index in a variable that normally holds a register. isStackSlot() 250 /// returns true if Reg is in the range used for stack slots. 251 /// 252 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 253 /// slots, so if a variable may contains a stack slot, always check 254 /// isStackSlot() first. 255 /// 256 static bool isStackSlot(unsigned Reg) { 257 return int(Reg) >= (1 << 30); 258 } 259 260 /// stackSlot2Index - Compute the frame index from a register value 261 /// representing a stack slot. 262 static int stackSlot2Index(unsigned Reg) { 263 assert(isStackSlot(Reg) && "Not a stack slot"); 264 return int(Reg - (1u << 30)); 265 } 266 267 /// index2StackSlot - Convert a non-negative frame index to a stack slot 268 /// register value. 269 static unsigned index2StackSlot(int FI) { 270 assert(FI >= 0 && "Cannot hold a negative frame index."); 271 return FI + (1u << 30); 272 } 273 274 /// isPhysicalRegister - Return true if the specified register number is in 275 /// the physical register namespace. 276 static bool isPhysicalRegister(unsigned Reg) { 277 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 278 return int(Reg) > 0; 279 } 280 281 /// isVirtualRegister - Return true if the specified register number is in 282 /// the virtual register namespace. 283 static bool isVirtualRegister(unsigned Reg) { 284 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 285 return int(Reg) < 0; 286 } 287 288 /// virtReg2Index - Convert a virtual register number to a 0-based index. 289 /// The first virtual register in a function will get the index 0. 290 static unsigned virtReg2Index(unsigned Reg) { 291 assert(isVirtualRegister(Reg) && "Not a virtual register"); 292 return Reg & ~(1u << 31); 293 } 294 295 /// index2VirtReg - Convert a 0-based index to a virtual register number. 296 /// This is the inverse operation of VirtReg2IndexFunctor below. 297 static unsigned index2VirtReg(unsigned Index) { 298 return Index | (1u << 31); 299 } 300 301 /// getMinimalPhysRegClass - Returns the Register Class of a physical 302 /// register of the given type, picking the most sub register class of 303 /// the right type that contains this physreg. 304 const TargetRegisterClass * 305 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 306 307 /// getAllocatableSet - Returns a bitset indexed by register number 308 /// indicating if a register is allocatable or not. If a register class is 309 /// specified, returns the subset for the class. 310 BitVector getAllocatableSet(const MachineFunction &MF, 311 const TargetRegisterClass *RC = NULL) const; 312 313 /// getCostPerUse - Return the additional cost of using this register instead 314 /// of other registers in its class. 315 unsigned getCostPerUse(unsigned RegNo) const { 316 return InfoDesc[RegNo].CostPerUse; 317 } 318 319 /// isInAllocatableClass - Return true if the register is in the allocation 320 /// of any register class. 321 bool isInAllocatableClass(unsigned RegNo) const { 322 return InfoDesc[RegNo].inAllocatableClass; 323 } 324 325 /// getSubRegIndexName - Return the human-readable symbolic target-specific 326 /// name for the specified SubRegIndex. 327 const char *getSubRegIndexName(unsigned SubIdx) const { 328 assert(SubIdx && "This is not a subregister index"); 329 return SubRegIndexNames[SubIdx-1]; 330 } 331 332 /// regsOverlap - Returns true if the two registers are equal or alias each 333 /// other. The registers may be virtual register. 334 bool regsOverlap(unsigned regA, unsigned regB) const { 335 if (regA == regB) return true; 336 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 337 return false; 338 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { 339 if (*regList == regB) return true; 340 } 341 return false; 342 } 343 344 /// isSubRegister - Returns true if regB is a sub-register of regA. 345 /// 346 bool isSubRegister(unsigned regA, unsigned regB) const { 347 return isSuperRegister(regB, regA); 348 } 349 350 /// isSuperRegister - Returns true if regB is a super-register of regA. 351 /// 352 bool isSuperRegister(unsigned regA, unsigned regB) const { 353 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ 354 if (*regList == regB) return true; 355 } 356 return false; 357 } 358 359 /// getCalleeSavedRegs - Return a null-terminated list of all of the 360 /// callee saved registers on this target. The register should be in the 361 /// order of desired callee-save stack frame offset. The first register is 362 /// closest to the incoming stack pointer if stack grows down, and vice versa. 363 /// 364 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 365 const = 0; 366 367 /// getCallPreservedMask - Return a mask of call-preserved registers for the 368 /// given calling convention on the current sub-target. The mask should 369 /// include all call-preserved aliases. This is used by the register 370 /// allocator to determine which registers can be live across a call. 371 /// 372 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 373 /// A set bit indicates that all bits of the corresponding register are 374 /// preserved across the function call. The bit mask is expected to be 375 /// sub-register complete, i.e. if A is preserved, so are all its 376 /// sub-registers. 377 /// 378 /// Bits are numbered from the LSB, so the bit for physical register Reg can 379 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 380 /// 381 /// A NULL pointer means that no register mask will be used, and call 382 /// instructions should use implicit-def operands to indicate call clobbered 383 /// registers. 384 /// 385 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 386 // The default mask clobbers everything. All targets should override. 387 return 0; 388 } 389 390 /// getReservedRegs - Returns a bitset indexed by physical register number 391 /// indicating if a register is a special register that has particular uses 392 /// and should be considered unavailable at all times, e.g. SP, RA. This is 393 /// used by register scavenger to determine what registers are free. 394 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 395 396 /// getSubReg - Returns the physical register number of sub-register "Index" 397 /// for physical register RegNo. Return zero if the sub-register does not 398 /// exist. 399 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 400 401 /// getSubRegIndex - For a given register pair, return the sub-register index 402 /// if the second register is a sub-register of the first. Return zero 403 /// otherwise. 404 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 405 406 /// getMatchingSuperReg - Return a super-register of the specified register 407 /// Reg so its sub-register of index SubIdx is Reg. 408 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 409 const TargetRegisterClass *RC) const { 410 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 411 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 412 return SR; 413 return 0; 414 } 415 416 /// canCombineSubRegIndices - Given a register class and a list of 417 /// subregister indices, return true if it's possible to combine the 418 /// subregister indices into one that corresponds to a larger 419 /// subregister. Return the new subregister index by reference. Note the 420 /// new index may be zero if the given subregisters can be combined to 421 /// form the whole register. 422 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 423 SmallVectorImpl<unsigned> &SubIndices, 424 unsigned &NewSubIdx) const { 425 return 0; 426 } 427 428 /// getMatchingSuperRegClass - Return a subclass of the specified register 429 /// class A so that each register in it has a sub-register of the 430 /// specified sub-register index which is in the specified register class B. 431 /// 432 /// TableGen will synthesize missing A sub-classes. 433 virtual const TargetRegisterClass * 434 getMatchingSuperRegClass(const TargetRegisterClass *A, 435 const TargetRegisterClass *B, unsigned Idx) const =0; 436 437 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 438 /// supports the sub-register index Idx. 439 /// If no such sub-class exists, return NULL. 440 /// If all registers in RC already have an Idx sub-register, return RC. 441 /// 442 /// TableGen generates a version of this function that is good enough in most 443 /// cases. Targets can override if they have constraints that TableGen 444 /// doesn't understand. For example, the x86 sub_8bit sub-register index is 445 /// supported by the full GR32 register class in 64-bit mode, but only by the 446 /// GR32_ABCD regiister class in 32-bit mode. 447 /// 448 /// TableGen will synthesize missing RC sub-classes. 449 virtual const TargetRegisterClass * 450 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0; 451 452 /// composeSubRegIndices - Return the subregister index you get from composing 453 /// two subregister indices. 454 /// 455 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 456 /// returns c. Note that composeSubRegIndices does not tell you about illegal 457 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 458 /// b, composeSubRegIndices doesn't tell you. 459 /// 460 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 461 /// ssub_0:S0 - ssub_3:S3 subregs. 462 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 463 /// 464 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 465 // This default implementation is correct for most targets. 466 return b; 467 } 468 469 //===--------------------------------------------------------------------===// 470 // Register Class Information 471 // 472 473 /// Register class iterators 474 /// 475 regclass_iterator regclass_begin() const { return RegClassBegin; } 476 regclass_iterator regclass_end() const { return RegClassEnd; } 477 478 unsigned getNumRegClasses() const { 479 return (unsigned)(regclass_end()-regclass_begin()); 480 } 481 482 /// getRegClass - Returns the register class associated with the enumeration 483 /// value. See class MCOperandInfo. 484 const TargetRegisterClass *getRegClass(unsigned i) const { 485 assert(i < getNumRegClasses() && "Register Class ID out of range"); 486 return RegClassBegin[i]; 487 } 488 489 /// getCommonSubClass - find the largest common subclass of A and B. Return 490 /// NULL if there is no common subclass. 491 const TargetRegisterClass * 492 getCommonSubClass(const TargetRegisterClass *A, 493 const TargetRegisterClass *B) const; 494 495 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 496 /// values. If a target supports multiple different pointer register classes, 497 /// kind specifies which one is indicated. 498 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 499 llvm_unreachable("Target didn't implement getPointerRegClass!"); 500 } 501 502 /// getCrossCopyRegClass - Returns a legal register class to copy a register 503 /// in the specified class to or from. If it is possible to copy the register 504 /// directly without using a cross register class copy, return the specified 505 /// RC. Returns NULL if it is not possible to copy between a two registers of 506 /// the specified class. 507 virtual const TargetRegisterClass * 508 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 509 return RC; 510 } 511 512 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 513 /// legal to use in the current sub-target and has the same spill size. 514 /// The returned register class can be used to create virtual registers which 515 /// means that all its registers can be copied and spilled. 516 virtual const TargetRegisterClass* 517 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 518 /// The default implementation is very conservative and doesn't allow the 519 /// register allocator to inflate register classes. 520 return RC; 521 } 522 523 /// getRegPressureLimit - Return the register pressure "high water mark" for 524 /// the specific register class. The scheduler is in high register pressure 525 /// mode (for the specific register class) if it goes over the limit. 526 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 527 MachineFunction &MF) const { 528 return 0; 529 } 530 531 /// getRawAllocationOrder - Returns the register allocation order for a 532 /// specified register class with a target-dependent hint. The returned list 533 /// may contain reserved registers that cannot be allocated. 534 /// 535 /// Register allocators need only call this function to resolve 536 /// target-dependent hints, but it should work without hinting as well. 537 virtual ArrayRef<unsigned> 538 getRawAllocationOrder(const TargetRegisterClass *RC, 539 unsigned HintType, unsigned HintReg, 540 const MachineFunction &MF) const { 541 return RC->getRawAllocationOrder(MF); 542 } 543 544 /// ResolveRegAllocHint - Resolves the specified register allocation hint 545 /// to a physical register. Returns the physical register if it is successful. 546 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 547 const MachineFunction &MF) const { 548 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 549 return Reg; 550 return 0; 551 } 552 553 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 554 /// writing a register from RC in two consecutive instructions. 555 /// This can avoid pipeline stalls on certain architectures. 556 /// It does cause increased register pressure, though. 557 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 558 return false; 559 } 560 561 /// UpdateRegAllocHint - A callback to allow target a chance to update 562 /// register allocation hints when a register is "changed" (e.g. coalesced) 563 /// to another register. e.g. On ARM, some virtual registers should target 564 /// register pairs, if one of pair is coalesced to another register, the 565 /// allocation hint of the other half of the pair should be changed to point 566 /// to the new register. 567 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 568 MachineFunction &MF) const { 569 // Do nothing. 570 } 571 572 /// requiresRegisterScavenging - returns true if the target requires (and can 573 /// make use of) the register scavenger. 574 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 575 return false; 576 } 577 578 /// useFPForScavengingIndex - returns true if the target wants to use 579 /// frame pointer based accesses to spill to the scavenger emergency spill 580 /// slot. 581 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 582 return true; 583 } 584 585 /// requiresFrameIndexScavenging - returns true if the target requires post 586 /// PEI scavenging of registers for materializing frame index constants. 587 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 588 return false; 589 } 590 591 /// requiresVirtualBaseRegisters - Returns true if the target wants the 592 /// LocalStackAllocation pass to be run and virtual base registers 593 /// used for more efficient stack access. 594 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 595 return false; 596 } 597 598 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 599 /// the stack frame of the given function for the specified register. e.g. On 600 /// x86, if the frame register is required, the first fixed stack object is 601 /// reserved as its spill slot. This tells PEI not to create a new stack frame 602 /// object for the given register. It should be called only after 603 /// processFunctionBeforeCalleeSavedScan(). 604 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 605 int &FrameIdx) const { 606 return false; 607 } 608 609 /// needsStackRealignment - true if storage within the function requires the 610 /// stack pointer to be aligned more than the normal calling convention calls 611 /// for. 612 virtual bool needsStackRealignment(const MachineFunction &MF) const { 613 return false; 614 } 615 616 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 617 /// index in the instruction, if there is one. 618 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 619 int Idx) const { 620 return 0; 621 } 622 623 /// needsFrameBaseReg - Returns true if the instruction's frame index 624 /// reference would be better served by a base register other than FP 625 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 626 /// references it should create new base registers for. 627 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 628 return false; 629 } 630 631 /// materializeFrameBaseRegister - Insert defining instruction(s) for 632 /// BaseReg to be a pointer to FrameIdx before insertion point I. 633 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 634 unsigned BaseReg, int FrameIdx, 635 int64_t Offset) const { 636 llvm_unreachable("materializeFrameBaseRegister does not exist on this " 637 "target"); 638 } 639 640 /// resolveFrameIndex - Resolve a frame index operand of an instruction 641 /// to reference the indicated base register plus offset instead. 642 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 643 unsigned BaseReg, int64_t Offset) const { 644 llvm_unreachable("resolveFrameIndex does not exist on this target"); 645 } 646 647 /// isFrameOffsetLegal - Determine whether a given offset immediate is 648 /// encodable to resolve a frame index. 649 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 650 int64_t Offset) const { 651 llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 652 } 653 654 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 655 /// code insertion to eliminate call frame setup and destroy pseudo 656 /// instructions (but only if the Target is using them). It is responsible 657 /// for eliminating these instructions, replacing them with concrete 658 /// instructions. This method need only be implemented if using call frame 659 /// setup/destroy pseudo instructions. 660 /// 661 virtual void 662 eliminateCallFramePseudoInstr(MachineFunction &MF, 663 MachineBasicBlock &MBB, 664 MachineBasicBlock::iterator MI) const { 665 llvm_unreachable("Call Frame Pseudo Instructions do not exist on this " 666 "target!"); 667 } 668 669 670 /// saveScavengerRegister - Spill the register so it can be used by the 671 /// register scavenger. Return true if the register was spilled, false 672 /// otherwise. If this function does not spill the register, the scavenger 673 /// will instead spill it to the emergency spill slot. 674 /// 675 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 676 MachineBasicBlock::iterator I, 677 MachineBasicBlock::iterator &UseMI, 678 const TargetRegisterClass *RC, 679 unsigned Reg) const { 680 return false; 681 } 682 683 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 684 /// frame indices from instructions which may use them. The instruction 685 /// referenced by the iterator contains an MO_FrameIndex operand which must be 686 /// eliminated by this method. This method may modify or replace the 687 /// specified instruction, as long as it keeps the iterator pointing at the 688 /// finished product. SPAdj is the SP adjustment due to call frame setup 689 /// instruction. 690 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 691 int SPAdj, RegScavenger *RS=NULL) const = 0; 692 693 //===--------------------------------------------------------------------===// 694 /// Debug information queries. 695 696 /// getFrameRegister - This method should return the register used as a base 697 /// for values allocated in the current stack frame. 698 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 699 700 /// getCompactUnwindRegNum - This function maps the register to the number for 701 /// compact unwind encoding. Return -1 if the register isn't valid. 702 virtual int getCompactUnwindRegNum(unsigned, bool) const { 703 return -1; 704 } 705}; 706 707 708// This is useful when building IndexedMaps keyed on virtual registers 709struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 710 unsigned operator()(unsigned Reg) const { 711 return TargetRegisterInfo::virtReg2Index(Reg); 712 } 713}; 714 715/// PrintReg - Helper class for printing registers on a raw_ostream. 716/// Prints virtual and physical registers with or without a TRI instance. 717/// 718/// The format is: 719/// %noreg - NoRegister 720/// %vreg5 - a virtual register. 721/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 722/// %EAX - a physical register 723/// %physreg17 - a physical register when no TRI instance given. 724/// 725/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 726/// 727class PrintReg { 728 const TargetRegisterInfo *TRI; 729 unsigned Reg; 730 unsigned SubIdx; 731public: 732 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 733 : TRI(tri), Reg(reg), SubIdx(subidx) {} 734 void print(raw_ostream&) const; 735}; 736 737static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 738 PR.print(OS); 739 return OS; 740} 741 742} // End llvm namespace 743 744#endif 745