TargetRegisterInfo.h revision 320bdcbfe2691021702085f718db1617b1d4df49
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/ADT/DenseSet.h" 22#include <cassert> 23#include <functional> 24 25namespace llvm { 26 27class BitVector; 28class MachineFunction; 29class MachineMove; 30class RegScavenger; 31template<class T> class SmallVectorImpl; 32 33/// TargetRegisterDesc - This record contains all of the information known about 34/// a particular register. The AliasSet field (if not null) contains a pointer 35/// to a Zero terminated array of registers that this register aliases. This is 36/// needed for architectures like X86 which have AL alias AX alias EAX. 37/// Registers that this does not apply to simply should set this to null. 38/// The SubRegs field is a zero terminated array of registers that are 39/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 40/// The SuperRegs field is a zero terminated array of registers that are 41/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 42/// of AX. 43/// 44struct TargetRegisterDesc { 45 const char *Name; // Printable name for the reg (for debugging) 46 const unsigned *AliasSet; // Register Alias Set, described above 47 const unsigned *SubRegs; // Sub-register set, described above 48 const unsigned *SuperRegs; // Super-register set, described above 49}; 50 51class TargetRegisterClass { 52public: 53 typedef const unsigned* iterator; 54 typedef const unsigned* const_iterator; 55 56 typedef const EVT* vt_iterator; 57 typedef const TargetRegisterClass* const * sc_iterator; 58private: 59 unsigned ID; 60 const char *Name; 61 const vt_iterator VTs; 62 const sc_iterator SubClasses; 63 const sc_iterator SuperClasses; 64 const sc_iterator SubRegClasses; 65 const sc_iterator SuperRegClasses; 66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 67 const int CopyCost; 68 const iterator RegsBegin, RegsEnd; 69 DenseSet<unsigned> RegSet; 70public: 71 TargetRegisterClass(unsigned id, 72 const char *name, 73 const EVT *vts, 74 const TargetRegisterClass * const *subcs, 75 const TargetRegisterClass * const *supcs, 76 const TargetRegisterClass * const *subregcs, 77 const TargetRegisterClass * const *superregcs, 78 unsigned RS, unsigned Al, int CC, 79 iterator RB, iterator RE) 80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 81 SubRegClasses(subregcs), SuperRegClasses(superregcs), 82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) { 83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) 84 RegSet.insert(*I); 85 } 86 virtual ~TargetRegisterClass() {} // Allow subclasses 87 88 /// getID() - Return the register class ID number. 89 /// 90 unsigned getID() const { return ID; } 91 92 /// getName() - Return the register class name for debugging. 93 /// 94 const char *getName() const { return Name; } 95 96 /// begin/end - Return all of the registers in this class. 97 /// 98 iterator begin() const { return RegsBegin; } 99 iterator end() const { return RegsEnd; } 100 101 /// getNumRegs - Return the number of registers in this class. 102 /// 103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 104 105 /// getRegister - Return the specified register in the class. 106 /// 107 unsigned getRegister(unsigned i) const { 108 assert(i < getNumRegs() && "Register number out of range!"); 109 return RegsBegin[i]; 110 } 111 112 /// contains - Return true if the specified register is included in this 113 /// register class. This does not include virtual registers. 114 bool contains(unsigned Reg) const { 115 return RegSet.count(Reg); 116 } 117 118 /// contains - Return true if both registers are in this class. 119 bool contains(unsigned Reg1, unsigned Reg2) const { 120 return contains(Reg1) && contains(Reg2); 121 } 122 123 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 124 /// 125 bool hasType(EVT vt) const { 126 for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i) 127 if (VTs[i] == vt) 128 return true; 129 return false; 130 } 131 132 /// vt_begin / vt_end - Loop over all of the value types that can be 133 /// represented by values in this register class. 134 vt_iterator vt_begin() const { 135 return VTs; 136 } 137 138 vt_iterator vt_end() const { 139 vt_iterator I = VTs; 140 while (I->getSimpleVT().SimpleTy != MVT::Other) ++I; 141 return I; 142 } 143 144 /// subregclasses_begin / subregclasses_end - Loop over all of 145 /// the subreg register classes of this register class. 146 sc_iterator subregclasses_begin() const { 147 return SubRegClasses; 148 } 149 150 sc_iterator subregclasses_end() const { 151 sc_iterator I = SubRegClasses; 152 while (*I != NULL) ++I; 153 return I; 154 } 155 156 /// getSubRegisterRegClass - Return the register class of subregisters with 157 /// index SubIdx, or NULL if no such class exists. 158 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 159 assert(SubIdx>0 && "Invalid subregister index"); 160 return SubRegClasses[SubIdx-1]; 161 } 162 163 /// superregclasses_begin / superregclasses_end - Loop over all of 164 /// the superreg register classes of this register class. 165 sc_iterator superregclasses_begin() const { 166 return SuperRegClasses; 167 } 168 169 sc_iterator superregclasses_end() const { 170 sc_iterator I = SuperRegClasses; 171 while (*I != NULL) ++I; 172 return I; 173 } 174 175 /// hasSubClass - return true if the specified TargetRegisterClass 176 /// is a proper subset of this TargetRegisterClass. 177 bool hasSubClass(const TargetRegisterClass *cs) const { 178 for (int i = 0; SubClasses[i] != NULL; ++i) 179 if (SubClasses[i] == cs) 180 return true; 181 return false; 182 } 183 184 /// subclasses_begin / subclasses_end - Loop over all of the classes 185 /// that are proper subsets of this register class. 186 sc_iterator subclasses_begin() const { 187 return SubClasses; 188 } 189 190 sc_iterator subclasses_end() const { 191 sc_iterator I = SubClasses; 192 while (*I != NULL) ++I; 193 return I; 194 } 195 196 /// hasSuperClass - return true if the specified TargetRegisterClass is a 197 /// proper superset of this TargetRegisterClass. 198 bool hasSuperClass(const TargetRegisterClass *cs) const { 199 for (int i = 0; SuperClasses[i] != NULL; ++i) 200 if (SuperClasses[i] == cs) 201 return true; 202 return false; 203 } 204 205 /// superclasses_begin / superclasses_end - Loop over all of the classes 206 /// that are proper supersets of this register class. 207 sc_iterator superclasses_begin() const { 208 return SuperClasses; 209 } 210 211 sc_iterator superclasses_end() const { 212 sc_iterator I = SuperClasses; 213 while (*I != NULL) ++I; 214 return I; 215 } 216 217 /// isASubClass - return true if this TargetRegisterClass is a subset 218 /// class of at least one other TargetRegisterClass. 219 bool isASubClass() const { 220 return SuperClasses[0] != 0; 221 } 222 223 /// allocation_order_begin/end - These methods define a range of registers 224 /// which specify the registers in this class that are valid to register 225 /// allocate, and the preferred order to allocate them in. For example, 226 /// callee saved registers should be at the end of the list, because it is 227 /// cheaper to allocate caller saved registers. 228 /// 229 /// These methods take a MachineFunction argument, which can be used to tune 230 /// the allocatable registers based on the characteristics of the function. 231 /// One simple example is that the frame pointer register can be used if 232 /// frame-pointer-elimination is performed. 233 /// 234 /// By default, these methods return all registers in the class. 235 /// 236 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 237 return begin(); 238 } 239 virtual iterator allocation_order_end(const MachineFunction &MF) const { 240 return end(); 241 } 242 243 /// getSize - Return the size of the register in bytes, which is also the size 244 /// of a stack slot allocated to hold a spilled copy of this register. 245 unsigned getSize() const { return RegSize; } 246 247 /// getAlignment - Return the minimum required alignment for a register of 248 /// this class. 249 unsigned getAlignment() const { return Alignment; } 250 251 /// getCopyCost - Return the cost of copying a value between two registers in 252 /// this class. A negative number means the register class is very expensive 253 /// to copy e.g. status flag register classes. 254 int getCopyCost() const { return CopyCost; } 255}; 256 257 258/// TargetRegisterInfo base class - We assume that the target defines a static 259/// array of TargetRegisterDesc objects that represent all of the machine 260/// registers that the target has. As such, we simply have to track a pointer 261/// to this array so that we can turn register number into a register 262/// descriptor. 263/// 264class TargetRegisterInfo { 265protected: 266 const unsigned* SubregHash; 267 const unsigned SubregHashSize; 268 const unsigned* AliasesHash; 269 const unsigned AliasesHashSize; 270public: 271 typedef const TargetRegisterClass * const * regclass_iterator; 272private: 273 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 274 const char *const *SubRegIndexNames; // Names of subreg indexes. 275 unsigned NumRegs; // Number of entries in the array 276 277 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 278 279 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 280 281protected: 282 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 283 regclass_iterator RegClassBegin, 284 regclass_iterator RegClassEnd, 285 const char *const *subregindexnames, 286 int CallFrameSetupOpcode = -1, 287 int CallFrameDestroyOpcode = -1, 288 const unsigned* subregs = 0, 289 const unsigned subregsize = 0, 290 const unsigned* aliases = 0, 291 const unsigned aliasessize = 0); 292 virtual ~TargetRegisterInfo(); 293public: 294 295 enum { // Define some target independent constants 296 /// NoRegister - This physical register is not a real target register. It 297 /// is useful as a sentinal. 298 NoRegister = 0, 299 300 /// FirstVirtualRegister - This is the first register number that is 301 /// considered to be a 'virtual' register, which is part of the SSA 302 /// namespace. This must be the same for all targets, which means that each 303 /// target is limited to this fixed number of registers. 304 FirstVirtualRegister = 1024 305 }; 306 307 /// isPhysicalRegister - Return true if the specified register number is in 308 /// the physical register namespace. 309 static bool isPhysicalRegister(unsigned Reg) { 310 assert(Reg && "this is not a register!"); 311 return Reg < FirstVirtualRegister; 312 } 313 314 /// isVirtualRegister - Return true if the specified register number is in 315 /// the virtual register namespace. 316 static bool isVirtualRegister(unsigned Reg) { 317 assert(Reg && "this is not a register!"); 318 return Reg >= FirstVirtualRegister; 319 } 320 321 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 322 /// register of the given type. If type is EVT::Other, then just return any 323 /// register class the register belongs to. 324 virtual const TargetRegisterClass * 325 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const; 326 327 /// getMinimalPhysRegClass - Returns the Register Class of a physical 328 /// register of the given type, picking the most sub register class of 329 /// the right type that contains this physreg. 330 const TargetRegisterClass * 331 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 332 333 /// getAllocatableSet - Returns a bitset indexed by register number 334 /// indicating if a register is allocatable or not. If a register class is 335 /// specified, returns the subset for the class. 336 BitVector getAllocatableSet(const MachineFunction &MF, 337 const TargetRegisterClass *RC = NULL) const; 338 339 const TargetRegisterDesc &operator[](unsigned RegNo) const { 340 assert(RegNo < NumRegs && 341 "Attempting to access record for invalid register number!"); 342 return Desc[RegNo]; 343 } 344 345 /// Provide a get method, equivalent to [], but more useful if we have a 346 /// pointer to this object. 347 /// 348 const TargetRegisterDesc &get(unsigned RegNo) const { 349 return operator[](RegNo); 350 } 351 352 /// getAliasSet - Return the set of registers aliased by the specified 353 /// register, or a null list of there are none. The list returned is zero 354 /// terminated. 355 /// 356 const unsigned *getAliasSet(unsigned RegNo) const { 357 return get(RegNo).AliasSet; 358 } 359 360 /// getSubRegisters - Return the list of registers that are sub-registers of 361 /// the specified register, or a null list of there are none. The list 362 /// returned is zero terminated and sorted according to super-sub register 363 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 364 /// 365 const unsigned *getSubRegisters(unsigned RegNo) const { 366 return get(RegNo).SubRegs; 367 } 368 369 /// getSuperRegisters - Return the list of registers that are super-registers 370 /// of the specified register, or a null list of there are none. The list 371 /// returned is zero terminated and sorted according to super-sub register 372 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 373 /// 374 const unsigned *getSuperRegisters(unsigned RegNo) const { 375 return get(RegNo).SuperRegs; 376 } 377 378 /// getName - Return the human-readable symbolic target-specific name for the 379 /// specified physical register. 380 const char *getName(unsigned RegNo) const { 381 return get(RegNo).Name; 382 } 383 384 /// getNumRegs - Return the number of registers this target has (useful for 385 /// sizing arrays holding per register information) 386 unsigned getNumRegs() const { 387 return NumRegs; 388 } 389 390 /// getSubRegIndexName - Return the human-readable symbolic target-specific 391 /// name for the specified SubRegIndex. 392 const char *getSubRegIndexName(unsigned SubIdx) const { 393 assert(SubIdx && "This is not a subregister index"); 394 return SubRegIndexNames[SubIdx-1]; 395 } 396 397 /// regsOverlap - Returns true if the two registers are equal or alias each 398 /// other. The registers may be virtual register. 399 bool regsOverlap(unsigned regA, unsigned regB) const { 400 if (regA == regB) 401 return true; 402 403 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 404 return false; 405 406 // regA and regB are distinct physical registers. Do they alias? 407 size_t index = (regA + regB * 37) & (AliasesHashSize-1); 408 unsigned ProbeAmt = 0; 409 while (AliasesHash[index*2] != 0 && 410 AliasesHash[index*2+1] != 0) { 411 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) 412 return true; 413 414 index = (index + ProbeAmt) & (AliasesHashSize-1); 415 ProbeAmt += 2; 416 } 417 418 return false; 419 } 420 421 /// isSubRegister - Returns true if regB is a sub-register of regA. 422 /// 423 bool isSubRegister(unsigned regA, unsigned regB) const { 424 // SubregHash is a simple quadratically probed hash table. 425 size_t index = (regA + regB * 37) & (SubregHashSize-1); 426 unsigned ProbeAmt = 2; 427 while (SubregHash[index*2] != 0 && 428 SubregHash[index*2+1] != 0) { 429 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 430 return true; 431 432 index = (index + ProbeAmt) & (SubregHashSize-1); 433 ProbeAmt += 2; 434 } 435 436 return false; 437 } 438 439 /// isSuperRegister - Returns true if regB is a super-register of regA. 440 /// 441 bool isSuperRegister(unsigned regA, unsigned regB) const { 442 return isSubRegister(regB, regA); 443 } 444 445 /// getCalleeSavedRegs - Return a null-terminated list of all of the 446 /// callee saved registers on this target. The register should be in the 447 /// order of desired callee-save stack frame offset. The first register is 448 /// closed to the incoming stack pointer if stack grows down, and vice versa. 449 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 450 const = 0; 451 452 453 /// getReservedRegs - Returns a bitset indexed by physical register number 454 /// indicating if a register is a special register that has particular uses 455 /// and should be considered unavailable at all times, e.g. SP, RA. This is 456 /// used by register scavenger to determine what registers are free. 457 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 458 459 /// getSubReg - Returns the physical register number of sub-register "Index" 460 /// for physical register RegNo. Return zero if the sub-register does not 461 /// exist. 462 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 463 464 /// getSubRegIndex - For a given register pair, return the sub-register index 465 /// if the second register is a sub-register of the first. Return zero 466 /// otherwise. 467 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 468 469 /// getMatchingSuperReg - Return a super-register of the specified register 470 /// Reg so its sub-register of index SubIdx is Reg. 471 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 472 const TargetRegisterClass *RC) const { 473 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 474 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 475 return SR; 476 return 0; 477 } 478 479 /// canCombineSubRegIndices - Given a register class and a list of 480 /// subregister indices, return true if it's possible to combine the 481 /// subregister indices into one that corresponds to a larger 482 /// subregister. Return the new subregister index by reference. Note the 483 /// new index may be zero if the given subregisters can be combined to 484 /// form the whole register. 485 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 486 SmallVectorImpl<unsigned> &SubIndices, 487 unsigned &NewSubIdx) const { 488 return 0; 489 } 490 491 /// getMatchingSuperRegClass - Return a subclass of the specified register 492 /// class A so that each register in it has a sub-register of the 493 /// specified sub-register index which is in the specified register class B. 494 virtual const TargetRegisterClass * 495 getMatchingSuperRegClass(const TargetRegisterClass *A, 496 const TargetRegisterClass *B, unsigned Idx) const { 497 return 0; 498 } 499 500 /// composeSubRegIndices - Return the subregister index you get from composing 501 /// two subregister indices. 502 /// 503 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 504 /// returns c. Note that composeSubRegIndices does not tell you about illegal 505 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 506 /// b, composeSubRegIndices doesn't tell you. 507 /// 508 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 509 /// ssub_0:S0 - ssub_3:S3 subregs. 510 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 511 /// 512 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 513 // This default implementation is correct for most targets. 514 return b; 515 } 516 517 //===--------------------------------------------------------------------===// 518 // Register Class Information 519 // 520 521 /// Register class iterators 522 /// 523 regclass_iterator regclass_begin() const { return RegClassBegin; } 524 regclass_iterator regclass_end() const { return RegClassEnd; } 525 526 unsigned getNumRegClasses() const { 527 return (unsigned)(regclass_end()-regclass_begin()); 528 } 529 530 /// getRegClass - Returns the register class associated with the enumeration 531 /// value. See class TargetOperandInfo. 532 const TargetRegisterClass *getRegClass(unsigned i) const { 533 assert(i < getNumRegClasses() && "Register Class ID out of range"); 534 return RegClassBegin[i]; 535 } 536 537 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 538 /// values. If a target supports multiple different pointer register classes, 539 /// kind specifies which one is indicated. 540 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 541 assert(0 && "Target didn't implement getPointerRegClass!"); 542 return 0; // Must return a value in order to compile with VS 2005 543 } 544 545 /// getCrossCopyRegClass - Returns a legal register class to copy a register 546 /// in the specified class to or from. Returns NULL if it is possible to copy 547 /// between a two registers of the specified class. 548 virtual const TargetRegisterClass * 549 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 550 return NULL; 551 } 552 553 /// getAllocationOrder - Returns the register allocation order for a specified 554 /// register class in the form of a pair of TargetRegisterClass iterators. 555 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 556 getAllocationOrder(const TargetRegisterClass *RC, 557 unsigned HintType, unsigned HintReg, 558 const MachineFunction &MF) const { 559 return std::make_pair(RC->allocation_order_begin(MF), 560 RC->allocation_order_end(MF)); 561 } 562 563 /// ResolveRegAllocHint - Resolves the specified register allocation hint 564 /// to a physical register. Returns the physical register if it is successful. 565 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 566 const MachineFunction &MF) const { 567 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 568 return Reg; 569 return 0; 570 } 571 572 /// UpdateRegAllocHint - A callback to allow target a chance to update 573 /// register allocation hints when a register is "changed" (e.g. coalesced) 574 /// to another register. e.g. On ARM, some virtual registers should target 575 /// register pairs, if one of pair is coalesced to another register, the 576 /// allocation hint of the other half of the pair should be changed to point 577 /// to the new register. 578 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 579 MachineFunction &MF) const { 580 // Do nothing. 581 } 582 583 /// targetHandlesStackFrameRounding - Returns true if the target is 584 /// responsible for rounding up the stack frame (probably at emitPrologue 585 /// time). 586 virtual bool targetHandlesStackFrameRounding() const { 587 return false; 588 } 589 590 /// requiresRegisterScavenging - returns true if the target requires (and can 591 /// make use of) the register scavenger. 592 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 593 return false; 594 } 595 596 /// requiresFrameIndexScavenging - returns true if the target requires post 597 /// PEI scavenging of registers for materializing frame index constants. 598 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 599 return false; 600 } 601 602 /// hasFP - Return true if the specified function should have a dedicated 603 /// frame pointer register. For most targets this is true only if the function 604 /// has variable sized allocas or if frame pointer elimination is disabled. 605 virtual bool hasFP(const MachineFunction &MF) const = 0; 606 607 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 608 /// not required, we reserve argument space for call sites in the function 609 /// immediately on entry to the current function. This eliminates the need for 610 /// add/sub sp brackets around call sites. Returns true if the call frame is 611 /// included as part of the stack frame. 612 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 613 return !hasFP(MF); 614 } 615 616 /// canSimplifyCallFramePseudos - When possible, it's best to simplify the 617 /// call frame pseudo ops before doing frame index elimination. This is 618 /// possible only when frame index references between the pseudos won't 619 /// need adjusted for the call frame adjustments. Normally, that's true 620 /// if the function has a reserved call frame or a frame pointer. Some 621 /// targets (Thumb2, for example) may have more complicated criteria, 622 /// however, and can override this behavior. 623 virtual bool canSimplifyCallFramePseudos(MachineFunction &MF) const { 624 return hasReservedCallFrame(MF) || hasFP(MF); 625 } 626 627 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 628 /// the stack frame of the given function for the specified register. e.g. On 629 /// x86, if the frame register is required, the first fixed stack object is 630 /// reserved as its spill slot. This tells PEI not to create a new stack frame 631 /// object for the given register. It should be called only after 632 /// processFunctionBeforeCalleeSavedScan(). 633 virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg, 634 int &FrameIdx) const { 635 return false; 636 } 637 638 /// needsStackRealignment - true if storage within the function requires the 639 /// stack pointer to be aligned more than the normal calling convention calls 640 /// for. 641 virtual bool needsStackRealignment(const MachineFunction &MF) const { 642 return false; 643 } 644 645 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 646 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 647 /// targets use pseudo instructions in order to abstract away the difference 648 /// between operating with a frame pointer and operating without, through the 649 /// use of these two instructions. 650 /// 651 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 652 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 653 654 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 655 /// code insertion to eliminate call frame setup and destroy pseudo 656 /// instructions (but only if the Target is using them). It is responsible 657 /// for eliminating these instructions, replacing them with concrete 658 /// instructions. This method need only be implemented if using call frame 659 /// setup/destroy pseudo instructions. 660 /// 661 virtual void 662 eliminateCallFramePseudoInstr(MachineFunction &MF, 663 MachineBasicBlock &MBB, 664 MachineBasicBlock::iterator MI) const { 665 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 666 "eliminateCallFramePseudoInstr must be implemented if using" 667 " call frame setup/destroy pseudo instructions!"); 668 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 669 } 670 671 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 672 /// before PrologEpilogInserter scans the physical registers used to determine 673 /// what callee saved registers should be spilled. This method is optional. 674 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 675 RegScavenger *RS = NULL) const { 676 677 } 678 679 /// processFunctionBeforeFrameFinalized - This method is called immediately 680 /// before the specified functions frame layout (MF.getFrameInfo()) is 681 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 682 /// replaced with direct constants. This method is optional. 683 /// 684 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 685 } 686 687 /// saveScavengerRegister - Spill the register so it can be used by the 688 /// register scavenger. Return true if the register was spilled, false 689 /// otherwise. If this function does not spill the register, the scavenger 690 /// will instead spill it to the emergency spill slot. 691 /// 692 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 693 MachineBasicBlock::iterator I, 694 MachineBasicBlock::iterator &UseMI, 695 const TargetRegisterClass *RC, 696 unsigned Reg) const { 697 return false; 698 } 699 700 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 701 /// frame indices from instructions which may use them. The instruction 702 /// referenced by the iterator contains an MO_FrameIndex operand which must be 703 /// eliminated by this method. This method may modify or replace the 704 /// specified instruction, as long as it keeps the iterator pointing at the 705 /// finished product. SPAdj is the SP adjustment due to call frame setup 706 /// instruction. 707 /// 708 /// When -enable-frame-index-scavenging is enabled, the virtual register 709 /// allocated for this frame index is returned and its value is stored in 710 /// *Value. 711 typedef std::pair<unsigned, int> FrameIndexValue; 712 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI, 713 int SPAdj, FrameIndexValue *Value = NULL, 714 RegScavenger *RS=NULL) const = 0; 715 716 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 717 /// the function. 718 virtual void emitPrologue(MachineFunction &MF) const = 0; 719 virtual void emitEpilogue(MachineFunction &MF, 720 MachineBasicBlock &MBB) const = 0; 721 722 //===--------------------------------------------------------------------===// 723 /// Debug information queries. 724 725 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 726 /// number. Returns -1 if there is no equivalent value. The second 727 /// parameter allows targets to use different numberings for EH info and 728 /// debugging info. 729 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 730 731 /// getFrameRegister - This method should return the register used as a base 732 /// for values allocated in the current stack frame. 733 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 734 735 /// getFrameIndexOffset - Returns the displacement from the frame register to 736 /// the stack frame of the specified index. 737 virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const; 738 739 /// getFrameIndexReference - This method should return the base register 740 /// and offset used to reference a frame index location. The offset is 741 /// returned directly, and the base register is returned via FrameReg. 742 virtual int getFrameIndexReference(const MachineFunction &MF, int FI, 743 unsigned &FrameReg) const { 744 // By default, assume all frame indices are referenced via whatever 745 // getFrameRegister() says. The target can override this if it's doing 746 // something different. 747 FrameReg = getFrameRegister(MF); 748 return getFrameIndexOffset(MF, FI); 749 } 750 751 /// getRARegister - This method should return the register where the return 752 /// address can be found. 753 virtual unsigned getRARegister() const = 0; 754 755 /// getInitialFrameState - Returns a list of machine moves that are assumed 756 /// on entry to all functions. Note that LabelID is ignored (assumed to be 757 /// the beginning of the function.) 758 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 759}; 760 761 762// This is useful when building IndexedMaps keyed on virtual registers 763struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 764 unsigned operator()(unsigned Reg) const { 765 return Reg - TargetRegisterInfo::FirstVirtualRegister; 766 } 767}; 768 769/// getCommonSubClass - find the largest common subclass of A and B. Return NULL 770/// if there is no common subclass. 771const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, 772 const TargetRegisterClass *B); 773 774} // End llvm namespace 775 776#endif 777