TargetRegisterInfo.h revision 57ce0319b7eb4418aac910d9a094e57d983a64d2
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/ValueTypes.h" 22#include <cassert> 23#include <functional> 24#include <set> 25 26namespace llvm { 27 28class BitVector; 29class MachineFunction; 30class MachineInstr; 31class MachineMove; 32class RegScavenger; 33class SDNode; 34class SelectionDAG; 35class TargetRegisterClass; 36class Type; 37 38/// TargetRegisterDesc - This record contains all of the information known about 39/// a particular register. The AliasSet field (if not null) contains a pointer 40/// to a Zero terminated array of registers that this register aliases. This is 41/// needed for architectures like X86 which have AL alias AX alias EAX. 42/// Registers that this does not apply to simply should set this to null. 43/// The SubRegs field is a zero terminated array of registers that are 44/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 45/// The SuperRegs field is a zero terminated array of registers that are 46/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 47/// of AX. 48/// 49struct TargetRegisterDesc { 50 const char *AsmName; // Assembly language name for the register 51 const char *Name; // Printable name for the reg (for debugging) 52 const unsigned *AliasSet; // Register Alias Set, described above 53 const unsigned *SubRegs; // Sub-register set, described above 54 const unsigned *SuperRegs; // Super-register set, described above 55}; 56 57class TargetRegisterClass { 58public: 59 typedef const unsigned* iterator; 60 typedef const unsigned* const_iterator; 61 62 typedef const MVT* vt_iterator; 63 typedef const TargetRegisterClass* const * sc_iterator; 64private: 65 unsigned ID; 66 bool isSubClass; 67 const vt_iterator VTs; 68 const sc_iterator SubClasses; 69 const sc_iterator SuperClasses; 70 const sc_iterator SubRegClasses; 71 const sc_iterator SuperRegClasses; 72 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 73 const int CopyCost; 74 const iterator RegsBegin, RegsEnd; 75public: 76 TargetRegisterClass(unsigned id, 77 const MVT *vts, 78 const TargetRegisterClass * const *subcs, 79 const TargetRegisterClass * const *supcs, 80 const TargetRegisterClass * const *subregcs, 81 const TargetRegisterClass * const *superregcs, 82 unsigned RS, unsigned Al, int CC, 83 iterator RB, iterator RE) 84 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 85 SubRegClasses(subregcs), SuperRegClasses(superregcs), 86 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {} 87 virtual ~TargetRegisterClass() {} // Allow subclasses 88 89 /// getID() - Return the register class ID number. 90 /// 91 unsigned getID() const { return ID; } 92 93 /// begin/end - Return all of the registers in this class. 94 /// 95 iterator begin() const { return RegsBegin; } 96 iterator end() const { return RegsEnd; } 97 98 /// getNumRegs - Return the number of registers in this class. 99 /// 100 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 101 102 /// getRegister - Return the specified register in the class. 103 /// 104 unsigned getRegister(unsigned i) const { 105 assert(i < getNumRegs() && "Register number out of range!"); 106 return RegsBegin[i]; 107 } 108 109 /// contains - Return true if the specified register is included in this 110 /// register class. 111 bool contains(unsigned Reg) const { 112 for (iterator I = begin(), E = end(); I != E; ++I) 113 if (*I == Reg) return true; 114 return false; 115 } 116 117 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 118 /// 119 bool hasType(MVT vt) const { 120 for(int i = 0; VTs[i] != MVT::Other; ++i) 121 if (VTs[i] == vt) 122 return true; 123 return false; 124 } 125 126 /// vt_begin / vt_end - Loop over all of the value types that can be 127 /// represented by values in this register class. 128 vt_iterator vt_begin() const { 129 return VTs; 130 } 131 132 vt_iterator vt_end() const { 133 vt_iterator I = VTs; 134 while (*I != MVT::Other) ++I; 135 return I; 136 } 137 138 /// hasSubClass - return true if the specified TargetRegisterClass is a 139 /// sub-register class of this TargetRegisterClass. 140 bool hasSubClass(const TargetRegisterClass *cs) const { 141 for (int i = 0; SubClasses[i] != NULL; ++i) 142 if (SubClasses[i] == cs) 143 return true; 144 return false; 145 } 146 147 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of 148 /// this register class. 149 sc_iterator subclasses_begin() const { 150 return SubClasses; 151 } 152 153 sc_iterator subclasses_end() const { 154 sc_iterator I = SubClasses; 155 while (*I != NULL) ++I; 156 return I; 157 } 158 159 /// hasSuperClass - return true if the specified TargetRegisterClass is a 160 /// super-register class of this TargetRegisterClass. 161 bool hasSuperClass(const TargetRegisterClass *cs) const { 162 for (int i = 0; SuperClasses[i] != NULL; ++i) 163 if (SuperClasses[i] == cs) 164 return true; 165 return false; 166 } 167 168 /// superclasses_begin / superclasses_end - Loop over all of the super-classes 169 /// of this register class. 170 sc_iterator superclasses_begin() const { 171 return SuperClasses; 172 } 173 174 sc_iterator superclasses_end() const { 175 sc_iterator I = SuperClasses; 176 while (*I != NULL) ++I; 177 return I; 178 } 179 180 /// hasSubRegClass - return true if the specified TargetRegisterClass is a 181 /// class of a sub-register class for this TargetRegisterClass. 182 bool hasSubRegClass(const TargetRegisterClass *cs) const { 183 for (int i = 0; SubRegClasses[i] != NULL; ++i) 184 if (SubRegClasses[i] == cs) 185 return true; 186 return false; 187 } 188 189 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a 190 /// class of a sub-register class for this TargetRegisterClass. 191 bool hasClassForSubReg(unsigned SubReg) const { 192 --SubReg; 193 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 194 if (i == SubReg) 195 return true; 196 return false; 197 } 198 199 /// getClassForSubReg - return theTargetRegisterClass for the sub-register 200 /// at idx for this TargetRegisterClass. 201 sc_iterator getClassForSubReg(unsigned SubReg) const { 202 --SubReg; 203 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 204 if (i == SubReg) 205 return &SubRegClasses[i]; 206 assert(0 && "Invalid subregister index for register class"); 207 return NULL; 208 } 209 210 /// subregclasses_begin / subregclasses_end - Loop over all of 211 /// the subregister classes of this register class. 212 sc_iterator subregclasses_begin() const { 213 return SubRegClasses; 214 } 215 216 sc_iterator subregclasses_end() const { 217 sc_iterator I = SubRegClasses; 218 while (*I != NULL) ++I; 219 return I; 220 } 221 222 /// superregclasses_begin / superregclasses_end - Loop over all of 223 /// the superregister classes of this register class. 224 sc_iterator superregclasses_begin() const { 225 return SuperRegClasses; 226 } 227 228 sc_iterator superregclasses_end() const { 229 sc_iterator I = SuperRegClasses; 230 while (*I != NULL) ++I; 231 return I; 232 } 233 234 /// allocation_order_begin/end - These methods define a range of registers 235 /// which specify the registers in this class that are valid to register 236 /// allocate, and the preferred order to allocate them in. For example, 237 /// callee saved registers should be at the end of the list, because it is 238 /// cheaper to allocate caller saved registers. 239 /// 240 /// These methods take a MachineFunction argument, which can be used to tune 241 /// the allocatable registers based on the characteristics of the function. 242 /// One simple example is that the frame pointer register can be used if 243 /// frame-pointer-elimination is performed. 244 /// 245 /// By default, these methods return all registers in the class. 246 /// 247 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 248 return begin(); 249 } 250 virtual iterator allocation_order_end(const MachineFunction &MF) const { 251 return end(); 252 } 253 254 255 256 /// getSize - Return the size of the register in bytes, which is also the size 257 /// of a stack slot allocated to hold a spilled copy of this register. 258 unsigned getSize() const { return RegSize; } 259 260 /// getAlignment - Return the minimum required alignment for a register of 261 /// this class. 262 unsigned getAlignment() const { return Alignment; } 263 264 /// getCopyCost - Return the cost of copying a value between two registers in 265 /// this class. 266 int getCopyCost() const { return CopyCost; } 267}; 268 269 270/// TargetRegisterInfo base class - We assume that the target defines a static 271/// array of TargetRegisterDesc objects that represent all of the machine 272/// registers that the target has. As such, we simply have to track a pointer 273/// to this array so that we can turn register number into a register 274/// descriptor. 275/// 276class TargetRegisterInfo { 277protected: 278 unsigned* SubregHash; 279 unsigned SubregHashSize; 280public: 281 typedef const TargetRegisterClass * const * regclass_iterator; 282private: 283 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 284 unsigned NumRegs; // Number of entries in the array 285 286 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 287 288 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 289protected: 290 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 291 regclass_iterator RegClassBegin, 292 regclass_iterator RegClassEnd, 293 int CallFrameSetupOpcode = -1, 294 int CallFrameDestroyOpcode = -1); 295 virtual ~TargetRegisterInfo(); 296public: 297 298 enum { // Define some target independent constants 299 /// NoRegister - This physical register is not a real target register. It 300 /// is useful as a sentinal. 301 NoRegister = 0, 302 303 /// FirstVirtualRegister - This is the first register number that is 304 /// considered to be a 'virtual' register, which is part of the SSA 305 /// namespace. This must be the same for all targets, which means that each 306 /// target is limited to 1024 registers. 307 FirstVirtualRegister = 1024 308 }; 309 310 /// isPhysicalRegister - Return true if the specified register number is in 311 /// the physical register namespace. 312 static bool isPhysicalRegister(unsigned Reg) { 313 assert(Reg && "this is not a register!"); 314 return Reg < FirstVirtualRegister; 315 } 316 317 /// isVirtualRegister - Return true if the specified register number is in 318 /// the virtual register namespace. 319 static bool isVirtualRegister(unsigned Reg) { 320 assert(Reg && "this is not a register!"); 321 return Reg >= FirstVirtualRegister; 322 } 323 324 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 325 /// register of the given type. If type is MVT::Other, then just return any 326 /// register class the register belongs to. 327 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg, 328 MVT VT = MVT::Other) const; 329 330 /// getAllocatableSet - Returns a bitset indexed by register number 331 /// indicating if a register is allocatable or not. If a register class is 332 /// specified, returns the subset for the class. 333 BitVector getAllocatableSet(MachineFunction &MF, 334 const TargetRegisterClass *RC = NULL) const; 335 336 const TargetRegisterDesc &operator[](unsigned RegNo) const { 337 assert(RegNo < NumRegs && 338 "Attempting to access record for invalid register number!"); 339 return Desc[RegNo]; 340 } 341 342 /// Provide a get method, equivalent to [], but more useful if we have a 343 /// pointer to this object. 344 /// 345 const TargetRegisterDesc &get(unsigned RegNo) const { 346 return operator[](RegNo); 347 } 348 349 /// getAliasSet - Return the set of registers aliased by the specified 350 /// register, or a null list of there are none. The list returned is zero 351 /// terminated. 352 /// 353 const unsigned *getAliasSet(unsigned RegNo) const { 354 return get(RegNo).AliasSet; 355 } 356 357 /// getSubRegisters - Return the list of registers that are sub-registers of 358 /// the specified register, or a null list of there are none. The list 359 /// returned is zero terminated and sorted according to super-sub register 360 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 361 /// 362 const unsigned *getSubRegisters(unsigned RegNo) const { 363 return get(RegNo).SubRegs; 364 } 365 366 /// getSuperRegisters - Return the list of registers that are super-registers 367 /// of the specified register, or a null list of there are none. The list 368 /// returned is zero terminated and sorted according to super-sub register 369 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 370 /// 371 const unsigned *getSuperRegisters(unsigned RegNo) const { 372 return get(RegNo).SuperRegs; 373 } 374 375 /// getAsmName - Return the symbolic target-specific name for the 376 /// specified physical register. 377 const char *getAsmName(unsigned RegNo) const { 378 return get(RegNo).AsmName; 379 } 380 381 /// getName - Return the human-readable symbolic target-specific name for the 382 /// specified physical register. 383 const char *getName(unsigned RegNo) const { 384 return get(RegNo).Name; 385 } 386 387 /// getNumRegs - Return the number of registers this target has (useful for 388 /// sizing arrays holding per register information) 389 unsigned getNumRegs() const { 390 return NumRegs; 391 } 392 393 /// areAliases - Returns true if the two registers alias each other, false 394 /// otherwise 395 bool areAliases(unsigned regA, unsigned regB) const { 396 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias) 397 if (*Alias == regB) return true; 398 return false; 399 } 400 401 /// regsOverlap - Returns true if the two registers are equal or alias each 402 /// other. The registers may be virtual register. 403 bool regsOverlap(unsigned regA, unsigned regB) const { 404 if (regA == regB) 405 return true; 406 407 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 408 return false; 409 return areAliases(regA, regB); 410 } 411 412 /// isSubRegister - Returns true if regB is a sub-register of regA. 413 /// 414 bool isSubRegister(unsigned regA, unsigned regB) const { 415 // SubregHash is a simple quadratically probed hash table. 416 size_t index = (regA + regB * 37) & (SubregHashSize-1); 417 unsigned ProbeAmt = 2; 418 while (SubregHash[index*2] != 0 && 419 SubregHash[index*2+1] != 0) { 420 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 421 return true; 422 423 index = (index + ProbeAmt) & (SubregHashSize-1); 424 ProbeAmt += 2; 425 } 426 427 return false; 428 } 429 430 /// isSuperRegister - Returns true if regB is a super-register of regA. 431 /// 432 bool isSuperRegister(unsigned regA, unsigned regB) const { 433 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR) 434 if (*SR == regB) return true; 435 return false; 436 } 437 438 /// getCalleeSavedRegs - Return a null-terminated list of all of the 439 /// callee saved registers on this target. The register should be in the 440 /// order of desired callee-save stack frame offset. The first register is 441 /// closed to the incoming stack pointer if stack grows down, and vice versa. 442 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 443 const = 0; 444 445 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 446 /// register classes to spill each callee saved register with. The order and 447 /// length of this list match the getCalleeSaveRegs() list. 448 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( 449 const MachineFunction *MF) const =0; 450 451 /// getReservedRegs - Returns a bitset indexed by physical register number 452 /// indicating if a register is a special register that has particular uses 453 /// and should be considered unavailable at all times, e.g. SP, RA. This is 454 /// used by register scavenger to determine what registers are free. 455 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 456 457 /// getSubReg - Returns the physical register number of sub-register "Index" 458 /// for physical register RegNo. 459 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 460 461 //===--------------------------------------------------------------------===// 462 // Register Class Information 463 // 464 465 /// Register class iterators 466 /// 467 regclass_iterator regclass_begin() const { return RegClassBegin; } 468 regclass_iterator regclass_end() const { return RegClassEnd; } 469 470 unsigned getNumRegClasses() const { 471 return (unsigned)(regclass_end()-regclass_begin()); 472 } 473 474 /// getRegClass - Returns the register class associated with the enumeration 475 /// value. See class TargetOperandInfo. 476 const TargetRegisterClass *getRegClass(unsigned i) const { 477 assert(i <= getNumRegClasses() && "Register Class ID out of range"); 478 return i ? RegClassBegin[i - 1] : NULL; 479 } 480 481 //===--------------------------------------------------------------------===// 482 // Interfaces used by the register allocator and stack frame 483 // manipulation passes to move data around between registers, 484 // immediates and memory. FIXME: Move these to TargetInstrInfo.h. 485 // 486 487 /// getCrossCopyRegClass - Returns a legal register class to copy a register 488 /// in the specified class to or from. Returns NULL if it is possible to copy 489 /// between a two registers of the specified class. 490 virtual const TargetRegisterClass * 491 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 492 return NULL; 493 } 494 495 /// targetHandlesStackFrameRounding - Returns true if the target is 496 /// responsible for rounding up the stack frame (probably at emitPrologue 497 /// time). 498 virtual bool targetHandlesStackFrameRounding() const { 499 return false; 500 } 501 502 /// requiresRegisterScavenging - returns true if the target requires (and can 503 /// make use of) the register scavenger. 504 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 505 return false; 506 } 507 508 /// hasFP - Return true if the specified function should have a dedicated 509 /// frame pointer register. For most targets this is true only if the function 510 /// has variable sized allocas or if frame pointer elimination is disabled. 511 virtual bool hasFP(const MachineFunction &MF) const = 0; 512 513 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is 514 // not required, we reserve argument space for call sites in the function 515 // immediately on entry to the current function. This eliminates the need for 516 // add/sub sp brackets around call sites. Returns true if the call frame is 517 // included as part of the stack frame. 518 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 519 return !hasFP(MF); 520 } 521 522 // needsStackRealignment - true if storage within the function requires the 523 // stack pointer to be aligned more than the normal calling convention calls 524 // for. 525 virtual bool needsStackRealignment(const MachineFunction &MF) const { 526 return false; 527 } 528 529 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 530 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 531 /// targets use pseudo instructions in order to abstract away the difference 532 /// between operating with a frame pointer and operating without, through the 533 /// use of these two instructions. 534 /// 535 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 536 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 537 538 539 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 540 /// code insertion to eliminate call frame setup and destroy pseudo 541 /// instructions (but only if the Target is using them). It is responsible 542 /// for eliminating these instructions, replacing them with concrete 543 /// instructions. This method need only be implemented if using call frame 544 /// setup/destroy pseudo instructions. 545 /// 546 virtual void 547 eliminateCallFramePseudoInstr(MachineFunction &MF, 548 MachineBasicBlock &MBB, 549 MachineBasicBlock::iterator MI) const { 550 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 551 "eliminateCallFramePseudoInstr must be implemented if using" 552 " call frame setup/destroy pseudo instructions!"); 553 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 554 } 555 556 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 557 /// before PrologEpilogInserter scans the physical registers used to determine 558 /// what callee saved registers should be spilled. This method is optional. 559 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 560 RegScavenger *RS = NULL) const { 561 562 } 563 564 /// processFunctionBeforeFrameFinalized - This method is called immediately 565 /// before the specified functions frame layout (MF.getFrameInfo()) is 566 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 567 /// replaced with direct constants. This method is optional. 568 /// 569 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 570 } 571 572 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 573 /// frame indices from instructions which may use them. The instruction 574 /// referenced by the iterator contains an MO_FrameIndex operand which must be 575 /// eliminated by this method. This method may modify or replace the 576 /// specified instruction, as long as it keeps the iterator pointing the the 577 /// finished product. SPAdj is the SP adjustment due to call frame setup 578 /// instruction. The return value is the number of instructions added to 579 /// (negative if removed from) the basic block. 580 /// 581 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 582 int SPAdj, RegScavenger *RS=NULL) const = 0; 583 584 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 585 /// the function. The return value is the number of instructions 586 /// added to (negative if removed from) the basic block (entry for prologue). 587 /// 588 virtual void emitPrologue(MachineFunction &MF) const = 0; 589 virtual void emitEpilogue(MachineFunction &MF, 590 MachineBasicBlock &MBB) const = 0; 591 592 //===--------------------------------------------------------------------===// 593 /// Debug information queries. 594 595 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 596 /// number. Returns -1 if there is no equivalent value. The second 597 /// parameter allows targets to use different numberings for EH info and 598 /// deubgging info. 599 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 600 601 /// getFrameRegister - This method should return the register used as a base 602 /// for values allocated in the current stack frame. 603 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 604 605 /// getFrameIndexOffset - Returns the displacement from the frame register to 606 /// the stack frame of the specified index. 607 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; 608 609 /// getRARegister - This method should return the register where the return 610 /// address can be found. 611 virtual unsigned getRARegister() const = 0; 612 613 /// getInitialFrameState - Returns a list of machine moves that are assumed 614 /// on entry to all functions. Note that LabelID is ignored (assumed to be 615 /// the beginning of the function.) 616 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 617}; 618 619// This is useful when building IndexedMaps keyed on virtual registers 620struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 621 unsigned operator()(unsigned Reg) const { 622 return Reg - TargetRegisterInfo::FirstVirtualRegister; 623 } 624}; 625 626} // End llvm namespace 627 628#endif 629