TargetRegisterInfo.h revision b3acdcc00c9dfb01663780e858e586cc5f04423f
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/MC/MCRegisterInfo.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/ValueTypes.h" 22#include "llvm/ADT/ArrayRef.h" 23#include "llvm/CallingConv.h" 24#include <cassert> 25#include <functional> 26 27namespace llvm { 28 29class BitVector; 30class MachineFunction; 31class RegScavenger; 32template<class T> class SmallVectorImpl; 33class raw_ostream; 34 35class TargetRegisterClass { 36public: 37 typedef const unsigned* iterator; 38 typedef const unsigned* const_iterator; 39 typedef const MVT::SimpleValueType* vt_iterator; 40 typedef const TargetRegisterClass* const * sc_iterator; 41 42 // Instance variables filled by tablegen, do not use! 43 const MCRegisterClass *MC; 44 const vt_iterator VTs; 45 const unsigned *SubClassMask; 46 const sc_iterator SuperClasses; 47 const sc_iterator SuperRegClasses; 48 ArrayRef<unsigned> (*OrderFunc)(const MachineFunction&); 49 50 /// getID() - Return the register class ID number. 51 /// 52 unsigned getID() const { return MC->getID(); } 53 54 /// getName() - Return the register class name for debugging. 55 /// 56 const char *getName() const { return MC->getName(); } 57 58 /// begin/end - Return all of the registers in this class. 59 /// 60 iterator begin() const { return MC->begin(); } 61 iterator end() const { return MC->end(); } 62 63 /// getNumRegs - Return the number of registers in this class. 64 /// 65 unsigned getNumRegs() const { return MC->getNumRegs(); } 66 67 /// getRegister - Return the specified register in the class. 68 /// 69 unsigned getRegister(unsigned i) const { 70 return MC->getRegister(i); 71 } 72 73 /// contains - Return true if the specified register is included in this 74 /// register class. This does not include virtual registers. 75 bool contains(unsigned Reg) const { 76 return MC->contains(Reg); 77 } 78 79 /// contains - Return true if both registers are in this class. 80 bool contains(unsigned Reg1, unsigned Reg2) const { 81 return MC->contains(Reg1, Reg2); 82 } 83 84 /// getSize - Return the size of the register in bytes, which is also the size 85 /// of a stack slot allocated to hold a spilled copy of this register. 86 unsigned getSize() const { return MC->getSize(); } 87 88 /// getAlignment - Return the minimum required alignment for a register of 89 /// this class. 90 unsigned getAlignment() const { return MC->getAlignment(); } 91 92 /// getCopyCost - Return the cost of copying a value between two registers in 93 /// this class. A negative number means the register class is very expensive 94 /// to copy e.g. status flag register classes. 95 int getCopyCost() const { return MC->getCopyCost(); } 96 97 /// isAllocatable - Return true if this register class may be used to create 98 /// virtual registers. 99 bool isAllocatable() const { return MC->isAllocatable(); } 100 101 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 102 /// 103 bool hasType(EVT vt) const { 104 for(int i = 0; VTs[i] != MVT::Other; ++i) 105 if (EVT(VTs[i]) == vt) 106 return true; 107 return false; 108 } 109 110 /// vt_begin / vt_end - Loop over all of the value types that can be 111 /// represented by values in this register class. 112 vt_iterator vt_begin() const { 113 return VTs; 114 } 115 116 vt_iterator vt_end() const { 117 vt_iterator I = VTs; 118 while (*I != MVT::Other) ++I; 119 return I; 120 } 121 122 /// superregclasses_begin / superregclasses_end - Loop over all of 123 /// the superreg register classes of this register class. 124 sc_iterator superregclasses_begin() const { 125 return SuperRegClasses; 126 } 127 128 sc_iterator superregclasses_end() const { 129 sc_iterator I = SuperRegClasses; 130 while (*I != NULL) ++I; 131 return I; 132 } 133 134 /// hasSubClass - return true if the specified TargetRegisterClass 135 /// is a proper sub-class of this TargetRegisterClass. 136 bool hasSubClass(const TargetRegisterClass *RC) const { 137 return RC != this && hasSubClassEq(RC); 138 } 139 140 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 141 /// class. 142 bool hasSubClassEq(const TargetRegisterClass *RC) const { 143 unsigned ID = RC->getID(); 144 return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 145 } 146 147 /// hasSuperClass - return true if the specified TargetRegisterClass is a 148 /// proper super-class of this TargetRegisterClass. 149 bool hasSuperClass(const TargetRegisterClass *RC) const { 150 return RC->hasSubClass(this); 151 } 152 153 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 154 /// class. 155 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 156 return RC->hasSubClassEq(this); 157 } 158 159 /// getSubClassMask - Returns a bit vector of subclasses, including this one. 160 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 161 /// use it. 162 const unsigned *getSubClassMask() const { 163 return SubClassMask; 164 } 165 166 /// getSuperClasses - Returns a NULL terminated list of super-classes. The 167 /// classes are ordered by ID which is also a topological ordering from large 168 /// to small classes. The list does NOT include the current class. 169 sc_iterator getSuperClasses() const { 170 return SuperClasses; 171 } 172 173 /// isASubClass - return true if this TargetRegisterClass is a subset 174 /// class of at least one other TargetRegisterClass. 175 bool isASubClass() const { 176 return SuperClasses[0] != 0; 177 } 178 179 /// getRawAllocationOrder - Returns the preferred order for allocating 180 /// registers from this register class in MF. The raw order comes directly 181 /// from the .td file and may include reserved registers that are not 182 /// allocatable. Register allocators should also make sure to allocate 183 /// callee-saved registers only after all the volatiles are used. The 184 /// RegisterClassInfo class provides filtered allocation orders with 185 /// callee-saved registers moved to the end. 186 /// 187 /// The MachineFunction argument can be used to tune the allocatable 188 /// registers based on the characteristics of the function, subtarget, or 189 /// other criteria. 190 /// 191 /// By default, this method returns all registers in the class. 192 /// 193 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { 194 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 195 } 196}; 197 198/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 199/// registers. These are used by codegen, not by MC. 200struct TargetRegisterInfoDesc { 201 unsigned CostPerUse; // Extra cost of instructions using register. 202 bool inAllocatableClass; // Register belongs to an allocatable regclass. 203}; 204 205/// TargetRegisterInfo base class - We assume that the target defines a static 206/// array of TargetRegisterDesc objects that represent all of the machine 207/// registers that the target has. As such, we simply have to track a pointer 208/// to this array so that we can turn register number into a register 209/// descriptor. 210/// 211class TargetRegisterInfo : public MCRegisterInfo { 212public: 213 typedef const TargetRegisterClass * const * regclass_iterator; 214private: 215 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 216 const char *const *SubRegIndexNames; // Names of subreg indexes. 217 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 218 219protected: 220 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 221 regclass_iterator RegClassBegin, 222 regclass_iterator RegClassEnd, 223 const char *const *subregindexnames); 224 virtual ~TargetRegisterInfo(); 225public: 226 227 // Register numbers can represent physical registers, virtual registers, and 228 // sometimes stack slots. The unsigned values are divided into these ranges: 229 // 230 // 0 Not a register, can be used as a sentinel. 231 // [1;2^30) Physical registers assigned by TableGen. 232 // [2^30;2^31) Stack slots. (Rarely used.) 233 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 234 // 235 // Further sentinels can be allocated from the small negative integers. 236 // DenseMapInfo<unsigned> uses -1u and -2u. 237 238 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 239 /// frame index in a variable that normally holds a register. isStackSlot() 240 /// returns true if Reg is in the range used for stack slots. 241 /// 242 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 243 /// slots, so if a variable may contains a stack slot, always check 244 /// isStackSlot() first. 245 /// 246 static bool isStackSlot(unsigned Reg) { 247 return int(Reg) >= (1 << 30); 248 } 249 250 /// stackSlot2Index - Compute the frame index from a register value 251 /// representing a stack slot. 252 static int stackSlot2Index(unsigned Reg) { 253 assert(isStackSlot(Reg) && "Not a stack slot"); 254 return int(Reg - (1u << 30)); 255 } 256 257 /// index2StackSlot - Convert a non-negative frame index to a stack slot 258 /// register value. 259 static unsigned index2StackSlot(int FI) { 260 assert(FI >= 0 && "Cannot hold a negative frame index."); 261 return FI + (1u << 30); 262 } 263 264 /// isPhysicalRegister - Return true if the specified register number is in 265 /// the physical register namespace. 266 static bool isPhysicalRegister(unsigned Reg) { 267 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 268 return int(Reg) > 0; 269 } 270 271 /// isVirtualRegister - Return true if the specified register number is in 272 /// the virtual register namespace. 273 static bool isVirtualRegister(unsigned Reg) { 274 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 275 return int(Reg) < 0; 276 } 277 278 /// virtReg2Index - Convert a virtual register number to a 0-based index. 279 /// The first virtual register in a function will get the index 0. 280 static unsigned virtReg2Index(unsigned Reg) { 281 assert(isVirtualRegister(Reg) && "Not a virtual register"); 282 return Reg & ~(1u << 31); 283 } 284 285 /// index2VirtReg - Convert a 0-based index to a virtual register number. 286 /// This is the inverse operation of VirtReg2IndexFunctor below. 287 static unsigned index2VirtReg(unsigned Index) { 288 return Index | (1u << 31); 289 } 290 291 /// getMinimalPhysRegClass - Returns the Register Class of a physical 292 /// register of the given type, picking the most sub register class of 293 /// the right type that contains this physreg. 294 const TargetRegisterClass * 295 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 296 297 /// getAllocatableSet - Returns a bitset indexed by register number 298 /// indicating if a register is allocatable or not. If a register class is 299 /// specified, returns the subset for the class. 300 BitVector getAllocatableSet(const MachineFunction &MF, 301 const TargetRegisterClass *RC = NULL) const; 302 303 /// getCostPerUse - Return the additional cost of using this register instead 304 /// of other registers in its class. 305 unsigned getCostPerUse(unsigned RegNo) const { 306 return InfoDesc[RegNo].CostPerUse; 307 } 308 309 /// isInAllocatableClass - Return true if the register is in the allocation 310 /// of any register class. 311 bool isInAllocatableClass(unsigned RegNo) const { 312 return InfoDesc[RegNo].inAllocatableClass; 313 } 314 315 /// getSubRegIndexName - Return the human-readable symbolic target-specific 316 /// name for the specified SubRegIndex. 317 const char *getSubRegIndexName(unsigned SubIdx) const { 318 assert(SubIdx && "This is not a subregister index"); 319 return SubRegIndexNames[SubIdx-1]; 320 } 321 322 /// regsOverlap - Returns true if the two registers are equal or alias each 323 /// other. The registers may be virtual register. 324 bool regsOverlap(unsigned regA, unsigned regB) const { 325 if (regA == regB) return true; 326 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 327 return false; 328 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { 329 if (*regList == regB) return true; 330 } 331 return false; 332 } 333 334 /// isSubRegister - Returns true if regB is a sub-register of regA. 335 /// 336 bool isSubRegister(unsigned regA, unsigned regB) const { 337 return isSuperRegister(regB, regA); 338 } 339 340 /// isSuperRegister - Returns true if regB is a super-register of regA. 341 /// 342 bool isSuperRegister(unsigned regA, unsigned regB) const { 343 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ 344 if (*regList == regB) return true; 345 } 346 return false; 347 } 348 349 /// getCalleeSavedRegs - Return a null-terminated list of all of the 350 /// callee saved registers on this target. The register should be in the 351 /// order of desired callee-save stack frame offset. The first register is 352 /// closest to the incoming stack pointer if stack grows down, and vice versa. 353 /// 354 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 355 const = 0; 356 357 /// getCallPreservedMask - Return a mask of call-preserved registers for the 358 /// given calling convention on the current sub-target. The mask should 359 /// include all call-preserved aliases. This is used by the register 360 /// allocator to determine which registers can be live across a call. 361 /// 362 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 363 /// A set bit indicates that all bits of the corresponding register are 364 /// preserved across the function call. The bit mask is expected to be 365 /// sub-register complete, i.e. if A is preserved, so are all its 366 /// sub-registers. 367 /// 368 /// Bits are numbered from the LSB, so the bit for physical register Reg can 369 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 370 /// 371 /// A NULL pointer means that no register mask will be used, and call 372 /// instructions should use implicit-def operands to indicate call clobbered 373 /// registers. 374 /// 375 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 376 // The default mask clobbers everything. All targets should override. 377 return 0; 378 } 379 380 /// getReservedRegs - Returns a bitset indexed by physical register number 381 /// indicating if a register is a special register that has particular uses 382 /// and should be considered unavailable at all times, e.g. SP, RA. This is 383 /// used by register scavenger to determine what registers are free. 384 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 385 386 /// getSubRegIndex - For a given register pair, return the sub-register index 387 /// if the second register is a sub-register of the first. Return zero 388 /// otherwise. 389 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 390 391 /// getMatchingSuperReg - Return a super-register of the specified register 392 /// Reg so its sub-register of index SubIdx is Reg. 393 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 394 const TargetRegisterClass *RC) const { 395 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 396 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 397 return SR; 398 return 0; 399 } 400 401 /// canCombineSubRegIndices - Given a register class and a list of 402 /// subregister indices, return true if it's possible to combine the 403 /// subregister indices into one that corresponds to a larger 404 /// subregister. Return the new subregister index by reference. Note the 405 /// new index may be zero if the given subregisters can be combined to 406 /// form the whole register. 407 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 408 SmallVectorImpl<unsigned> &SubIndices, 409 unsigned &NewSubIdx) const { 410 return 0; 411 } 412 413 /// getMatchingSuperRegClass - Return a subclass of the specified register 414 /// class A so that each register in it has a sub-register of the 415 /// specified sub-register index which is in the specified register class B. 416 /// 417 /// TableGen will synthesize missing A sub-classes. 418 virtual const TargetRegisterClass * 419 getMatchingSuperRegClass(const TargetRegisterClass *A, 420 const TargetRegisterClass *B, unsigned Idx) const =0; 421 422 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 423 /// supports the sub-register index Idx. 424 /// If no such sub-class exists, return NULL. 425 /// If all registers in RC already have an Idx sub-register, return RC. 426 /// 427 /// TableGen generates a version of this function that is good enough in most 428 /// cases. Targets can override if they have constraints that TableGen 429 /// doesn't understand. For example, the x86 sub_8bit sub-register index is 430 /// supported by the full GR32 register class in 64-bit mode, but only by the 431 /// GR32_ABCD regiister class in 32-bit mode. 432 /// 433 /// TableGen will synthesize missing RC sub-classes. 434 virtual const TargetRegisterClass * 435 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0; 436 437 /// composeSubRegIndices - Return the subregister index you get from composing 438 /// two subregister indices. 439 /// 440 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 441 /// returns c. Note that composeSubRegIndices does not tell you about illegal 442 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 443 /// b, composeSubRegIndices doesn't tell you. 444 /// 445 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 446 /// ssub_0:S0 - ssub_3:S3 subregs. 447 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 448 /// 449 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 450 // This default implementation is correct for most targets. 451 return b; 452 } 453 454 //===--------------------------------------------------------------------===// 455 // Register Class Information 456 // 457 458 /// Register class iterators 459 /// 460 regclass_iterator regclass_begin() const { return RegClassBegin; } 461 regclass_iterator regclass_end() const { return RegClassEnd; } 462 463 unsigned getNumRegClasses() const { 464 return (unsigned)(regclass_end()-regclass_begin()); 465 } 466 467 /// getRegClass - Returns the register class associated with the enumeration 468 /// value. See class MCOperandInfo. 469 const TargetRegisterClass *getRegClass(unsigned i) const { 470 assert(i < getNumRegClasses() && "Register Class ID out of range"); 471 return RegClassBegin[i]; 472 } 473 474 /// getCommonSubClass - find the largest common subclass of A and B. Return 475 /// NULL if there is no common subclass. 476 const TargetRegisterClass * 477 getCommonSubClass(const TargetRegisterClass *A, 478 const TargetRegisterClass *B) const; 479 480 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 481 /// values. If a target supports multiple different pointer register classes, 482 /// kind specifies which one is indicated. 483 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 484 llvm_unreachable("Target didn't implement getPointerRegClass!"); 485 } 486 487 /// getCrossCopyRegClass - Returns a legal register class to copy a register 488 /// in the specified class to or from. If it is possible to copy the register 489 /// directly without using a cross register class copy, return the specified 490 /// RC. Returns NULL if it is not possible to copy between a two registers of 491 /// the specified class. 492 virtual const TargetRegisterClass * 493 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 494 return RC; 495 } 496 497 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 498 /// legal to use in the current sub-target and has the same spill size. 499 /// The returned register class can be used to create virtual registers which 500 /// means that all its registers can be copied and spilled. 501 virtual const TargetRegisterClass* 502 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 503 /// The default implementation is very conservative and doesn't allow the 504 /// register allocator to inflate register classes. 505 return RC; 506 } 507 508 /// getRegPressureLimit - Return the register pressure "high water mark" for 509 /// the specific register class. The scheduler is in high register pressure 510 /// mode (for the specific register class) if it goes over the limit. 511 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 512 MachineFunction &MF) const { 513 return 0; 514 } 515 516 /// getRawAllocationOrder - Returns the register allocation order for a 517 /// specified register class with a target-dependent hint. The returned list 518 /// may contain reserved registers that cannot be allocated. 519 /// 520 /// Register allocators need only call this function to resolve 521 /// target-dependent hints, but it should work without hinting as well. 522 virtual ArrayRef<unsigned> 523 getRawAllocationOrder(const TargetRegisterClass *RC, 524 unsigned HintType, unsigned HintReg, 525 const MachineFunction &MF) const { 526 return RC->getRawAllocationOrder(MF); 527 } 528 529 /// ResolveRegAllocHint - Resolves the specified register allocation hint 530 /// to a physical register. Returns the physical register if it is successful. 531 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 532 const MachineFunction &MF) const { 533 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 534 return Reg; 535 return 0; 536 } 537 538 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 539 /// writing a register from RC in two consecutive instructions. 540 /// This can avoid pipeline stalls on certain architectures. 541 /// It does cause increased register pressure, though. 542 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 543 return false; 544 } 545 546 /// UpdateRegAllocHint - A callback to allow target a chance to update 547 /// register allocation hints when a register is "changed" (e.g. coalesced) 548 /// to another register. e.g. On ARM, some virtual registers should target 549 /// register pairs, if one of pair is coalesced to another register, the 550 /// allocation hint of the other half of the pair should be changed to point 551 /// to the new register. 552 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 553 MachineFunction &MF) const { 554 // Do nothing. 555 } 556 557 /// requiresRegisterScavenging - returns true if the target requires (and can 558 /// make use of) the register scavenger. 559 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 560 return false; 561 } 562 563 /// useFPForScavengingIndex - returns true if the target wants to use 564 /// frame pointer based accesses to spill to the scavenger emergency spill 565 /// slot. 566 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 567 return true; 568 } 569 570 /// requiresFrameIndexScavenging - returns true if the target requires post 571 /// PEI scavenging of registers for materializing frame index constants. 572 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 573 return false; 574 } 575 576 /// requiresVirtualBaseRegisters - Returns true if the target wants the 577 /// LocalStackAllocation pass to be run and virtual base registers 578 /// used for more efficient stack access. 579 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 580 return false; 581 } 582 583 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 584 /// the stack frame of the given function for the specified register. e.g. On 585 /// x86, if the frame register is required, the first fixed stack object is 586 /// reserved as its spill slot. This tells PEI not to create a new stack frame 587 /// object for the given register. It should be called only after 588 /// processFunctionBeforeCalleeSavedScan(). 589 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 590 int &FrameIdx) const { 591 return false; 592 } 593 594 /// needsStackRealignment - true if storage within the function requires the 595 /// stack pointer to be aligned more than the normal calling convention calls 596 /// for. 597 virtual bool needsStackRealignment(const MachineFunction &MF) const { 598 return false; 599 } 600 601 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 602 /// index in the instruction, if there is one. 603 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 604 int Idx) const { 605 return 0; 606 } 607 608 /// needsFrameBaseReg - Returns true if the instruction's frame index 609 /// reference would be better served by a base register other than FP 610 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 611 /// references it should create new base registers for. 612 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 613 return false; 614 } 615 616 /// materializeFrameBaseRegister - Insert defining instruction(s) for 617 /// BaseReg to be a pointer to FrameIdx before insertion point I. 618 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 619 unsigned BaseReg, int FrameIdx, 620 int64_t Offset) const { 621 llvm_unreachable("materializeFrameBaseRegister does not exist on this " 622 "target"); 623 } 624 625 /// resolveFrameIndex - Resolve a frame index operand of an instruction 626 /// to reference the indicated base register plus offset instead. 627 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 628 unsigned BaseReg, int64_t Offset) const { 629 llvm_unreachable("resolveFrameIndex does not exist on this target"); 630 } 631 632 /// isFrameOffsetLegal - Determine whether a given offset immediate is 633 /// encodable to resolve a frame index. 634 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 635 int64_t Offset) const { 636 llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 637 } 638 639 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 640 /// code insertion to eliminate call frame setup and destroy pseudo 641 /// instructions (but only if the Target is using them). It is responsible 642 /// for eliminating these instructions, replacing them with concrete 643 /// instructions. This method need only be implemented if using call frame 644 /// setup/destroy pseudo instructions. 645 /// 646 virtual void 647 eliminateCallFramePseudoInstr(MachineFunction &MF, 648 MachineBasicBlock &MBB, 649 MachineBasicBlock::iterator MI) const { 650 llvm_unreachable("Call Frame Pseudo Instructions do not exist on this " 651 "target!"); 652 } 653 654 655 /// saveScavengerRegister - Spill the register so it can be used by the 656 /// register scavenger. Return true if the register was spilled, false 657 /// otherwise. If this function does not spill the register, the scavenger 658 /// will instead spill it to the emergency spill slot. 659 /// 660 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 661 MachineBasicBlock::iterator I, 662 MachineBasicBlock::iterator &UseMI, 663 const TargetRegisterClass *RC, 664 unsigned Reg) const { 665 return false; 666 } 667 668 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 669 /// frame indices from instructions which may use them. The instruction 670 /// referenced by the iterator contains an MO_FrameIndex operand which must be 671 /// eliminated by this method. This method may modify or replace the 672 /// specified instruction, as long as it keeps the iterator pointing at the 673 /// finished product. SPAdj is the SP adjustment due to call frame setup 674 /// instruction. 675 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 676 int SPAdj, RegScavenger *RS=NULL) const = 0; 677 678 //===--------------------------------------------------------------------===// 679 /// Debug information queries. 680 681 /// getFrameRegister - This method should return the register used as a base 682 /// for values allocated in the current stack frame. 683 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 684 685 /// getCompactUnwindRegNum - This function maps the register to the number for 686 /// compact unwind encoding. Return -1 if the register isn't valid. 687 virtual int getCompactUnwindRegNum(unsigned, bool) const { 688 return -1; 689 } 690}; 691 692 693// This is useful when building IndexedMaps keyed on virtual registers 694struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 695 unsigned operator()(unsigned Reg) const { 696 return TargetRegisterInfo::virtReg2Index(Reg); 697 } 698}; 699 700/// PrintReg - Helper class for printing registers on a raw_ostream. 701/// Prints virtual and physical registers with or without a TRI instance. 702/// 703/// The format is: 704/// %noreg - NoRegister 705/// %vreg5 - a virtual register. 706/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 707/// %EAX - a physical register 708/// %physreg17 - a physical register when no TRI instance given. 709/// 710/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 711/// 712class PrintReg { 713 const TargetRegisterInfo *TRI; 714 unsigned Reg; 715 unsigned SubIdx; 716public: 717 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 718 : TRI(tri), Reg(reg), SubIdx(subidx) {} 719 void print(raw_ostream&) const; 720}; 721 722static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 723 PR.print(OS); 724 return OS; 725} 726 727} // End llvm namespace 728 729#endif 730