TargetRegisterInfo.h revision ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/ADT/DenseSet.h" 22#include <cassert> 23#include <functional> 24 25namespace llvm { 26 27class BitVector; 28class MachineFunction; 29class MachineMove; 30class RegScavenger; 31 32/// TargetRegisterDesc - This record contains all of the information known about 33/// a particular register. The AliasSet field (if not null) contains a pointer 34/// to a Zero terminated array of registers that this register aliases. This is 35/// needed for architectures like X86 which have AL alias AX alias EAX. 36/// Registers that this does not apply to simply should set this to null. 37/// The SubRegs field is a zero terminated array of registers that are 38/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 39/// The SuperRegs field is a zero terminated array of registers that are 40/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 41/// of AX. 42/// 43struct TargetRegisterDesc { 44 const char *AsmName; // Assembly language name for the register 45 const char *Name; // Printable name for the reg (for debugging) 46 const unsigned *AliasSet; // Register Alias Set, described above 47 const unsigned *SubRegs; // Sub-register set, described above 48 const unsigned *SuperRegs; // Super-register set, described above 49}; 50 51class TargetRegisterClass { 52public: 53 typedef const unsigned* iterator; 54 typedef const unsigned* const_iterator; 55 56 typedef const MVT* vt_iterator; 57 typedef const TargetRegisterClass* const * sc_iterator; 58private: 59 unsigned ID; 60 const char *Name; 61 const vt_iterator VTs; 62 const sc_iterator SubClasses; 63 const sc_iterator SuperClasses; 64 const sc_iterator SubRegClasses; 65 const sc_iterator SuperRegClasses; 66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 67 const int CopyCost; 68 const iterator RegsBegin, RegsEnd; 69 DenseSet<unsigned> RegSet; 70public: 71 TargetRegisterClass(unsigned id, 72 const char *name, 73 const MVT *vts, 74 const TargetRegisterClass * const *subcs, 75 const TargetRegisterClass * const *supcs, 76 const TargetRegisterClass * const *subregcs, 77 const TargetRegisterClass * const *superregcs, 78 unsigned RS, unsigned Al, int CC, 79 iterator RB, iterator RE) 80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 81 SubRegClasses(subregcs), SuperRegClasses(superregcs), 82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) { 83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) 84 RegSet.insert(*I); 85 } 86 virtual ~TargetRegisterClass() {} // Allow subclasses 87 88 /// getID() - Return the register class ID number. 89 /// 90 unsigned getID() const { return ID; } 91 92 /// getName() - Return the register class name for debugging. 93 /// 94 const char *getName() const { return Name; } 95 96 /// begin/end - Return all of the registers in this class. 97 /// 98 iterator begin() const { return RegsBegin; } 99 iterator end() const { return RegsEnd; } 100 101 /// getNumRegs - Return the number of registers in this class. 102 /// 103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 104 105 /// getRegister - Return the specified register in the class. 106 /// 107 unsigned getRegister(unsigned i) const { 108 assert(i < getNumRegs() && "Register number out of range!"); 109 return RegsBegin[i]; 110 } 111 112 /// contains - Return true if the specified register is included in this 113 /// register class. 114 bool contains(unsigned Reg) const { 115 return RegSet.count(Reg); 116 } 117 118 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 119 /// 120 bool hasType(MVT vt) const { 121 for(int i = 0; VTs[i] != MVT::Other; ++i) 122 if (VTs[i] == vt) 123 return true; 124 return false; 125 } 126 127 /// vt_begin / vt_end - Loop over all of the value types that can be 128 /// represented by values in this register class. 129 vt_iterator vt_begin() const { 130 return VTs; 131 } 132 133 vt_iterator vt_end() const { 134 vt_iterator I = VTs; 135 while (*I != MVT::Other) ++I; 136 return I; 137 } 138 139 /// subregclasses_begin / subregclasses_end - Loop over all of 140 /// the subreg register classes of this register class. 141 sc_iterator subregclasses_begin() const { 142 return SubRegClasses; 143 } 144 145 sc_iterator subregclasses_end() const { 146 sc_iterator I = SubRegClasses; 147 while (*I != NULL) ++I; 148 return I; 149 } 150 151 /// getSubRegisterRegClass - Return the register class of subregisters with 152 /// index SubIdx, or NULL if no such class exists. 153 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 154 assert(SubIdx>0 && "Invalid subregister index"); 155 for (unsigned s = 0; s != SubIdx-1; ++s) 156 if (!SubRegClasses[s]) 157 return NULL; 158 return SubRegClasses[SubIdx-1]; 159 } 160 161 /// superregclasses_begin / superregclasses_end - Loop over all of 162 /// the superreg register classes of this register class. 163 sc_iterator superregclasses_begin() const { 164 return SuperRegClasses; 165 } 166 167 sc_iterator superregclasses_end() const { 168 sc_iterator I = SuperRegClasses; 169 while (*I != NULL) ++I; 170 return I; 171 } 172 173 /// hasSubClass - return true if the the specified TargetRegisterClass 174 /// is a proper subset of this TargetRegisterClass. 175 bool hasSubClass(const TargetRegisterClass *cs) const { 176 for (int i = 0; SubClasses[i] != NULL; ++i) 177 if (SubClasses[i] == cs) 178 return true; 179 return false; 180 } 181 182 /// subclasses_begin / subclasses_end - Loop over all of the classes 183 /// that are proper subsets of this register class. 184 sc_iterator subclasses_begin() const { 185 return SubClasses; 186 } 187 188 sc_iterator subclasses_end() const { 189 sc_iterator I = SubClasses; 190 while (*I != NULL) ++I; 191 return I; 192 } 193 194 /// hasSuperClass - return true if the specified TargetRegisterClass is a 195 /// proper superset of this TargetRegisterClass. 196 bool hasSuperClass(const TargetRegisterClass *cs) const { 197 for (int i = 0; SuperClasses[i] != NULL; ++i) 198 if (SuperClasses[i] == cs) 199 return true; 200 return false; 201 } 202 203 /// superclasses_begin / superclasses_end - Loop over all of the classes 204 /// that are proper supersets of this register class. 205 sc_iterator superclasses_begin() const { 206 return SuperClasses; 207 } 208 209 sc_iterator superclasses_end() const { 210 sc_iterator I = SuperClasses; 211 while (*I != NULL) ++I; 212 return I; 213 } 214 215 /// isASubClass - return true if this TargetRegisterClass is a subset 216 /// class of at least one other TargetRegisterClass. 217 bool isASubClass() const { 218 return SuperClasses[0] != 0; 219 } 220 221 /// allocation_order_begin/end - These methods define a range of registers 222 /// which specify the registers in this class that are valid to register 223 /// allocate, and the preferred order to allocate them in. For example, 224 /// callee saved registers should be at the end of the list, because it is 225 /// cheaper to allocate caller saved registers. 226 /// 227 /// These methods take a MachineFunction argument, which can be used to tune 228 /// the allocatable registers based on the characteristics of the function. 229 /// One simple example is that the frame pointer register can be used if 230 /// frame-pointer-elimination is performed. 231 /// 232 /// By default, these methods return all registers in the class. 233 /// 234 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 235 return begin(); 236 } 237 virtual iterator allocation_order_end(const MachineFunction &MF) const { 238 return end(); 239 } 240 241 242 243 /// getSize - Return the size of the register in bytes, which is also the size 244 /// of a stack slot allocated to hold a spilled copy of this register. 245 unsigned getSize() const { return RegSize; } 246 247 /// getAlignment - Return the minimum required alignment for a register of 248 /// this class. 249 unsigned getAlignment() const { return Alignment; } 250 251 /// getCopyCost - Return the cost of copying a value between two registers in 252 /// this class. A negative number means the register class is very expensive 253 /// to copy e.g. status flag register classes. 254 int getCopyCost() const { return CopyCost; } 255}; 256 257/// getCommonSubClass - find the largest common subclass of A and B. Return NULL 258/// if there is no common subclass. 259const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, 260 const TargetRegisterClass *B); 261 262/// TargetRegisterInfo base class - We assume that the target defines a static 263/// array of TargetRegisterDesc objects that represent all of the machine 264/// registers that the target has. As such, we simply have to track a pointer 265/// to this array so that we can turn register number into a register 266/// descriptor. 267/// 268class TargetRegisterInfo { 269protected: 270 const unsigned* SubregHash; 271 const unsigned SubregHashSize; 272 const unsigned* SuperregHash; 273 const unsigned SuperregHashSize; 274 const unsigned* AliasesHash; 275 const unsigned AliasesHashSize; 276public: 277 typedef const TargetRegisterClass * const * regclass_iterator; 278private: 279 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 280 unsigned NumRegs; // Number of entries in the array 281 282 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 283 284 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 285protected: 286 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 287 regclass_iterator RegClassBegin, 288 regclass_iterator RegClassEnd, 289 int CallFrameSetupOpcode = -1, 290 int CallFrameDestroyOpcode = -1, 291 const unsigned* subregs = 0, 292 const unsigned subregsize = 0, 293 const unsigned* superregs = 0, 294 const unsigned superregsize = 0, 295 const unsigned* aliases = 0, 296 const unsigned aliasessize = 0); 297 virtual ~TargetRegisterInfo(); 298public: 299 300 enum { // Define some target independent constants 301 /// NoRegister - This physical register is not a real target register. It 302 /// is useful as a sentinal. 303 NoRegister = 0, 304 305 /// FirstVirtualRegister - This is the first register number that is 306 /// considered to be a 'virtual' register, which is part of the SSA 307 /// namespace. This must be the same for all targets, which means that each 308 /// target is limited to 1024 registers. 309 FirstVirtualRegister = 1024 310 }; 311 312 /// isPhysicalRegister - Return true if the specified register number is in 313 /// the physical register namespace. 314 static bool isPhysicalRegister(unsigned Reg) { 315 assert(Reg && "this is not a register!"); 316 return Reg < FirstVirtualRegister; 317 } 318 319 /// isVirtualRegister - Return true if the specified register number is in 320 /// the virtual register namespace. 321 static bool isVirtualRegister(unsigned Reg) { 322 assert(Reg && "this is not a register!"); 323 return Reg >= FirstVirtualRegister; 324 } 325 326 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 327 /// register of the given type. If type is MVT::Other, then just return any 328 /// register class the register belongs to. 329 virtual const TargetRegisterClass * 330 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const; 331 332 /// getAllocatableSet - Returns a bitset indexed by register number 333 /// indicating if a register is allocatable or not. If a register class is 334 /// specified, returns the subset for the class. 335 BitVector getAllocatableSet(MachineFunction &MF, 336 const TargetRegisterClass *RC = NULL) const; 337 338 const TargetRegisterDesc &operator[](unsigned RegNo) const { 339 assert(RegNo < NumRegs && 340 "Attempting to access record for invalid register number!"); 341 return Desc[RegNo]; 342 } 343 344 /// Provide a get method, equivalent to [], but more useful if we have a 345 /// pointer to this object. 346 /// 347 const TargetRegisterDesc &get(unsigned RegNo) const { 348 return operator[](RegNo); 349 } 350 351 /// getAliasSet - Return the set of registers aliased by the specified 352 /// register, or a null list of there are none. The list returned is zero 353 /// terminated. 354 /// 355 const unsigned *getAliasSet(unsigned RegNo) const { 356 return get(RegNo).AliasSet; 357 } 358 359 /// getSubRegisters - Return the list of registers that are sub-registers of 360 /// the specified register, or a null list of there are none. The list 361 /// returned is zero terminated and sorted according to super-sub register 362 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 363 /// 364 const unsigned *getSubRegisters(unsigned RegNo) const { 365 return get(RegNo).SubRegs; 366 } 367 368 /// getSuperRegisters - Return the list of registers that are super-registers 369 /// of the specified register, or a null list of there are none. The list 370 /// returned is zero terminated and sorted according to super-sub register 371 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 372 /// 373 const unsigned *getSuperRegisters(unsigned RegNo) const { 374 return get(RegNo).SuperRegs; 375 } 376 377 /// getAsmName - Return the symbolic target-specific name for the 378 /// specified physical register. 379 const char *getAsmName(unsigned RegNo) const { 380 return get(RegNo).AsmName; 381 } 382 383 /// getName - Return the human-readable symbolic target-specific name for the 384 /// specified physical register. 385 const char *getName(unsigned RegNo) const { 386 return get(RegNo).Name; 387 } 388 389 /// getNumRegs - Return the number of registers this target has (useful for 390 /// sizing arrays holding per register information) 391 unsigned getNumRegs() const { 392 return NumRegs; 393 } 394 395 /// areAliases - Returns true if the two registers alias each other, false 396 /// otherwise 397 bool areAliases(unsigned regA, unsigned regB) const { 398 size_t index = (regA + regB * 37) & (AliasesHashSize-1); 399 unsigned ProbeAmt = 0; 400 while (AliasesHash[index*2] != 0 && 401 AliasesHash[index*2+1] != 0) { 402 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) 403 return true; 404 405 index = (index + ProbeAmt) & (AliasesHashSize-1); 406 ProbeAmt += 2; 407 } 408 409 return false; 410 } 411 412 /// regsOverlap - Returns true if the two registers are equal or alias each 413 /// other. The registers may be virtual register. 414 bool regsOverlap(unsigned regA, unsigned regB) const { 415 if (regA == regB) 416 return true; 417 418 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 419 return false; 420 return areAliases(regA, regB); 421 } 422 423 /// isSubRegister - Returns true if regB is a sub-register of regA. 424 /// 425 bool isSubRegister(unsigned regA, unsigned regB) const { 426 // SubregHash is a simple quadratically probed hash table. 427 size_t index = (regA + regB * 37) & (SubregHashSize-1); 428 unsigned ProbeAmt = 2; 429 while (SubregHash[index*2] != 0 && 430 SubregHash[index*2+1] != 0) { 431 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 432 return true; 433 434 index = (index + ProbeAmt) & (SubregHashSize-1); 435 ProbeAmt += 2; 436 } 437 438 return false; 439 } 440 441 /// isSuperRegister - Returns true if regB is a super-register of regA. 442 /// 443 bool isSuperRegister(unsigned regA, unsigned regB) const { 444 // SuperregHash is a simple quadratically probed hash table. 445 size_t index = (regA + regB * 37) & (SuperregHashSize-1); 446 unsigned ProbeAmt = 2; 447 while (SuperregHash[index*2] != 0 && 448 SuperregHash[index*2+1] != 0) { 449 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB) 450 return true; 451 452 index = (index + ProbeAmt) & (SuperregHashSize-1); 453 ProbeAmt += 2; 454 } 455 456 return false; 457 } 458 459 /// getCalleeSavedRegs - Return a null-terminated list of all of the 460 /// callee saved registers on this target. The register should be in the 461 /// order of desired callee-save stack frame offset. The first register is 462 /// closed to the incoming stack pointer if stack grows down, and vice versa. 463 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 464 const = 0; 465 466 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 467 /// register classes to spill each callee saved register with. The order and 468 /// length of this list match the getCalleeSaveRegs() list. 469 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( 470 const MachineFunction *MF) const =0; 471 472 /// getReservedRegs - Returns a bitset indexed by physical register number 473 /// indicating if a register is a special register that has particular uses 474 /// and should be considered unavailable at all times, e.g. SP, RA. This is 475 /// used by register scavenger to determine what registers are free. 476 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 477 478 /// getSubReg - Returns the physical register number of sub-register "Index" 479 /// for physical register RegNo. Return zero if the sub-register does not 480 /// exist. 481 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 482 483 /// getMatchingSuperReg - Return a super-register of the specified register 484 /// Reg so its sub-register of index SubIdx is Reg. 485 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 486 const TargetRegisterClass *RC) const { 487 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 488 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 489 return SR; 490 return 0; 491 } 492 493 //===--------------------------------------------------------------------===// 494 // Register Class Information 495 // 496 497 /// Register class iterators 498 /// 499 regclass_iterator regclass_begin() const { return RegClassBegin; } 500 regclass_iterator regclass_end() const { return RegClassEnd; } 501 502 unsigned getNumRegClasses() const { 503 return (unsigned)(regclass_end()-regclass_begin()); 504 } 505 506 /// getRegClass - Returns the register class associated with the enumeration 507 /// value. See class TargetOperandInfo. 508 const TargetRegisterClass *getRegClass(unsigned i) const { 509 assert(i <= getNumRegClasses() && "Register Class ID out of range"); 510 return i ? RegClassBegin[i - 1] : NULL; 511 } 512 513 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 514 /// values. 515 virtual const TargetRegisterClass *getPointerRegClass() const { 516 assert(0 && "Target didn't implement getPointerRegClass!"); 517 return 0; // Must return a value in order to compile with VS 2005 518 } 519 520 /// getCrossCopyRegClass - Returns a legal register class to copy a register 521 /// in the specified class to or from. Returns NULL if it is possible to copy 522 /// between a two registers of the specified class. 523 virtual const TargetRegisterClass * 524 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 525 return NULL; 526 } 527 528 /// targetHandlesStackFrameRounding - Returns true if the target is 529 /// responsible for rounding up the stack frame (probably at emitPrologue 530 /// time). 531 virtual bool targetHandlesStackFrameRounding() const { 532 return false; 533 } 534 535 /// requiresRegisterScavenging - returns true if the target requires (and can 536 /// make use of) the register scavenger. 537 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 538 return false; 539 } 540 541 /// hasFP - Return true if the specified function should have a dedicated 542 /// frame pointer register. For most targets this is true only if the function 543 /// has variable sized allocas or if frame pointer elimination is disabled. 544 virtual bool hasFP(const MachineFunction &MF) const = 0; 545 546 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is 547 // not required, we reserve argument space for call sites in the function 548 // immediately on entry to the current function. This eliminates the need for 549 // add/sub sp brackets around call sites. Returns true if the call frame is 550 // included as part of the stack frame. 551 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 552 return !hasFP(MF); 553 } 554 555 // needsStackRealignment - true if storage within the function requires the 556 // stack pointer to be aligned more than the normal calling convention calls 557 // for. 558 virtual bool needsStackRealignment(const MachineFunction &MF) const { 559 return false; 560 } 561 562 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 563 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 564 /// targets use pseudo instructions in order to abstract away the difference 565 /// between operating with a frame pointer and operating without, through the 566 /// use of these two instructions. 567 /// 568 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 569 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 570 571 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 572 /// code insertion to eliminate call frame setup and destroy pseudo 573 /// instructions (but only if the Target is using them). It is responsible 574 /// for eliminating these instructions, replacing them with concrete 575 /// instructions. This method need only be implemented if using call frame 576 /// setup/destroy pseudo instructions. 577 /// 578 virtual void 579 eliminateCallFramePseudoInstr(MachineFunction &MF, 580 MachineBasicBlock &MBB, 581 MachineBasicBlock::iterator MI) const { 582 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 583 "eliminateCallFramePseudoInstr must be implemented if using" 584 " call frame setup/destroy pseudo instructions!"); 585 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 586 } 587 588 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 589 /// before PrologEpilogInserter scans the physical registers used to determine 590 /// what callee saved registers should be spilled. This method is optional. 591 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 592 RegScavenger *RS = NULL) const { 593 594 } 595 596 /// processFunctionBeforeFrameFinalized - This method is called immediately 597 /// before the specified functions frame layout (MF.getFrameInfo()) is 598 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 599 /// replaced with direct constants. This method is optional. 600 /// 601 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 602 } 603 604 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 605 /// frame indices from instructions which may use them. The instruction 606 /// referenced by the iterator contains an MO_FrameIndex operand which must be 607 /// eliminated by this method. This method may modify or replace the 608 /// specified instruction, as long as it keeps the iterator pointing the the 609 /// finished product. SPAdj is the SP adjustment due to call frame setup 610 /// instruction. 611 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 612 int SPAdj, RegScavenger *RS=NULL) const = 0; 613 614 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 615 /// the function. 616 virtual void emitPrologue(MachineFunction &MF) const = 0; 617 virtual void emitEpilogue(MachineFunction &MF, 618 MachineBasicBlock &MBB) const = 0; 619 620 //===--------------------------------------------------------------------===// 621 /// Debug information queries. 622 623 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 624 /// number. Returns -1 if there is no equivalent value. The second 625 /// parameter allows targets to use different numberings for EH info and 626 /// debugging info. 627 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 628 629 /// getFrameRegister - This method should return the register used as a base 630 /// for values allocated in the current stack frame. 631 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 632 633 /// getFrameIndexOffset - Returns the displacement from the frame register to 634 /// the stack frame of the specified index. 635 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; 636 637 /// getRARegister - This method should return the register where the return 638 /// address can be found. 639 virtual unsigned getRARegister() const = 0; 640 641 /// getInitialFrameState - Returns a list of machine moves that are assumed 642 /// on entry to all functions. Note that LabelID is ignored (assumed to be 643 /// the beginning of the function.) 644 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 645}; 646 647// This is useful when building IndexedMaps keyed on virtual registers 648struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 649 unsigned operator()(unsigned Reg) const { 650 return Reg - TargetRegisterInfo::FirstVirtualRegister; 651 } 652}; 653 654} // End llvm namespace 655 656#endif 657