TargetRegisterInfo.h revision ca1267c02b025cc719190b05f9e1a5d174a9caf7
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/ValueTypes.h" 22#include <cassert> 23#include <functional> 24 25namespace llvm { 26 27class BitVector; 28class MachineFunction; 29class MachineInstr; 30class MachineMove; 31class RegScavenger; 32class SDNode; 33class SelectionDAG; 34class TargetRegisterClass; 35class Type; 36 37/// TargetRegisterDesc - This record contains all of the information known about 38/// a particular register. The AliasSet field (if not null) contains a pointer 39/// to a Zero terminated array of registers that this register aliases. This is 40/// needed for architectures like X86 which have AL alias AX alias EAX. 41/// Registers that this does not apply to simply should set this to null. 42/// The SubRegs field is a zero terminated array of registers that are 43/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 44/// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate 45/// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH, 46/// AL which are immediate sub-registers of AX. The SuperRegs field is a zero 47/// terminated array of registers that are super-registers of the specific 48/// register, e.g. RAX, EAX, are super-registers of AX. 49/// 50struct TargetRegisterDesc { 51 const char *AsmName; // Assembly language name for the register 52 const char *Name; // Printable name for the reg (for debugging) 53 const unsigned *AliasSet; // Register Alias Set, described above 54 const unsigned *SubRegs; // Sub-register set, described above 55 const unsigned *ImmSubRegs; // Immediate sub-register set, described above 56 const unsigned *SuperRegs; // Super-register set, described above 57}; 58 59class TargetRegisterClass { 60public: 61 typedef const unsigned* iterator; 62 typedef const unsigned* const_iterator; 63 64 typedef const MVT::ValueType* vt_iterator; 65 typedef const TargetRegisterClass* const * sc_iterator; 66private: 67 unsigned ID; 68 bool isSubClass; 69 const vt_iterator VTs; 70 const sc_iterator SubClasses; 71 const sc_iterator SuperClasses; 72 const sc_iterator SubRegClasses; 73 const sc_iterator SuperRegClasses; 74 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 75 const int CopyCost; 76 const iterator RegsBegin, RegsEnd; 77public: 78 TargetRegisterClass(unsigned id, 79 const MVT::ValueType *vts, 80 const TargetRegisterClass * const *subcs, 81 const TargetRegisterClass * const *supcs, 82 const TargetRegisterClass * const *subregcs, 83 const TargetRegisterClass * const *superregcs, 84 unsigned RS, unsigned Al, int CC, 85 iterator RB, iterator RE) 86 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 87 SubRegClasses(subregcs), SuperRegClasses(superregcs), 88 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {} 89 virtual ~TargetRegisterClass() {} // Allow subclasses 90 91 /// getID() - Return the register class ID number. 92 /// 93 unsigned getID() const { return ID; } 94 95 /// begin/end - Return all of the registers in this class. 96 /// 97 iterator begin() const { return RegsBegin; } 98 iterator end() const { return RegsEnd; } 99 100 /// getNumRegs - Return the number of registers in this class. 101 /// 102 unsigned getNumRegs() const { return RegsEnd-RegsBegin; } 103 104 /// getRegister - Return the specified register in the class. 105 /// 106 unsigned getRegister(unsigned i) const { 107 assert(i < getNumRegs() && "Register number out of range!"); 108 return RegsBegin[i]; 109 } 110 111 /// contains - Return true if the specified register is included in this 112 /// register class. 113 bool contains(unsigned Reg) const { 114 for (iterator I = begin(), E = end(); I != E; ++I) 115 if (*I == Reg) return true; 116 return false; 117 } 118 119 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 120 /// 121 bool hasType(MVT::ValueType vt) const { 122 for(int i = 0; VTs[i] != MVT::Other; ++i) 123 if (VTs[i] == vt) 124 return true; 125 return false; 126 } 127 128 /// vt_begin / vt_end - Loop over all of the value types that can be 129 /// represented by values in this register class. 130 vt_iterator vt_begin() const { 131 return VTs; 132 } 133 134 vt_iterator vt_end() const { 135 vt_iterator I = VTs; 136 while (*I != MVT::Other) ++I; 137 return I; 138 } 139 140 /// hasSubClass - return true if the specified TargetRegisterClass is a 141 /// sub-register class of this TargetRegisterClass. 142 bool hasSubClass(const TargetRegisterClass *cs) const { 143 for (int i = 0; SubClasses[i] != NULL; ++i) 144 if (SubClasses[i] == cs) 145 return true; 146 return false; 147 } 148 149 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of 150 /// this register class. 151 sc_iterator subclasses_begin() const { 152 return SubClasses; 153 } 154 155 sc_iterator subclasses_end() const { 156 sc_iterator I = SubClasses; 157 while (*I != NULL) ++I; 158 return I; 159 } 160 161 /// hasSuperClass - return true if the specified TargetRegisterClass is a 162 /// super-register class of this TargetRegisterClass. 163 bool hasSuperClass(const TargetRegisterClass *cs) const { 164 for (int i = 0; SuperClasses[i] != NULL; ++i) 165 if (SuperClasses[i] == cs) 166 return true; 167 return false; 168 } 169 170 /// superclasses_begin / superclasses_end - Loop over all of the super-classes 171 /// of this register class. 172 sc_iterator superclasses_begin() const { 173 return SuperClasses; 174 } 175 176 sc_iterator superclasses_end() const { 177 sc_iterator I = SuperClasses; 178 while (*I != NULL) ++I; 179 return I; 180 } 181 182 /// hasSubRegClass - return true if the specified TargetRegisterClass is a 183 /// class of a sub-register class for this TargetRegisterClass. 184 bool hasSubRegClass(const TargetRegisterClass *cs) const { 185 for (int i = 0; SubRegClasses[i] != NULL; ++i) 186 if (SubRegClasses[i] == cs) 187 return true; 188 return false; 189 } 190 191 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a 192 /// class of a sub-register class for this TargetRegisterClass. 193 bool hasClassForSubReg(unsigned SubReg) const { 194 --SubReg; 195 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 196 if (i == SubReg) 197 return true; 198 return false; 199 } 200 201 /// getClassForSubReg - return theTargetRegisterClass for the sub-register 202 /// at idx for this TargetRegisterClass. 203 sc_iterator getClassForSubReg(unsigned SubReg) const { 204 --SubReg; 205 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) 206 if (i == SubReg) 207 return &SubRegClasses[i]; 208 assert(0 && "Invalid subregister index for register class"); 209 return NULL; 210 } 211 212 /// subregclasses_begin / subregclasses_end - Loop over all of 213 /// the subregister classes of this register class. 214 sc_iterator subregclasses_begin() const { 215 return SubRegClasses; 216 } 217 218 sc_iterator subregclasses_end() const { 219 sc_iterator I = SubRegClasses; 220 while (*I != NULL) ++I; 221 return I; 222 } 223 224 /// superregclasses_begin / superregclasses_end - Loop over all of 225 /// the superregister classes of this register class. 226 sc_iterator superregclasses_begin() const { 227 return SuperRegClasses; 228 } 229 230 sc_iterator superregclasses_end() const { 231 sc_iterator I = SuperRegClasses; 232 while (*I != NULL) ++I; 233 return I; 234 } 235 236 /// allocation_order_begin/end - These methods define a range of registers 237 /// which specify the registers in this class that are valid to register 238 /// allocate, and the preferred order to allocate them in. For example, 239 /// callee saved registers should be at the end of the list, because it is 240 /// cheaper to allocate caller saved registers. 241 /// 242 /// These methods take a MachineFunction argument, which can be used to tune 243 /// the allocatable registers based on the characteristics of the function. 244 /// One simple example is that the frame pointer register can be used if 245 /// frame-pointer-elimination is performed. 246 /// 247 /// By default, these methods return all registers in the class. 248 /// 249 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 250 return begin(); 251 } 252 virtual iterator allocation_order_end(const MachineFunction &MF) const { 253 return end(); 254 } 255 256 257 258 /// getSize - Return the size of the register in bytes, which is also the size 259 /// of a stack slot allocated to hold a spilled copy of this register. 260 unsigned getSize() const { return RegSize; } 261 262 /// getAlignment - Return the minimum required alignment for a register of 263 /// this class. 264 unsigned getAlignment() const { return Alignment; } 265 266 /// getCopyCost - Return the cost of copying a value between two registers in 267 /// this class. 268 int getCopyCost() const { return CopyCost; } 269}; 270 271 272/// TargetRegisterInfo base class - We assume that the target defines a static 273/// array of TargetRegisterDesc objects that represent all of the machine 274/// registers that the target has. As such, we simply have to track a pointer 275/// to this array so that we can turn register number into a register 276/// descriptor. 277/// 278class TargetRegisterInfo { 279public: 280 typedef const TargetRegisterClass * const * regclass_iterator; 281private: 282 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 283 unsigned NumRegs; // Number of entries in the array 284 285 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 286 287 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 288protected: 289 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 290 regclass_iterator RegClassBegin, 291 regclass_iterator RegClassEnd, 292 int CallFrameSetupOpcode = -1, 293 int CallFrameDestroyOpcode = -1); 294 virtual ~TargetRegisterInfo(); 295public: 296 297 enum { // Define some target independent constants 298 /// NoRegister - This physical register is not a real target register. It 299 /// is useful as a sentinal. 300 NoRegister = 0, 301 302 /// FirstVirtualRegister - This is the first register number that is 303 /// considered to be a 'virtual' register, which is part of the SSA 304 /// namespace. This must be the same for all targets, which means that each 305 /// target is limited to 1024 registers. 306 FirstVirtualRegister = 1024 307 }; 308 309 /// isPhysicalRegister - Return true if the specified register number is in 310 /// the physical register namespace. 311 static bool isPhysicalRegister(unsigned Reg) { 312 assert(Reg && "this is not a register!"); 313 return Reg < FirstVirtualRegister; 314 } 315 316 /// isVirtualRegister - Return true if the specified register number is in 317 /// the virtual register namespace. 318 static bool isVirtualRegister(unsigned Reg) { 319 assert(Reg && "this is not a register!"); 320 return Reg >= FirstVirtualRegister; 321 } 322 323 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 324 /// register of the given type. If type is MVT::Other, then just return any 325 /// register class the register belongs to. 326 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg, 327 MVT::ValueType VT = MVT::Other) const; 328 329 /// getAllocatableSet - Returns a bitset indexed by register number 330 /// indicating if a register is allocatable or not. If a register class is 331 /// specified, returns the subset for the class. 332 BitVector getAllocatableSet(MachineFunction &MF, 333 const TargetRegisterClass *RC = NULL) const; 334 335 const TargetRegisterDesc &operator[](unsigned RegNo) const { 336 assert(RegNo < NumRegs && 337 "Attempting to access record for invalid register number!"); 338 return Desc[RegNo]; 339 } 340 341 /// Provide a get method, equivalent to [], but more useful if we have a 342 /// pointer to this object. 343 /// 344 const TargetRegisterDesc &get(unsigned RegNo) const { 345 return operator[](RegNo); 346 } 347 348 /// getAliasSet - Return the set of registers aliased by the specified 349 /// register, or a null list of there are none. The list returned is zero 350 /// terminated. 351 /// 352 const unsigned *getAliasSet(unsigned RegNo) const { 353 return get(RegNo).AliasSet; 354 } 355 356 /// getSubRegisters - Return the set of registers that are sub-registers of 357 /// the specified register, or a null list of there are none. The list 358 /// returned is zero terminated. 359 /// 360 const unsigned *getSubRegisters(unsigned RegNo) const { 361 return get(RegNo).SubRegs; 362 } 363 364 /// getImmediateSubRegisters - Return the set of registers that are immediate 365 /// sub-registers of the specified register, or a null list of there are none. 366 /// The list returned is zero terminated. 367 /// 368 const unsigned *getImmediateSubRegisters(unsigned RegNo) const { 369 return get(RegNo).ImmSubRegs; 370 } 371 372 /// getSuperRegisters - Return the set of registers that are super-registers 373 /// of the specified register, or a null list of there are none. The list 374 /// returned is zero terminated. 375 /// 376 const unsigned *getSuperRegisters(unsigned RegNo) const { 377 return get(RegNo).SuperRegs; 378 } 379 380 /// getAsmName - Return the symbolic target-specific name for the 381 /// specified physical register. 382 const char *getAsmName(unsigned RegNo) const { 383 return get(RegNo).AsmName; 384 } 385 386 /// getName - Return the human-readable symbolic target-specific name for the 387 /// specified physical register. 388 const char *getName(unsigned RegNo) const { 389 return get(RegNo).Name; 390 } 391 392 /// getNumRegs - Return the number of registers this target has (useful for 393 /// sizing arrays holding per register information) 394 unsigned getNumRegs() const { 395 return NumRegs; 396 } 397 398 /// areAliases - Returns true if the two registers alias each other, false 399 /// otherwise 400 bool areAliases(unsigned regA, unsigned regB) const { 401 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias) 402 if (*Alias == regB) return true; 403 return false; 404 } 405 406 /// regsOverlap - Returns true if the two registers are equal or alias each 407 /// other. The registers may be virtual register. 408 bool regsOverlap(unsigned regA, unsigned regB) const { 409 if (regA == regB) 410 return true; 411 412 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 413 return false; 414 return areAliases(regA, regB); 415 } 416 417 /// isSubRegister - Returns true if regB is a sub-register of regA. 418 /// 419 bool isSubRegister(unsigned regA, unsigned regB) const { 420 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR) 421 if (*SR == regB) return true; 422 return false; 423 } 424 425 /// isSuperRegister - Returns true if regB is a super-register of regA. 426 /// 427 bool isSuperRegister(unsigned regA, unsigned regB) const { 428 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR) 429 if (*SR == regB) return true; 430 return false; 431 } 432 433 /// getCalleeSavedRegs - Return a null-terminated list of all of the 434 /// callee saved registers on this target. The register should be in the 435 /// order of desired callee-save stack frame offset. The first register is 436 /// closed to the incoming stack pointer if stack grows down, and vice versa. 437 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 438 const = 0; 439 440 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 441 /// register classes to spill each callee saved register with. The order and 442 /// length of this list match the getCalleeSaveRegs() list. 443 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( 444 const MachineFunction *MF) const =0; 445 446 /// getReservedRegs - Returns a bitset indexed by physical register number 447 /// indicating if a register is a special register that has particular uses 448 /// and should be considered unavailable at all times, e.g. SP, RA. This is 449 /// used by register scavenger to determine what registers are free. 450 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 451 452 /// getSubReg - Returns the physical register number of sub-register "Index" 453 /// for physical register RegNo. 454 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 455 456 //===--------------------------------------------------------------------===// 457 // Register Class Information 458 // 459 460 /// Register class iterators 461 /// 462 regclass_iterator regclass_begin() const { return RegClassBegin; } 463 regclass_iterator regclass_end() const { return RegClassEnd; } 464 465 unsigned getNumRegClasses() const { 466 return regclass_end()-regclass_begin(); 467 } 468 469 /// getRegClass - Returns the register class associated with the enumeration 470 /// value. See class TargetOperandInfo. 471 const TargetRegisterClass *getRegClass(unsigned i) const { 472 assert(i <= getNumRegClasses() && "Register Class ID out of range"); 473 return i ? RegClassBegin[i - 1] : NULL; 474 } 475 476 //===--------------------------------------------------------------------===// 477 // Interfaces used by the register allocator and stack frame 478 // manipulation passes to move data around between registers, 479 // immediates and memory. FIXME: Move these to TargetInstrInfo.h. 480 // 481 482 /// getCrossCopyRegClass - Returns a legal register class to copy a register 483 /// in the specified class to or from. Returns NULL if it is possible to copy 484 /// between a two registers of the specified class. 485 virtual const TargetRegisterClass * 486 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 487 return NULL; 488 } 489 490 /// targetHandlesStackFrameRounding - Returns true if the target is 491 /// responsible for rounding up the stack frame (probably at emitPrologue 492 /// time). 493 virtual bool targetHandlesStackFrameRounding() const { 494 return false; 495 } 496 497 /// requiresRegisterScavenging - returns true if the target requires (and can 498 /// make use of) the register scavenger. 499 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 500 return false; 501 } 502 503 /// hasFP - Return true if the specified function should have a dedicated 504 /// frame pointer register. For most targets this is true only if the function 505 /// has variable sized allocas or if frame pointer elimination is disabled. 506 virtual bool hasFP(const MachineFunction &MF) const = 0; 507 508 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is 509 // not required, we reserve argument space for call sites in the function 510 // immediately on entry to the current function. This eliminates the need for 511 // add/sub sp brackets around call sites. Returns true if the call frame is 512 // included as part of the stack frame. 513 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 514 return !hasFP(MF); 515 } 516 517 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 518 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 519 /// targets use pseudo instructions in order to abstract away the difference 520 /// between operating with a frame pointer and operating without, through the 521 /// use of these two instructions. 522 /// 523 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 524 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 525 526 527 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 528 /// code insertion to eliminate call frame setup and destroy pseudo 529 /// instructions (but only if the Target is using them). It is responsible 530 /// for eliminating these instructions, replacing them with concrete 531 /// instructions. This method need only be implemented if using call frame 532 /// setup/destroy pseudo instructions. 533 /// 534 virtual void 535 eliminateCallFramePseudoInstr(MachineFunction &MF, 536 MachineBasicBlock &MBB, 537 MachineBasicBlock::iterator MI) const { 538 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 539 "eliminateCallFramePseudoInstr must be implemented if using" 540 " call frame setup/destroy pseudo instructions!"); 541 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 542 } 543 544 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 545 /// before PrologEpilogInserter scans the physical registers used to determine 546 /// what callee saved registers should be spilled. This method is optional. 547 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 548 RegScavenger *RS = NULL) const { 549 550 } 551 552 /// processFunctionBeforeFrameFinalized - This method is called immediately 553 /// before the specified functions frame layout (MF.getFrameInfo()) is 554 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 555 /// replaced with direct constants. This method is optional. 556 /// 557 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 558 } 559 560 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 561 /// frame indices from instructions which may use them. The instruction 562 /// referenced by the iterator contains an MO_FrameIndex operand which must be 563 /// eliminated by this method. This method may modify or replace the 564 /// specified instruction, as long as it keeps the iterator pointing the the 565 /// finished product. SPAdj is the SP adjustment due to call frame setup 566 /// instruction. The return value is the number of instructions added to 567 /// (negative if removed from) the basic block. 568 /// 569 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 570 int SPAdj, RegScavenger *RS=NULL) const = 0; 571 572 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 573 /// the function. The return value is the number of instructions 574 /// added to (negative if removed from) the basic block (entry for prologue). 575 /// 576 virtual void emitPrologue(MachineFunction &MF) const = 0; 577 virtual void emitEpilogue(MachineFunction &MF, 578 MachineBasicBlock &MBB) const = 0; 579 580 //===--------------------------------------------------------------------===// 581 /// Debug information queries. 582 583 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 584 /// number. Returns -1 if there is no equivalent value. The second 585 /// parameter allows targets to use different numberings for EH info and 586 /// deubgging info. 587 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 588 589 /// getFrameRegister - This method should return the register used as a base 590 /// for values allocated in the current stack frame. 591 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 592 593 /// getFrameIndexOffset - Returns the displacement from the frame register to 594 /// the stack frame of the specified index. 595 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; 596 597 /// getRARegister - This method should return the register where the return 598 /// address can be found. 599 virtual unsigned getRARegister() const = 0; 600 601 /// getInitialFrameState - Returns a list of machine moves that are assumed 602 /// on entry to all functions. Note that LabelID is ignored (assumed to be 603 /// the beginning of the function.) 604 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 605}; 606 607// This is useful when building IndexedMaps keyed on virtual registers 608struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 609 unsigned operator()(unsigned Reg) const { 610 return Reg - TargetRegisterInfo::FirstVirtualRegister; 611 } 612}; 613 614} // End llvm namespace 615 616#endif 617