TargetRegisterInfo.h revision d31f972bd33de85071c716f69bf5c6d735f730f2
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/ADT/DenseSet.h" 22#include <cassert> 23#include <functional> 24 25namespace llvm { 26 27class BitVector; 28class MachineFunction; 29class MachineMove; 30class RegScavenger; 31template<class T> class SmallVectorImpl; 32 33/// TargetRegisterDesc - This record contains all of the information known about 34/// a particular register. The AliasSet field (if not null) contains a pointer 35/// to a Zero terminated array of registers that this register aliases. This is 36/// needed for architectures like X86 which have AL alias AX alias EAX. 37/// Registers that this does not apply to simply should set this to null. 38/// The SubRegs field is a zero terminated array of registers that are 39/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 40/// The SuperRegs field is a zero terminated array of registers that are 41/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 42/// of AX. 43/// 44struct TargetRegisterDesc { 45 const char *Name; // Printable name for the reg (for debugging) 46 const unsigned *AliasSet; // Register Alias Set, described above 47 const unsigned *SubRegs; // Sub-register set, described above 48 const unsigned *SuperRegs; // Super-register set, described above 49}; 50 51class TargetRegisterClass { 52public: 53 typedef const unsigned* iterator; 54 typedef const unsigned* const_iterator; 55 56 typedef const EVT* vt_iterator; 57 typedef const TargetRegisterClass* const * sc_iterator; 58private: 59 unsigned ID; 60 const char *Name; 61 const vt_iterator VTs; 62 const sc_iterator SubClasses; 63 const sc_iterator SuperClasses; 64 const sc_iterator SubRegClasses; 65 const sc_iterator SuperRegClasses; 66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 67 const int CopyCost; 68 const iterator RegsBegin, RegsEnd; 69 DenseSet<unsigned> RegSet; 70public: 71 TargetRegisterClass(unsigned id, 72 const char *name, 73 const EVT *vts, 74 const TargetRegisterClass * const *subcs, 75 const TargetRegisterClass * const *supcs, 76 const TargetRegisterClass * const *subregcs, 77 const TargetRegisterClass * const *superregcs, 78 unsigned RS, unsigned Al, int CC, 79 iterator RB, iterator RE) 80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 81 SubRegClasses(subregcs), SuperRegClasses(superregcs), 82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) { 83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) 84 RegSet.insert(*I); 85 } 86 virtual ~TargetRegisterClass() {} // Allow subclasses 87 88 /// getID() - Return the register class ID number. 89 /// 90 unsigned getID() const { return ID; } 91 92 /// getName() - Return the register class name for debugging. 93 /// 94 const char *getName() const { return Name; } 95 96 /// begin/end - Return all of the registers in this class. 97 /// 98 iterator begin() const { return RegsBegin; } 99 iterator end() const { return RegsEnd; } 100 101 /// getNumRegs - Return the number of registers in this class. 102 /// 103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 104 105 /// getRegister - Return the specified register in the class. 106 /// 107 unsigned getRegister(unsigned i) const { 108 assert(i < getNumRegs() && "Register number out of range!"); 109 return RegsBegin[i]; 110 } 111 112 /// contains - Return true if the specified register is included in this 113 /// register class. This does not include virtual registers. 114 bool contains(unsigned Reg) const { 115 return RegSet.count(Reg); 116 } 117 118 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 119 /// 120 bool hasType(EVT vt) const { 121 for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i) 122 if (VTs[i] == vt) 123 return true; 124 return false; 125 } 126 127 /// vt_begin / vt_end - Loop over all of the value types that can be 128 /// represented by values in this register class. 129 vt_iterator vt_begin() const { 130 return VTs; 131 } 132 133 vt_iterator vt_end() const { 134 vt_iterator I = VTs; 135 while (I->getSimpleVT().SimpleTy != MVT::Other) ++I; 136 return I; 137 } 138 139 /// subregclasses_begin / subregclasses_end - Loop over all of 140 /// the subreg register classes of this register class. 141 sc_iterator subregclasses_begin() const { 142 return SubRegClasses; 143 } 144 145 sc_iterator subregclasses_end() const { 146 sc_iterator I = SubRegClasses; 147 while (*I != NULL) ++I; 148 return I; 149 } 150 151 /// getSubRegisterRegClass - Return the register class of subregisters with 152 /// index SubIdx, or NULL if no such class exists. 153 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 154 assert(SubIdx>0 && "Invalid subregister index"); 155 return SubRegClasses[SubIdx-1]; 156 } 157 158 /// superregclasses_begin / superregclasses_end - Loop over all of 159 /// the superreg register classes of this register class. 160 sc_iterator superregclasses_begin() const { 161 return SuperRegClasses; 162 } 163 164 sc_iterator superregclasses_end() const { 165 sc_iterator I = SuperRegClasses; 166 while (*I != NULL) ++I; 167 return I; 168 } 169 170 /// hasSubClass - return true if the specified TargetRegisterClass 171 /// is a proper subset of this TargetRegisterClass. 172 bool hasSubClass(const TargetRegisterClass *cs) const { 173 for (int i = 0; SubClasses[i] != NULL; ++i) 174 if (SubClasses[i] == cs) 175 return true; 176 return false; 177 } 178 179 /// subclasses_begin / subclasses_end - Loop over all of the classes 180 /// that are proper subsets of this register class. 181 sc_iterator subclasses_begin() const { 182 return SubClasses; 183 } 184 185 sc_iterator subclasses_end() const { 186 sc_iterator I = SubClasses; 187 while (*I != NULL) ++I; 188 return I; 189 } 190 191 /// hasSuperClass - return true if the specified TargetRegisterClass is a 192 /// proper superset of this TargetRegisterClass. 193 bool hasSuperClass(const TargetRegisterClass *cs) const { 194 for (int i = 0; SuperClasses[i] != NULL; ++i) 195 if (SuperClasses[i] == cs) 196 return true; 197 return false; 198 } 199 200 /// superclasses_begin / superclasses_end - Loop over all of the classes 201 /// that are proper supersets of this register class. 202 sc_iterator superclasses_begin() const { 203 return SuperClasses; 204 } 205 206 sc_iterator superclasses_end() const { 207 sc_iterator I = SuperClasses; 208 while (*I != NULL) ++I; 209 return I; 210 } 211 212 /// isASubClass - return true if this TargetRegisterClass is a subset 213 /// class of at least one other TargetRegisterClass. 214 bool isASubClass() const { 215 return SuperClasses[0] != 0; 216 } 217 218 /// allocation_order_begin/end - These methods define a range of registers 219 /// which specify the registers in this class that are valid to register 220 /// allocate, and the preferred order to allocate them in. For example, 221 /// callee saved registers should be at the end of the list, because it is 222 /// cheaper to allocate caller saved registers. 223 /// 224 /// These methods take a MachineFunction argument, which can be used to tune 225 /// the allocatable registers based on the characteristics of the function. 226 /// One simple example is that the frame pointer register can be used if 227 /// frame-pointer-elimination is performed. 228 /// 229 /// By default, these methods return all registers in the class. 230 /// 231 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 232 return begin(); 233 } 234 virtual iterator allocation_order_end(const MachineFunction &MF) const { 235 return end(); 236 } 237 238 /// getSize - Return the size of the register in bytes, which is also the size 239 /// of a stack slot allocated to hold a spilled copy of this register. 240 unsigned getSize() const { return RegSize; } 241 242 /// getAlignment - Return the minimum required alignment for a register of 243 /// this class. 244 unsigned getAlignment() const { return Alignment; } 245 246 /// getCopyCost - Return the cost of copying a value between two registers in 247 /// this class. A negative number means the register class is very expensive 248 /// to copy e.g. status flag register classes. 249 int getCopyCost() const { return CopyCost; } 250}; 251 252 253/// TargetRegisterInfo base class - We assume that the target defines a static 254/// array of TargetRegisterDesc objects that represent all of the machine 255/// registers that the target has. As such, we simply have to track a pointer 256/// to this array so that we can turn register number into a register 257/// descriptor. 258/// 259class TargetRegisterInfo { 260protected: 261 const unsigned* SubregHash; 262 const unsigned SubregHashSize; 263 const unsigned* AliasesHash; 264 const unsigned AliasesHashSize; 265public: 266 typedef const TargetRegisterClass * const * regclass_iterator; 267private: 268 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 269 const char *const *SubRegIndexNames; // Names of subreg indexes. 270 unsigned NumRegs; // Number of entries in the array 271 272 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 273 274 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 275 276protected: 277 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 278 regclass_iterator RegClassBegin, 279 regclass_iterator RegClassEnd, 280 const char *const *subregindexnames, 281 int CallFrameSetupOpcode = -1, 282 int CallFrameDestroyOpcode = -1, 283 const unsigned* subregs = 0, 284 const unsigned subregsize = 0, 285 const unsigned* aliases = 0, 286 const unsigned aliasessize = 0); 287 virtual ~TargetRegisterInfo(); 288public: 289 290 enum { // Define some target independent constants 291 /// NoRegister - This physical register is not a real target register. It 292 /// is useful as a sentinal. 293 NoRegister = 0, 294 295 /// FirstVirtualRegister - This is the first register number that is 296 /// considered to be a 'virtual' register, which is part of the SSA 297 /// namespace. This must be the same for all targets, which means that each 298 /// target is limited to this fixed number of registers. 299 FirstVirtualRegister = 1024 300 }; 301 302 /// isPhysicalRegister - Return true if the specified register number is in 303 /// the physical register namespace. 304 static bool isPhysicalRegister(unsigned Reg) { 305 assert(Reg && "this is not a register!"); 306 return Reg < FirstVirtualRegister; 307 } 308 309 /// isVirtualRegister - Return true if the specified register number is in 310 /// the virtual register namespace. 311 static bool isVirtualRegister(unsigned Reg) { 312 assert(Reg && "this is not a register!"); 313 return Reg >= FirstVirtualRegister; 314 } 315 316 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 317 /// register of the given type. If type is EVT::Other, then just return any 318 /// register class the register belongs to. 319 virtual const TargetRegisterClass * 320 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const; 321 322 /// getMinimalPhysRegClass - Returns the Register Class of a physical 323 /// register of the given type. 324 const TargetRegisterClass * 325 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 326 327 /// getAllocatableSet - Returns a bitset indexed by register number 328 /// indicating if a register is allocatable or not. If a register class is 329 /// specified, returns the subset for the class. 330 BitVector getAllocatableSet(const MachineFunction &MF, 331 const TargetRegisterClass *RC = NULL) const; 332 333 const TargetRegisterDesc &operator[](unsigned RegNo) const { 334 assert(RegNo < NumRegs && 335 "Attempting to access record for invalid register number!"); 336 return Desc[RegNo]; 337 } 338 339 /// Provide a get method, equivalent to [], but more useful if we have a 340 /// pointer to this object. 341 /// 342 const TargetRegisterDesc &get(unsigned RegNo) const { 343 return operator[](RegNo); 344 } 345 346 /// getAliasSet - Return the set of registers aliased by the specified 347 /// register, or a null list of there are none. The list returned is zero 348 /// terminated. 349 /// 350 const unsigned *getAliasSet(unsigned RegNo) const { 351 return get(RegNo).AliasSet; 352 } 353 354 /// getSubRegisters - Return the list of registers that are sub-registers of 355 /// the specified register, or a null list of there are none. The list 356 /// returned is zero terminated and sorted according to super-sub register 357 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 358 /// 359 const unsigned *getSubRegisters(unsigned RegNo) const { 360 return get(RegNo).SubRegs; 361 } 362 363 /// getSuperRegisters - Return the list of registers that are super-registers 364 /// of the specified register, or a null list of there are none. The list 365 /// returned is zero terminated and sorted according to super-sub register 366 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 367 /// 368 const unsigned *getSuperRegisters(unsigned RegNo) const { 369 return get(RegNo).SuperRegs; 370 } 371 372 /// getName - Return the human-readable symbolic target-specific name for the 373 /// specified physical register. 374 const char *getName(unsigned RegNo) const { 375 return get(RegNo).Name; 376 } 377 378 /// getNumRegs - Return the number of registers this target has (useful for 379 /// sizing arrays holding per register information) 380 unsigned getNumRegs() const { 381 return NumRegs; 382 } 383 384 /// getSubRegIndexName - Return the human-readable symbolic target-specific 385 /// name for the specified SubRegIndex. 386 const char *getSubRegIndexName(unsigned SubIdx) const { 387 assert(SubIdx && "This is not a subregister index"); 388 return SubRegIndexNames[SubIdx-1]; 389 } 390 391 /// regsOverlap - Returns true if the two registers are equal or alias each 392 /// other. The registers may be virtual register. 393 bool regsOverlap(unsigned regA, unsigned regB) const { 394 if (regA == regB) 395 return true; 396 397 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 398 return false; 399 400 // regA and regB are distinct physical registers. Do they alias? 401 size_t index = (regA + regB * 37) & (AliasesHashSize-1); 402 unsigned ProbeAmt = 0; 403 while (AliasesHash[index*2] != 0 && 404 AliasesHash[index*2+1] != 0) { 405 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) 406 return true; 407 408 index = (index + ProbeAmt) & (AliasesHashSize-1); 409 ProbeAmt += 2; 410 } 411 412 return false; 413 } 414 415 /// isSubRegister - Returns true if regB is a sub-register of regA. 416 /// 417 bool isSubRegister(unsigned regA, unsigned regB) const { 418 // SubregHash is a simple quadratically probed hash table. 419 size_t index = (regA + regB * 37) & (SubregHashSize-1); 420 unsigned ProbeAmt = 2; 421 while (SubregHash[index*2] != 0 && 422 SubregHash[index*2+1] != 0) { 423 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 424 return true; 425 426 index = (index + ProbeAmt) & (SubregHashSize-1); 427 ProbeAmt += 2; 428 } 429 430 return false; 431 } 432 433 /// isSuperRegister - Returns true if regB is a super-register of regA. 434 /// 435 bool isSuperRegister(unsigned regA, unsigned regB) const { 436 return isSubRegister(regB, regA); 437 } 438 439 /// getCalleeSavedRegs - Return a null-terminated list of all of the 440 /// callee saved registers on this target. The register should be in the 441 /// order of desired callee-save stack frame offset. The first register is 442 /// closed to the incoming stack pointer if stack grows down, and vice versa. 443 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 444 const = 0; 445 446 447 /// getReservedRegs - Returns a bitset indexed by physical register number 448 /// indicating if a register is a special register that has particular uses 449 /// and should be considered unavailable at all times, e.g. SP, RA. This is 450 /// used by register scavenger to determine what registers are free. 451 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 452 453 /// getSubReg - Returns the physical register number of sub-register "Index" 454 /// for physical register RegNo. Return zero if the sub-register does not 455 /// exist. 456 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 457 458 /// getSubRegIndex - For a given register pair, return the sub-register index 459 /// if the second register is a sub-register of the first. Return zero 460 /// otherwise. 461 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 462 463 /// getMatchingSuperReg - Return a super-register of the specified register 464 /// Reg so its sub-register of index SubIdx is Reg. 465 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 466 const TargetRegisterClass *RC) const { 467 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 468 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 469 return SR; 470 return 0; 471 } 472 473 /// canCombineSubRegIndices - Given a register class and a list of 474 /// subregister indices, return true if it's possible to combine the 475 /// subregister indices into one that corresponds to a larger 476 /// subregister. Return the new subregister index by reference. Note the 477 /// new index may be zero if the given subregisters can be combined to 478 /// form the whole register. 479 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 480 SmallVectorImpl<unsigned> &SubIndices, 481 unsigned &NewSubIdx) const { 482 return 0; 483 } 484 485 /// getMatchingSuperRegClass - Return a subclass of the specified register 486 /// class A so that each register in it has a sub-register of the 487 /// specified sub-register index which is in the specified register class B. 488 virtual const TargetRegisterClass * 489 getMatchingSuperRegClass(const TargetRegisterClass *A, 490 const TargetRegisterClass *B, unsigned Idx) const { 491 return 0; 492 } 493 494 /// composeSubRegIndices - Return the subregister index you get from composing 495 /// two subregister indices. 496 /// 497 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 498 /// returns c. Note that composeSubRegIndices does not tell you about illegal 499 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 500 /// b, composeSubRegIndices doesn't tell you. 501 /// 502 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 503 /// ssub_0:S0 - ssub_3:S3 subregs. 504 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 505 /// 506 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 507 // This default implementation is correct for most targets. 508 return b; 509 } 510 511 //===--------------------------------------------------------------------===// 512 // Register Class Information 513 // 514 515 /// Register class iterators 516 /// 517 regclass_iterator regclass_begin() const { return RegClassBegin; } 518 regclass_iterator regclass_end() const { return RegClassEnd; } 519 520 unsigned getNumRegClasses() const { 521 return (unsigned)(regclass_end()-regclass_begin()); 522 } 523 524 /// getRegClass - Returns the register class associated with the enumeration 525 /// value. See class TargetOperandInfo. 526 const TargetRegisterClass *getRegClass(unsigned i) const { 527 assert(i < getNumRegClasses() && "Register Class ID out of range"); 528 return RegClassBegin[i]; 529 } 530 531 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 532 /// values. If a target supports multiple different pointer register classes, 533 /// kind specifies which one is indicated. 534 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 535 assert(0 && "Target didn't implement getPointerRegClass!"); 536 return 0; // Must return a value in order to compile with VS 2005 537 } 538 539 /// getCrossCopyRegClass - Returns a legal register class to copy a register 540 /// in the specified class to or from. Returns NULL if it is possible to copy 541 /// between a two registers of the specified class. 542 virtual const TargetRegisterClass * 543 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 544 return NULL; 545 } 546 547 /// getAllocationOrder - Returns the register allocation order for a specified 548 /// register class in the form of a pair of TargetRegisterClass iterators. 549 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 550 getAllocationOrder(const TargetRegisterClass *RC, 551 unsigned HintType, unsigned HintReg, 552 const MachineFunction &MF) const { 553 return std::make_pair(RC->allocation_order_begin(MF), 554 RC->allocation_order_end(MF)); 555 } 556 557 /// ResolveRegAllocHint - Resolves the specified register allocation hint 558 /// to a physical register. Returns the physical register if it is successful. 559 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 560 const MachineFunction &MF) const { 561 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 562 return Reg; 563 return 0; 564 } 565 566 /// UpdateRegAllocHint - A callback to allow target a chance to update 567 /// register allocation hints when a register is "changed" (e.g. coalesced) 568 /// to another register. e.g. On ARM, some virtual registers should target 569 /// register pairs, if one of pair is coalesced to another register, the 570 /// allocation hint of the other half of the pair should be changed to point 571 /// to the new register. 572 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 573 MachineFunction &MF) const { 574 // Do nothing. 575 } 576 577 /// targetHandlesStackFrameRounding - Returns true if the target is 578 /// responsible for rounding up the stack frame (probably at emitPrologue 579 /// time). 580 virtual bool targetHandlesStackFrameRounding() const { 581 return false; 582 } 583 584 /// requiresRegisterScavenging - returns true if the target requires (and can 585 /// make use of) the register scavenger. 586 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 587 return false; 588 } 589 590 /// requiresFrameIndexScavenging - returns true if the target requires post 591 /// PEI scavenging of registers for materializing frame index constants. 592 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 593 return false; 594 } 595 596 /// hasFP - Return true if the specified function should have a dedicated 597 /// frame pointer register. For most targets this is true only if the function 598 /// has variable sized allocas or if frame pointer elimination is disabled. 599 virtual bool hasFP(const MachineFunction &MF) const = 0; 600 601 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 602 /// not required, we reserve argument space for call sites in the function 603 /// immediately on entry to the current function. This eliminates the need for 604 /// add/sub sp brackets around call sites. Returns true if the call frame is 605 /// included as part of the stack frame. 606 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 607 return !hasFP(MF); 608 } 609 610 /// canSimplifyCallFramePseudos - When possible, it's best to simplify the 611 /// call frame pseudo ops before doing frame index elimination. This is 612 /// possible only when frame index references between the pseudos won't 613 /// need adjusted for the call frame adjustments. Normally, that's true 614 /// if the function has a reserved call frame or a frame pointer. Some 615 /// targets (Thumb2, for example) may have more complicated criteria, 616 /// however, and can override this behavior. 617 virtual bool canSimplifyCallFramePseudos(MachineFunction &MF) const { 618 return hasReservedCallFrame(MF) || hasFP(MF); 619 } 620 621 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 622 /// the stack frame of the given function for the specified register. e.g. On 623 /// x86, if the frame register is required, the first fixed stack object is 624 /// reserved as its spill slot. This tells PEI not to create a new stack frame 625 /// object for the given register. It should be called only after 626 /// processFunctionBeforeCalleeSavedScan(). 627 virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg, 628 int &FrameIdx) const { 629 return false; 630 } 631 632 /// needsStackRealignment - true if storage within the function requires the 633 /// stack pointer to be aligned more than the normal calling convention calls 634 /// for. 635 virtual bool needsStackRealignment(const MachineFunction &MF) const { 636 return false; 637 } 638 639 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 640 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 641 /// targets use pseudo instructions in order to abstract away the difference 642 /// between operating with a frame pointer and operating without, through the 643 /// use of these two instructions. 644 /// 645 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 646 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 647 648 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 649 /// code insertion to eliminate call frame setup and destroy pseudo 650 /// instructions (but only if the Target is using them). It is responsible 651 /// for eliminating these instructions, replacing them with concrete 652 /// instructions. This method need only be implemented if using call frame 653 /// setup/destroy pseudo instructions. 654 /// 655 virtual void 656 eliminateCallFramePseudoInstr(MachineFunction &MF, 657 MachineBasicBlock &MBB, 658 MachineBasicBlock::iterator MI) const { 659 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 660 "eliminateCallFramePseudoInstr must be implemented if using" 661 " call frame setup/destroy pseudo instructions!"); 662 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 663 } 664 665 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 666 /// before PrologEpilogInserter scans the physical registers used to determine 667 /// what callee saved registers should be spilled. This method is optional. 668 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 669 RegScavenger *RS = NULL) const { 670 671 } 672 673 /// processFunctionBeforeFrameFinalized - This method is called immediately 674 /// before the specified functions frame layout (MF.getFrameInfo()) is 675 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 676 /// replaced with direct constants. This method is optional. 677 /// 678 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 679 } 680 681 /// saveScavengerRegister - Spill the register so it can be used by the 682 /// register scavenger. Return true if the register was spilled, false 683 /// otherwise. If this function does not spill the register, the scavenger 684 /// will instead spill it to the emergency spill slot. 685 /// 686 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 687 MachineBasicBlock::iterator I, 688 MachineBasicBlock::iterator &UseMI, 689 const TargetRegisterClass *RC, 690 unsigned Reg) const { 691 return false; 692 } 693 694 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 695 /// frame indices from instructions which may use them. The instruction 696 /// referenced by the iterator contains an MO_FrameIndex operand which must be 697 /// eliminated by this method. This method may modify or replace the 698 /// specified instruction, as long as it keeps the iterator pointing at the 699 /// finished product. SPAdj is the SP adjustment due to call frame setup 700 /// instruction. 701 /// 702 /// When -enable-frame-index-scavenging is enabled, the virtual register 703 /// allocated for this frame index is returned and its value is stored in 704 /// *Value. 705 typedef std::pair<unsigned, int> FrameIndexValue; 706 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI, 707 int SPAdj, FrameIndexValue *Value = NULL, 708 RegScavenger *RS=NULL) const = 0; 709 710 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 711 /// the function. 712 virtual void emitPrologue(MachineFunction &MF) const = 0; 713 virtual void emitEpilogue(MachineFunction &MF, 714 MachineBasicBlock &MBB) const = 0; 715 716 //===--------------------------------------------------------------------===// 717 /// Debug information queries. 718 719 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 720 /// number. Returns -1 if there is no equivalent value. The second 721 /// parameter allows targets to use different numberings for EH info and 722 /// debugging info. 723 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 724 725 /// getFrameRegister - This method should return the register used as a base 726 /// for values allocated in the current stack frame. 727 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 728 729 /// getFrameIndexOffset - Returns the displacement from the frame register to 730 /// the stack frame of the specified index. 731 virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const; 732 733 /// getFrameIndexReference - This method should return the base register 734 /// and offset used to reference a frame index location. The offset is 735 /// returned directly, and the base register is returned via FrameReg. 736 virtual int getFrameIndexReference(const MachineFunction &MF, int FI, 737 unsigned &FrameReg) const { 738 // By default, assume all frame indices are referenced via whatever 739 // getFrameRegister() says. The target can override this if it's doing 740 // something different. 741 FrameReg = getFrameRegister(MF); 742 return getFrameIndexOffset(MF, FI); 743 } 744 745 /// getRARegister - This method should return the register where the return 746 /// address can be found. 747 virtual unsigned getRARegister() const = 0; 748 749 /// getInitialFrameState - Returns a list of machine moves that are assumed 750 /// on entry to all functions. Note that LabelID is ignored (assumed to be 751 /// the beginning of the function.) 752 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 753}; 754 755 756// This is useful when building IndexedMaps keyed on virtual registers 757struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 758 unsigned operator()(unsigned Reg) const { 759 return Reg - TargetRegisterInfo::FirstVirtualRegister; 760 } 761}; 762 763/// getCommonSubClass - find the largest common subclass of A and B. Return NULL 764/// if there is no common subclass. 765const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, 766 const TargetRegisterClass *B); 767 768} // End llvm namespace 769 770#endif 771