TargetRegisterInfo.h revision d9c1fa5205cc31474f9f9a6d715af32098a1a719
11e230224d412d763b98472a8cd92a8349afba99bLiming Gao//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 21e230224d412d763b98472a8cd92a8349afba99bLiming Gao// 31e230224d412d763b98472a8cd92a8349afba99bLiming Gao// The LLVM Compiler Infrastructure 41e230224d412d763b98472a8cd92a8349afba99bLiming Gao// 51e230224d412d763b98472a8cd92a8349afba99bLiming Gao// This file is distributed under the University of Illinois Open Source 61e230224d412d763b98472a8cd92a8349afba99bLiming Gao// License. See LICENSE.TXT for details. 71e230224d412d763b98472a8cd92a8349afba99bLiming Gao// 81e230224d412d763b98472a8cd92a8349afba99bLiming Gao//===----------------------------------------------------------------------===// 91e230224d412d763b98472a8cd92a8349afba99bLiming Gao// 101e230224d412d763b98472a8cd92a8349afba99bLiming Gao// This file describes an abstract interface used to get information about a 111e230224d412d763b98472a8cd92a8349afba99bLiming Gao// target machines register file. This information is used for a variety of 121e230224d412d763b98472a8cd92a8349afba99bLiming Gao// purposed, especially register allocation. 131e230224d412d763b98472a8cd92a8349afba99bLiming Gao// 141e230224d412d763b98472a8cd92a8349afba99bLiming Gao//===----------------------------------------------------------------------===// 151e230224d412d763b98472a8cd92a8349afba99bLiming Gao 161e230224d412d763b98472a8cd92a8349afba99bLiming Gao#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 171e230224d412d763b98472a8cd92a8349afba99bLiming Gao#define LLVM_TARGET_TARGETREGISTERINFO_H 181e230224d412d763b98472a8cd92a8349afba99bLiming Gao 191e230224d412d763b98472a8cd92a8349afba99bLiming Gao#include "llvm/MC/MCRegisterInfo.h" 201e230224d412d763b98472a8cd92a8349afba99bLiming Gao#include "llvm/CodeGen/MachineBasicBlock.h" 211e230224d412d763b98472a8cd92a8349afba99bLiming Gao#include "llvm/CodeGen/ValueTypes.h" 221e230224d412d763b98472a8cd92a8349afba99bLiming Gao#include "llvm/ADT/ArrayRef.h" 231e230224d412d763b98472a8cd92a8349afba99bLiming Gao#include <cassert> 241e230224d412d763b98472a8cd92a8349afba99bLiming Gao#include <functional> 251e230224d412d763b98472a8cd92a8349afba99bLiming Gao 261e230224d412d763b98472a8cd92a8349afba99bLiming Gaonamespace llvm { 271e230224d412d763b98472a8cd92a8349afba99bLiming Gao 281e230224d412d763b98472a8cd92a8349afba99bLiming Gaoclass BitVector; 291e230224d412d763b98472a8cd92a8349afba99bLiming Gaoclass MachineFunction; 301e230224d412d763b98472a8cd92a8349afba99bLiming Gaoclass RegScavenger; 311e230224d412d763b98472a8cd92a8349afba99bLiming Gaotemplate<class T> class SmallVectorImpl; 321e230224d412d763b98472a8cd92a8349afba99bLiming Gaoclass raw_ostream; 331e230224d412d763b98472a8cd92a8349afba99bLiming Gao 341e230224d412d763b98472a8cd92a8349afba99bLiming Gaoclass TargetRegisterClass { 351e230224d412d763b98472a8cd92a8349afba99bLiming Gaopublic: 361e230224d412d763b98472a8cd92a8349afba99bLiming Gao typedef const unsigned* iterator; 371e230224d412d763b98472a8cd92a8349afba99bLiming Gao typedef const unsigned* const_iterator; 381e230224d412d763b98472a8cd92a8349afba99bLiming Gao typedef const EVT* vt_iterator; 391e230224d412d763b98472a8cd92a8349afba99bLiming Gao typedef const TargetRegisterClass* const * sc_iterator; 401e230224d412d763b98472a8cd92a8349afba99bLiming Gaoprivate: 411e230224d412d763b98472a8cd92a8349afba99bLiming Gao const MCRegisterClass *MC; 421e230224d412d763b98472a8cd92a8349afba99bLiming Gao const vt_iterator VTs; 431e230224d412d763b98472a8cd92a8349afba99bLiming Gao const unsigned *SubClassMask; 441e230224d412d763b98472a8cd92a8349afba99bLiming Gao const sc_iterator SuperClasses; 451e230224d412d763b98472a8cd92a8349afba99bLiming Gao const sc_iterator SuperRegClasses; 461e230224d412d763b98472a8cd92a8349afba99bLiming Gaopublic: 471e230224d412d763b98472a8cd92a8349afba99bLiming Gao TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts, 481e230224d412d763b98472a8cd92a8349afba99bLiming Gao const unsigned *subcm, 491e230224d412d763b98472a8cd92a8349afba99bLiming Gao const TargetRegisterClass * const *supcs, 501e230224d412d763b98472a8cd92a8349afba99bLiming Gao const TargetRegisterClass * const *superregcs) 511e230224d412d763b98472a8cd92a8349afba99bLiming Gao : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs), 521e230224d412d763b98472a8cd92a8349afba99bLiming Gao SuperRegClasses(superregcs) {} 531e230224d412d763b98472a8cd92a8349afba99bLiming Gao 541e230224d412d763b98472a8cd92a8349afba99bLiming Gao virtual ~TargetRegisterClass() {} // Allow subclasses 551e230224d412d763b98472a8cd92a8349afba99bLiming Gao 561e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getID() - Return the register class ID number. 571e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 581e230224d412d763b98472a8cd92a8349afba99bLiming Gao unsigned getID() const { return MC->getID(); } 591e230224d412d763b98472a8cd92a8349afba99bLiming Gao 601e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getName() - Return the register class name for debugging. 611e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 621e230224d412d763b98472a8cd92a8349afba99bLiming Gao const char *getName() const { return MC->getName(); } 631e230224d412d763b98472a8cd92a8349afba99bLiming Gao 641e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// begin/end - Return all of the registers in this class. 651e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 661e230224d412d763b98472a8cd92a8349afba99bLiming Gao iterator begin() const { return MC->begin(); } 671e230224d412d763b98472a8cd92a8349afba99bLiming Gao iterator end() const { return MC->end(); } 681e230224d412d763b98472a8cd92a8349afba99bLiming Gao 691e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getNumRegs - Return the number of registers in this class. 701e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 711e230224d412d763b98472a8cd92a8349afba99bLiming Gao unsigned getNumRegs() const { return MC->getNumRegs(); } 721e230224d412d763b98472a8cd92a8349afba99bLiming Gao 731e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getRegister - Return the specified register in the class. 741e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 751e230224d412d763b98472a8cd92a8349afba99bLiming Gao unsigned getRegister(unsigned i) const { 761e230224d412d763b98472a8cd92a8349afba99bLiming Gao return MC->getRegister(i); 771e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 781e230224d412d763b98472a8cd92a8349afba99bLiming Gao 791e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// contains - Return true if the specified register is included in this 801e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// register class. This does not include virtual registers. 811e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool contains(unsigned Reg) const { 821e230224d412d763b98472a8cd92a8349afba99bLiming Gao return MC->contains(Reg); 831e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 841e230224d412d763b98472a8cd92a8349afba99bLiming Gao 851e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// contains - Return true if both registers are in this class. 861e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool contains(unsigned Reg1, unsigned Reg2) const { 871e230224d412d763b98472a8cd92a8349afba99bLiming Gao return MC->contains(Reg1, Reg2); 881e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 891e230224d412d763b98472a8cd92a8349afba99bLiming Gao 901e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getSize - Return the size of the register in bytes, which is also the size 911e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// of a stack slot allocated to hold a spilled copy of this register. 921e230224d412d763b98472a8cd92a8349afba99bLiming Gao unsigned getSize() const { return MC->getSize(); } 931e230224d412d763b98472a8cd92a8349afba99bLiming Gao 941e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getAlignment - Return the minimum required alignment for a register of 951e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// this class. 961e230224d412d763b98472a8cd92a8349afba99bLiming Gao unsigned getAlignment() const { return MC->getAlignment(); } 971e230224d412d763b98472a8cd92a8349afba99bLiming Gao 981e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getCopyCost - Return the cost of copying a value between two registers in 991e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// this class. A negative number means the register class is very expensive 1001e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// to copy e.g. status flag register classes. 1011e230224d412d763b98472a8cd92a8349afba99bLiming Gao int getCopyCost() const { return MC->getCopyCost(); } 1021e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1031e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isAllocatable - Return true if this register class may be used to create 1041e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// virtual registers. 1051e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool isAllocatable() const { return MC->isAllocatable(); } 1061e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1071e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// hasType - return true if this TargetRegisterClass has the ValueType vt. 1081e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 1091e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool hasType(EVT vt) const { 1101e230224d412d763b98472a8cd92a8349afba99bLiming Gao for(int i = 0; VTs[i] != MVT::Other; ++i) 1111e230224d412d763b98472a8cd92a8349afba99bLiming Gao if (VTs[i] == vt) 1121e230224d412d763b98472a8cd92a8349afba99bLiming Gao return true; 1131e230224d412d763b98472a8cd92a8349afba99bLiming Gao return false; 1141e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1151e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1161e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// vt_begin / vt_end - Loop over all of the value types that can be 1171e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// represented by values in this register class. 1181e230224d412d763b98472a8cd92a8349afba99bLiming Gao vt_iterator vt_begin() const { 1191e230224d412d763b98472a8cd92a8349afba99bLiming Gao return VTs; 1201e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1211e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1221e230224d412d763b98472a8cd92a8349afba99bLiming Gao vt_iterator vt_end() const { 1231e230224d412d763b98472a8cd92a8349afba99bLiming Gao vt_iterator I = VTs; 1241e230224d412d763b98472a8cd92a8349afba99bLiming Gao while (*I != MVT::Other) ++I; 1251e230224d412d763b98472a8cd92a8349afba99bLiming Gao return I; 1261e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1271e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1281e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// superregclasses_begin / superregclasses_end - Loop over all of 1291e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// the superreg register classes of this register class. 1301e230224d412d763b98472a8cd92a8349afba99bLiming Gao sc_iterator superregclasses_begin() const { 1311e230224d412d763b98472a8cd92a8349afba99bLiming Gao return SuperRegClasses; 1321e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1331e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1341e230224d412d763b98472a8cd92a8349afba99bLiming Gao sc_iterator superregclasses_end() const { 1351e230224d412d763b98472a8cd92a8349afba99bLiming Gao sc_iterator I = SuperRegClasses; 1361e230224d412d763b98472a8cd92a8349afba99bLiming Gao while (*I != NULL) ++I; 1371e230224d412d763b98472a8cd92a8349afba99bLiming Gao return I; 1381e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1391e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1401e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// hasSubClass - return true if the specified TargetRegisterClass 1411e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// is a proper sub-class of this TargetRegisterClass. 1421e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool hasSubClass(const TargetRegisterClass *RC) const { 1431e230224d412d763b98472a8cd92a8349afba99bLiming Gao return RC != this && hasSubClassEq(RC); 1441e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1451e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1461e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 1471e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// class. 1481e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool hasSubClassEq(const TargetRegisterClass *RC) const { 1491e230224d412d763b98472a8cd92a8349afba99bLiming Gao unsigned ID = RC->getID(); 1501e230224d412d763b98472a8cd92a8349afba99bLiming Gao return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 1511e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1521e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1531e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// hasSuperClass - return true if the specified TargetRegisterClass is a 1541e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// proper super-class of this TargetRegisterClass. 1551e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool hasSuperClass(const TargetRegisterClass *RC) const { 1561e230224d412d763b98472a8cd92a8349afba99bLiming Gao return RC->hasSubClass(this); 1571e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1581e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1591e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 1601e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// class. 1611e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool hasSuperClassEq(const TargetRegisterClass *RC) const { 1621e230224d412d763b98472a8cd92a8349afba99bLiming Gao return RC->hasSubClassEq(this); 1631e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1641e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1651e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getSubClassMask - Returns a bit vector of subclasses, including this one. 1661e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 1671e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// use it. 1681e230224d412d763b98472a8cd92a8349afba99bLiming Gao const unsigned *getSubClassMask() const { 1691e230224d412d763b98472a8cd92a8349afba99bLiming Gao return SubClassMask; 1701e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1711e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1721e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getSuperClasses - Returns a NULL terminated list of super-classes. The 1731e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// classes are ordered by ID which is also a topological ordering from large 1741e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// to small classes. The list does NOT include the current class. 1751e230224d412d763b98472a8cd92a8349afba99bLiming Gao sc_iterator getSuperClasses() const { 1761e230224d412d763b98472a8cd92a8349afba99bLiming Gao return SuperClasses; 1771e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1781e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1791e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isASubClass - return true if this TargetRegisterClass is a subset 1801e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// class of at least one other TargetRegisterClass. 1811e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool isASubClass() const { 1821e230224d412d763b98472a8cd92a8349afba99bLiming Gao return SuperClasses[0] != 0; 1831e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 1841e230224d412d763b98472a8cd92a8349afba99bLiming Gao 1851e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getRawAllocationOrder - Returns the preferred order for allocating 1861e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// registers from this register class in MF. The raw order comes directly 1871e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// from the .td file and may include reserved registers that are not 1881e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// allocatable. Register allocators should also make sure to allocate 1891e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// callee-saved registers only after all the volatiles are used. The 1901e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// RegisterClassInfo class provides filtered allocation orders with 1911e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// callee-saved registers moved to the end. 1921e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 1931e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// The MachineFunction argument can be used to tune the allocatable 1941e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// registers based on the characteristics of the function, subtarget, or 1951e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// other criteria. 1961e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 1971e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// By default, this method returns all registers in the class. 1981e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 1991e230224d412d763b98472a8cd92a8349afba99bLiming Gao virtual 2001e230224d412d763b98472a8cd92a8349afba99bLiming Gao ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { 2011e230224d412d763b98472a8cd92a8349afba99bLiming Gao return makeArrayRef(begin(), getNumRegs()); 2021e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 2031e230224d412d763b98472a8cd92a8349afba99bLiming Gao}; 2041e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2051e230224d412d763b98472a8cd92a8349afba99bLiming Gao/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 2061e230224d412d763b98472a8cd92a8349afba99bLiming Gao/// registers. These are used by codegen, not by MC. 2071e230224d412d763b98472a8cd92a8349afba99bLiming Gaostruct TargetRegisterInfoDesc { 2081e230224d412d763b98472a8cd92a8349afba99bLiming Gao unsigned CostPerUse; // Extra cost of instructions using register. 2091e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool inAllocatableClass; // Register belongs to an allocatable regclass. 2101e230224d412d763b98472a8cd92a8349afba99bLiming Gao}; 2111e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2121e230224d412d763b98472a8cd92a8349afba99bLiming Gao/// TargetRegisterInfo base class - We assume that the target defines a static 2131e230224d412d763b98472a8cd92a8349afba99bLiming Gao/// array of TargetRegisterDesc objects that represent all of the machine 2141e230224d412d763b98472a8cd92a8349afba99bLiming Gao/// registers that the target has. As such, we simply have to track a pointer 2151e230224d412d763b98472a8cd92a8349afba99bLiming Gao/// to this array so that we can turn register number into a register 2161e230224d412d763b98472a8cd92a8349afba99bLiming Gao/// descriptor. 2171e230224d412d763b98472a8cd92a8349afba99bLiming Gao/// 2181e230224d412d763b98472a8cd92a8349afba99bLiming Gaoclass TargetRegisterInfo : public MCRegisterInfo { 2191e230224d412d763b98472a8cd92a8349afba99bLiming Gaopublic: 2201e230224d412d763b98472a8cd92a8349afba99bLiming Gao typedef const TargetRegisterClass * const * regclass_iterator; 2211e230224d412d763b98472a8cd92a8349afba99bLiming Gaoprivate: 2221e230224d412d763b98472a8cd92a8349afba99bLiming Gao const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 2231e230224d412d763b98472a8cd92a8349afba99bLiming Gao const char *const *SubRegIndexNames; // Names of subreg indexes. 2241e230224d412d763b98472a8cd92a8349afba99bLiming Gao regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 2251e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2261e230224d412d763b98472a8cd92a8349afba99bLiming Gaoprotected: 2271e230224d412d763b98472a8cd92a8349afba99bLiming Gao TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 2281e230224d412d763b98472a8cd92a8349afba99bLiming Gao regclass_iterator RegClassBegin, 2291e230224d412d763b98472a8cd92a8349afba99bLiming Gao regclass_iterator RegClassEnd, 2301e230224d412d763b98472a8cd92a8349afba99bLiming Gao const char *const *subregindexnames); 2311e230224d412d763b98472a8cd92a8349afba99bLiming Gao virtual ~TargetRegisterInfo(); 2321e230224d412d763b98472a8cd92a8349afba99bLiming Gaopublic: 2331e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2341e230224d412d763b98472a8cd92a8349afba99bLiming Gao // Register numbers can represent physical registers, virtual registers, and 2351e230224d412d763b98472a8cd92a8349afba99bLiming Gao // sometimes stack slots. The unsigned values are divided into these ranges: 2361e230224d412d763b98472a8cd92a8349afba99bLiming Gao // 2371e230224d412d763b98472a8cd92a8349afba99bLiming Gao // 0 Not a register, can be used as a sentinel. 2381e230224d412d763b98472a8cd92a8349afba99bLiming Gao // [1;2^30) Physical registers assigned by TableGen. 2391e230224d412d763b98472a8cd92a8349afba99bLiming Gao // [2^30;2^31) Stack slots. (Rarely used.) 2401e230224d412d763b98472a8cd92a8349afba99bLiming Gao // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 2411e230224d412d763b98472a8cd92a8349afba99bLiming Gao // 2421e230224d412d763b98472a8cd92a8349afba99bLiming Gao // Further sentinels can be allocated from the small negative integers. 2431e230224d412d763b98472a8cd92a8349afba99bLiming Gao // DenseMapInfo<unsigned> uses -1u and -2u. 2441e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2451e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isStackSlot - Sometimes it is useful the be able to store a non-negative 2461e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// frame index in a variable that normally holds a register. isStackSlot() 2471e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// returns true if Reg is in the range used for stack slots. 2481e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 2491e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 2501e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// slots, so if a variable may contains a stack slot, always check 2511e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isStackSlot() first. 2521e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 2531e230224d412d763b98472a8cd92a8349afba99bLiming Gao static bool isStackSlot(unsigned Reg) { 2541e230224d412d763b98472a8cd92a8349afba99bLiming Gao return int(Reg) >= (1 << 30); 2551e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 2561e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2571e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// stackSlot2Index - Compute the frame index from a register value 2581e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// representing a stack slot. 2591e230224d412d763b98472a8cd92a8349afba99bLiming Gao static int stackSlot2Index(unsigned Reg) { 2601e230224d412d763b98472a8cd92a8349afba99bLiming Gao assert(isStackSlot(Reg) && "Not a stack slot"); 2611e230224d412d763b98472a8cd92a8349afba99bLiming Gao return int(Reg - (1u << 30)); 2621e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 2631e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2641e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// index2StackSlot - Convert a non-negative frame index to a stack slot 2651e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// register value. 2661e230224d412d763b98472a8cd92a8349afba99bLiming Gao static unsigned index2StackSlot(int FI) { 2671e230224d412d763b98472a8cd92a8349afba99bLiming Gao assert(FI >= 0 && "Cannot hold a negative frame index."); 2681e230224d412d763b98472a8cd92a8349afba99bLiming Gao return FI + (1u << 30); 2691e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 2701e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2711e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isPhysicalRegister - Return true if the specified register number is in 2721e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// the physical register namespace. 2731e230224d412d763b98472a8cd92a8349afba99bLiming Gao static bool isPhysicalRegister(unsigned Reg) { 2741e230224d412d763b98472a8cd92a8349afba99bLiming Gao assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 2751e230224d412d763b98472a8cd92a8349afba99bLiming Gao return int(Reg) > 0; 2761e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 2771e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2781e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isVirtualRegister - Return true if the specified register number is in 2791e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// the virtual register namespace. 2801e230224d412d763b98472a8cd92a8349afba99bLiming Gao static bool isVirtualRegister(unsigned Reg) { 2811e230224d412d763b98472a8cd92a8349afba99bLiming Gao assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 2821e230224d412d763b98472a8cd92a8349afba99bLiming Gao return int(Reg) < 0; 2831e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 2841e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2851e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// virtReg2Index - Convert a virtual register number to a 0-based index. 2861e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// The first virtual register in a function will get the index 0. 2871e230224d412d763b98472a8cd92a8349afba99bLiming Gao static unsigned virtReg2Index(unsigned Reg) { 2881e230224d412d763b98472a8cd92a8349afba99bLiming Gao assert(isVirtualRegister(Reg) && "Not a virtual register"); 2891e230224d412d763b98472a8cd92a8349afba99bLiming Gao return Reg & ~(1u << 31); 2901e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 2911e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2921e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// index2VirtReg - Convert a 0-based index to a virtual register number. 2931e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// This is the inverse operation of VirtReg2IndexFunctor below. 2941e230224d412d763b98472a8cd92a8349afba99bLiming Gao static unsigned index2VirtReg(unsigned Index) { 2951e230224d412d763b98472a8cd92a8349afba99bLiming Gao return Index | (1u << 31); 2961e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 2971e230224d412d763b98472a8cd92a8349afba99bLiming Gao 2981e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getMinimalPhysRegClass - Returns the Register Class of a physical 2991e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// register of the given type, picking the most sub register class of 3001e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// the right type that contains this physreg. 3011e230224d412d763b98472a8cd92a8349afba99bLiming Gao const TargetRegisterClass * 3021e230224d412d763b98472a8cd92a8349afba99bLiming Gao getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 3031e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3041e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getAllocatableSet - Returns a bitset indexed by register number 3051e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// indicating if a register is allocatable or not. If a register class is 3061e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// specified, returns the subset for the class. 3071e230224d412d763b98472a8cd92a8349afba99bLiming Gao BitVector getAllocatableSet(const MachineFunction &MF, 3081e230224d412d763b98472a8cd92a8349afba99bLiming Gao const TargetRegisterClass *RC = NULL) const; 3091e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3101e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getCostPerUse - Return the additional cost of using this register instead 3111e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// of other registers in its class. 3121e230224d412d763b98472a8cd92a8349afba99bLiming Gao unsigned getCostPerUse(unsigned RegNo) const { 3131e230224d412d763b98472a8cd92a8349afba99bLiming Gao return InfoDesc[RegNo].CostPerUse; 3141e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 3151e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3161e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isInAllocatableClass - Return true if the register is in the allocation 3171e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// of any register class. 3181e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool isInAllocatableClass(unsigned RegNo) const { 3191e230224d412d763b98472a8cd92a8349afba99bLiming Gao return InfoDesc[RegNo].inAllocatableClass; 3201e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 3211e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3221e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getSubRegIndexName - Return the human-readable symbolic target-specific 3231e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// name for the specified SubRegIndex. 3241e230224d412d763b98472a8cd92a8349afba99bLiming Gao const char *getSubRegIndexName(unsigned SubIdx) const { 3251e230224d412d763b98472a8cd92a8349afba99bLiming Gao assert(SubIdx && "This is not a subregister index"); 3261e230224d412d763b98472a8cd92a8349afba99bLiming Gao return SubRegIndexNames[SubIdx-1]; 3271e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 3281e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3291e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// regsOverlap - Returns true if the two registers are equal or alias each 3301e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// other. The registers may be virtual register. 3311e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool regsOverlap(unsigned regA, unsigned regB) const { 3321e230224d412d763b98472a8cd92a8349afba99bLiming Gao if (regA == regB) return true; 3331e230224d412d763b98472a8cd92a8349afba99bLiming Gao if (isVirtualRegister(regA) || isVirtualRegister(regB)) 3341e230224d412d763b98472a8cd92a8349afba99bLiming Gao return false; 3351e230224d412d763b98472a8cd92a8349afba99bLiming Gao for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { 3361e230224d412d763b98472a8cd92a8349afba99bLiming Gao if (*regList == regB) return true; 3371e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 3381e230224d412d763b98472a8cd92a8349afba99bLiming Gao return false; 3391e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 3401e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3411e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isSubRegister - Returns true if regB is a sub-register of regA. 3421e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 3431e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool isSubRegister(unsigned regA, unsigned regB) const { 3441e230224d412d763b98472a8cd92a8349afba99bLiming Gao return isSuperRegister(regB, regA); 3451e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 3461e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3471e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// isSuperRegister - Returns true if regB is a super-register of regA. 3481e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// 3491e230224d412d763b98472a8cd92a8349afba99bLiming Gao bool isSuperRegister(unsigned regA, unsigned regB) const { 3501e230224d412d763b98472a8cd92a8349afba99bLiming Gao for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ 3511e230224d412d763b98472a8cd92a8349afba99bLiming Gao if (*regList == regB) return true; 3521e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 3531e230224d412d763b98472a8cd92a8349afba99bLiming Gao return false; 3541e230224d412d763b98472a8cd92a8349afba99bLiming Gao } 3551e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3561e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// getCalleeSavedRegs - Return a null-terminated list of all of the 3571e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// callee saved registers on this target. The register should be in the 3581e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// order of desired callee-save stack frame offset. The first register is 3591e230224d412d763b98472a8cd92a8349afba99bLiming Gao /// closed to the incoming stack pointer if stack grows down, and vice versa. 3601e230224d412d763b98472a8cd92a8349afba99bLiming Gao virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 3611e230224d412d763b98472a8cd92a8349afba99bLiming Gao const = 0; 3621e230224d412d763b98472a8cd92a8349afba99bLiming Gao 3631e230224d412d763b98472a8cd92a8349afba99bLiming Gao 364 /// getReservedRegs - Returns a bitset indexed by physical register number 365 /// indicating if a register is a special register that has particular uses 366 /// and should be considered unavailable at all times, e.g. SP, RA. This is 367 /// used by register scavenger to determine what registers are free. 368 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 369 370 /// getSubReg - Returns the physical register number of sub-register "Index" 371 /// for physical register RegNo. Return zero if the sub-register does not 372 /// exist. 373 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 374 375 /// getSubRegIndex - For a given register pair, return the sub-register index 376 /// if the second register is a sub-register of the first. Return zero 377 /// otherwise. 378 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 379 380 /// getMatchingSuperReg - Return a super-register of the specified register 381 /// Reg so its sub-register of index SubIdx is Reg. 382 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 383 const TargetRegisterClass *RC) const { 384 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 385 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 386 return SR; 387 return 0; 388 } 389 390 /// canCombineSubRegIndices - Given a register class and a list of 391 /// subregister indices, return true if it's possible to combine the 392 /// subregister indices into one that corresponds to a larger 393 /// subregister. Return the new subregister index by reference. Note the 394 /// new index may be zero if the given subregisters can be combined to 395 /// form the whole register. 396 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 397 SmallVectorImpl<unsigned> &SubIndices, 398 unsigned &NewSubIdx) const { 399 return 0; 400 } 401 402 /// getMatchingSuperRegClass - Return a subclass of the specified register 403 /// class A so that each register in it has a sub-register of the 404 /// specified sub-register index which is in the specified register class B. 405 virtual const TargetRegisterClass * 406 getMatchingSuperRegClass(const TargetRegisterClass *A, 407 const TargetRegisterClass *B, unsigned Idx) const { 408 return 0; 409 } 410 411 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 412 /// supports the sub-register index Idx. 413 /// If no such sub-class exists, return NULL. 414 /// If all registers in RC already have an Idx sub-register, return RC. 415 /// 416 /// TableGen generates a version of this function that is good enough in most 417 /// cases. Targets can override if they have constraints that TableGen 418 /// doesn't understand. For example, the x86 sub_8bit sub-register index is 419 /// supported by the full GR32 register class in 64-bit mode, but only by the 420 /// GR32_ABCD regiister class in 32-bit mode. 421 /// 422 virtual const TargetRegisterClass * 423 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0; 424 425 /// composeSubRegIndices - Return the subregister index you get from composing 426 /// two subregister indices. 427 /// 428 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 429 /// returns c. Note that composeSubRegIndices does not tell you about illegal 430 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 431 /// b, composeSubRegIndices doesn't tell you. 432 /// 433 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 434 /// ssub_0:S0 - ssub_3:S3 subregs. 435 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 436 /// 437 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 438 // This default implementation is correct for most targets. 439 return b; 440 } 441 442 //===--------------------------------------------------------------------===// 443 // Register Class Information 444 // 445 446 /// Register class iterators 447 /// 448 regclass_iterator regclass_begin() const { return RegClassBegin; } 449 regclass_iterator regclass_end() const { return RegClassEnd; } 450 451 unsigned getNumRegClasses() const { 452 return (unsigned)(regclass_end()-regclass_begin()); 453 } 454 455 /// getRegClass - Returns the register class associated with the enumeration 456 /// value. See class MCOperandInfo. 457 const TargetRegisterClass *getRegClass(unsigned i) const { 458 assert(i < getNumRegClasses() && "Register Class ID out of range"); 459 return RegClassBegin[i]; 460 } 461 462 /// getCommonSubClass - find the largest common subclass of A and B. Return 463 /// NULL if there is no common subclass. 464 const TargetRegisterClass * 465 getCommonSubClass(const TargetRegisterClass *A, 466 const TargetRegisterClass *B) const; 467 468 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 469 /// values. If a target supports multiple different pointer register classes, 470 /// kind specifies which one is indicated. 471 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 472 assert(0 && "Target didn't implement getPointerRegClass!"); 473 return 0; // Must return a value in order to compile with VS 2005 474 } 475 476 /// getCrossCopyRegClass - Returns a legal register class to copy a register 477 /// in the specified class to or from. If it is possible to copy the register 478 /// directly without using a cross register class copy, return the specified 479 /// RC. Returns NULL if it is not possible to copy between a two registers of 480 /// the specified class. 481 virtual const TargetRegisterClass * 482 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 483 return RC; 484 } 485 486 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 487 /// legal to use in the current sub-target and has the same spill size. 488 /// The returned register class can be used to create virtual registers which 489 /// means that all its registers can be copied and spilled. 490 virtual const TargetRegisterClass* 491 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 492 /// The default implementation is very conservative and doesn't allow the 493 /// register allocator to inflate register classes. 494 return RC; 495 } 496 497 /// getRegPressureLimit - Return the register pressure "high water mark" for 498 /// the specific register class. The scheduler is in high register pressure 499 /// mode (for the specific register class) if it goes over the limit. 500 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 501 MachineFunction &MF) const { 502 return 0; 503 } 504 505 /// getRawAllocationOrder - Returns the register allocation order for a 506 /// specified register class with a target-dependent hint. The returned list 507 /// may contain reserved registers that cannot be allocated. 508 /// 509 /// Register allocators need only call this function to resolve 510 /// target-dependent hints, but it should work without hinting as well. 511 virtual ArrayRef<unsigned> 512 getRawAllocationOrder(const TargetRegisterClass *RC, 513 unsigned HintType, unsigned HintReg, 514 const MachineFunction &MF) const { 515 return RC->getRawAllocationOrder(MF); 516 } 517 518 /// ResolveRegAllocHint - Resolves the specified register allocation hint 519 /// to a physical register. Returns the physical register if it is successful. 520 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 521 const MachineFunction &MF) const { 522 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 523 return Reg; 524 return 0; 525 } 526 527 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 528 /// writing a register from RC in two consecutive instructions. 529 /// This can avoid pipeline stalls on certain architectures. 530 /// It does cause increased register pressure, though. 531 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 532 return false; 533 } 534 535 /// UpdateRegAllocHint - A callback to allow target a chance to update 536 /// register allocation hints when a register is "changed" (e.g. coalesced) 537 /// to another register. e.g. On ARM, some virtual registers should target 538 /// register pairs, if one of pair is coalesced to another register, the 539 /// allocation hint of the other half of the pair should be changed to point 540 /// to the new register. 541 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 542 MachineFunction &MF) const { 543 // Do nothing. 544 } 545 546 /// requiresRegisterScavenging - returns true if the target requires (and can 547 /// make use of) the register scavenger. 548 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 549 return false; 550 } 551 552 /// useFPForScavengingIndex - returns true if the target wants to use 553 /// frame pointer based accesses to spill to the scavenger emergency spill 554 /// slot. 555 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 556 return true; 557 } 558 559 /// requiresFrameIndexScavenging - returns true if the target requires post 560 /// PEI scavenging of registers for materializing frame index constants. 561 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 562 return false; 563 } 564 565 /// requiresVirtualBaseRegisters - Returns true if the target wants the 566 /// LocalStackAllocation pass to be run and virtual base registers 567 /// used for more efficient stack access. 568 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 569 return false; 570 } 571 572 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 573 /// the stack frame of the given function for the specified register. e.g. On 574 /// x86, if the frame register is required, the first fixed stack object is 575 /// reserved as its spill slot. This tells PEI not to create a new stack frame 576 /// object for the given register. It should be called only after 577 /// processFunctionBeforeCalleeSavedScan(). 578 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 579 int &FrameIdx) const { 580 return false; 581 } 582 583 /// needsStackRealignment - true if storage within the function requires the 584 /// stack pointer to be aligned more than the normal calling convention calls 585 /// for. 586 virtual bool needsStackRealignment(const MachineFunction &MF) const { 587 return false; 588 } 589 590 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 591 /// index in the instruction, if there is one. 592 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 593 int Idx) const { 594 return 0; 595 } 596 597 /// needsFrameBaseReg - Returns true if the instruction's frame index 598 /// reference would be better served by a base register other than FP 599 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 600 /// references it should create new base registers for. 601 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 602 return false; 603 } 604 605 /// materializeFrameBaseRegister - Insert defining instruction(s) for 606 /// BaseReg to be a pointer to FrameIdx before insertion point I. 607 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 608 unsigned BaseReg, int FrameIdx, 609 int64_t Offset) const { 610 assert(0 && "materializeFrameBaseRegister does not exist on this target"); 611 } 612 613 /// resolveFrameIndex - Resolve a frame index operand of an instruction 614 /// to reference the indicated base register plus offset instead. 615 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 616 unsigned BaseReg, int64_t Offset) const { 617 assert(0 && "resolveFrameIndex does not exist on this target"); 618 } 619 620 /// isFrameOffsetLegal - Determine whether a given offset immediate is 621 /// encodable to resolve a frame index. 622 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 623 int64_t Offset) const { 624 assert(0 && "isFrameOffsetLegal does not exist on this target"); 625 return false; // Must return a value in order to compile with VS 2005 626 } 627 628 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 629 /// code insertion to eliminate call frame setup and destroy pseudo 630 /// instructions (but only if the Target is using them). It is responsible 631 /// for eliminating these instructions, replacing them with concrete 632 /// instructions. This method need only be implemented if using call frame 633 /// setup/destroy pseudo instructions. 634 /// 635 virtual void 636 eliminateCallFramePseudoInstr(MachineFunction &MF, 637 MachineBasicBlock &MBB, 638 MachineBasicBlock::iterator MI) const { 639 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 640 } 641 642 643 /// saveScavengerRegister - Spill the register so it can be used by the 644 /// register scavenger. Return true if the register was spilled, false 645 /// otherwise. If this function does not spill the register, the scavenger 646 /// will instead spill it to the emergency spill slot. 647 /// 648 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 649 MachineBasicBlock::iterator I, 650 MachineBasicBlock::iterator &UseMI, 651 const TargetRegisterClass *RC, 652 unsigned Reg) const { 653 return false; 654 } 655 656 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 657 /// frame indices from instructions which may use them. The instruction 658 /// referenced by the iterator contains an MO_FrameIndex operand which must be 659 /// eliminated by this method. This method may modify or replace the 660 /// specified instruction, as long as it keeps the iterator pointing at the 661 /// finished product. SPAdj is the SP adjustment due to call frame setup 662 /// instruction. 663 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 664 int SPAdj, RegScavenger *RS=NULL) const = 0; 665 666 //===--------------------------------------------------------------------===// 667 /// Debug information queries. 668 669 /// getFrameRegister - This method should return the register used as a base 670 /// for values allocated in the current stack frame. 671 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 672 673 /// getCompactUnwindRegNum - This function maps the register to the number for 674 /// compact unwind encoding. Return -1 if the register isn't valid. 675 virtual int getCompactUnwindRegNum(unsigned, bool) const { 676 return -1; 677 } 678}; 679 680 681// This is useful when building IndexedMaps keyed on virtual registers 682struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 683 unsigned operator()(unsigned Reg) const { 684 return TargetRegisterInfo::virtReg2Index(Reg); 685 } 686}; 687 688/// PrintReg - Helper class for printing registers on a raw_ostream. 689/// Prints virtual and physical registers with or without a TRI instance. 690/// 691/// The format is: 692/// %noreg - NoRegister 693/// %vreg5 - a virtual register. 694/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 695/// %EAX - a physical register 696/// %physreg17 - a physical register when no TRI instance given. 697/// 698/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 699/// 700class PrintReg { 701 const TargetRegisterInfo *TRI; 702 unsigned Reg; 703 unsigned SubIdx; 704public: 705 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 706 : TRI(tri), Reg(reg), SubIdx(subidx) {} 707 void print(raw_ostream&) const; 708}; 709 710static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 711 PR.print(OS); 712 return OS; 713} 714 715} // End llvm namespace 716 717#endif 718