TargetRegisterInfo.h revision e50ed30282bb5b4a9ed952580523f2dda16215ac
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/ADT/DenseSet.h" 22#include <cassert> 23#include <functional> 24 25namespace llvm { 26 27class BitVector; 28class MachineFunction; 29class MachineMove; 30class RegScavenger; 31 32/// TargetRegisterDesc - This record contains all of the information known about 33/// a particular register. The AliasSet field (if not null) contains a pointer 34/// to a Zero terminated array of registers that this register aliases. This is 35/// needed for architectures like X86 which have AL alias AX alias EAX. 36/// Registers that this does not apply to simply should set this to null. 37/// The SubRegs field is a zero terminated array of registers that are 38/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 39/// The SuperRegs field is a zero terminated array of registers that are 40/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 41/// of AX. 42/// 43struct TargetRegisterDesc { 44 const char *AsmName; // Assembly language name for the register 45 const char *Name; // Printable name for the reg (for debugging) 46 const unsigned *AliasSet; // Register Alias Set, described above 47 const unsigned *SubRegs; // Sub-register set, described above 48 const unsigned *SuperRegs; // Super-register set, described above 49}; 50 51class TargetRegisterClass { 52public: 53 typedef const unsigned* iterator; 54 typedef const unsigned* const_iterator; 55 56 typedef const EVT* vt_iterator; 57 typedef const TargetRegisterClass* const * sc_iterator; 58private: 59 unsigned ID; 60 const char *Name; 61 const vt_iterator VTs; 62 const sc_iterator SubClasses; 63 const sc_iterator SuperClasses; 64 const sc_iterator SubRegClasses; 65 const sc_iterator SuperRegClasses; 66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 67 const int CopyCost; 68 const iterator RegsBegin, RegsEnd; 69 DenseSet<unsigned> RegSet; 70public: 71 TargetRegisterClass(unsigned id, 72 const char *name, 73 const EVT *vts, 74 const TargetRegisterClass * const *subcs, 75 const TargetRegisterClass * const *supcs, 76 const TargetRegisterClass * const *subregcs, 77 const TargetRegisterClass * const *superregcs, 78 unsigned RS, unsigned Al, int CC, 79 iterator RB, iterator RE) 80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 81 SubRegClasses(subregcs), SuperRegClasses(superregcs), 82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) { 83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) 84 RegSet.insert(*I); 85 } 86 virtual ~TargetRegisterClass() {} // Allow subclasses 87 88 /// getID() - Return the register class ID number. 89 /// 90 unsigned getID() const { return ID; } 91 92 /// getName() - Return the register class name for debugging. 93 /// 94 const char *getName() const { return Name; } 95 96 /// begin/end - Return all of the registers in this class. 97 /// 98 iterator begin() const { return RegsBegin; } 99 iterator end() const { return RegsEnd; } 100 101 /// getNumRegs - Return the number of registers in this class. 102 /// 103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 104 105 /// getRegister - Return the specified register in the class. 106 /// 107 unsigned getRegister(unsigned i) const { 108 assert(i < getNumRegs() && "Register number out of range!"); 109 return RegsBegin[i]; 110 } 111 112 /// contains - Return true if the specified register is included in this 113 /// register class. 114 bool contains(unsigned Reg) const { 115 return RegSet.count(Reg); 116 } 117 118 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 119 /// 120 bool hasType(EVT vt) const { 121 for(int i = 0; VTs[i] != EVT::Other; ++i) 122 if (VTs[i] == vt) 123 return true; 124 return false; 125 } 126 127 /// vt_begin / vt_end - Loop over all of the value types that can be 128 /// represented by values in this register class. 129 vt_iterator vt_begin() const { 130 return VTs; 131 } 132 133 vt_iterator vt_end() const { 134 vt_iterator I = VTs; 135 while (*I != EVT::Other) ++I; 136 return I; 137 } 138 139 /// subregclasses_begin / subregclasses_end - Loop over all of 140 /// the subreg register classes of this register class. 141 sc_iterator subregclasses_begin() const { 142 return SubRegClasses; 143 } 144 145 sc_iterator subregclasses_end() const { 146 sc_iterator I = SubRegClasses; 147 while (*I != NULL) ++I; 148 return I; 149 } 150 151 /// getSubRegisterRegClass - Return the register class of subregisters with 152 /// index SubIdx, or NULL if no such class exists. 153 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 154 assert(SubIdx>0 && "Invalid subregister index"); 155 for (unsigned s = 0; s != SubIdx-1; ++s) 156 if (!SubRegClasses[s]) 157 return NULL; 158 return SubRegClasses[SubIdx-1]; 159 } 160 161 /// superregclasses_begin / superregclasses_end - Loop over all of 162 /// the superreg register classes of this register class. 163 sc_iterator superregclasses_begin() const { 164 return SuperRegClasses; 165 } 166 167 sc_iterator superregclasses_end() const { 168 sc_iterator I = SuperRegClasses; 169 while (*I != NULL) ++I; 170 return I; 171 } 172 173 /// hasSubClass - return true if the the specified TargetRegisterClass 174 /// is a proper subset of this TargetRegisterClass. 175 bool hasSubClass(const TargetRegisterClass *cs) const { 176 for (int i = 0; SubClasses[i] != NULL; ++i) 177 if (SubClasses[i] == cs) 178 return true; 179 return false; 180 } 181 182 /// subclasses_begin / subclasses_end - Loop over all of the classes 183 /// that are proper subsets of this register class. 184 sc_iterator subclasses_begin() const { 185 return SubClasses; 186 } 187 188 sc_iterator subclasses_end() const { 189 sc_iterator I = SubClasses; 190 while (*I != NULL) ++I; 191 return I; 192 } 193 194 /// hasSuperClass - return true if the specified TargetRegisterClass is a 195 /// proper superset of this TargetRegisterClass. 196 bool hasSuperClass(const TargetRegisterClass *cs) const { 197 for (int i = 0; SuperClasses[i] != NULL; ++i) 198 if (SuperClasses[i] == cs) 199 return true; 200 return false; 201 } 202 203 /// superclasses_begin / superclasses_end - Loop over all of the classes 204 /// that are proper supersets of this register class. 205 sc_iterator superclasses_begin() const { 206 return SuperClasses; 207 } 208 209 sc_iterator superclasses_end() const { 210 sc_iterator I = SuperClasses; 211 while (*I != NULL) ++I; 212 return I; 213 } 214 215 /// isASubClass - return true if this TargetRegisterClass is a subset 216 /// class of at least one other TargetRegisterClass. 217 bool isASubClass() const { 218 return SuperClasses[0] != 0; 219 } 220 221 /// allocation_order_begin/end - These methods define a range of registers 222 /// which specify the registers in this class that are valid to register 223 /// allocate, and the preferred order to allocate them in. For example, 224 /// callee saved registers should be at the end of the list, because it is 225 /// cheaper to allocate caller saved registers. 226 /// 227 /// These methods take a MachineFunction argument, which can be used to tune 228 /// the allocatable registers based on the characteristics of the function. 229 /// One simple example is that the frame pointer register can be used if 230 /// frame-pointer-elimination is performed. 231 /// 232 /// By default, these methods return all registers in the class. 233 /// 234 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 235 return begin(); 236 } 237 virtual iterator allocation_order_end(const MachineFunction &MF) const { 238 return end(); 239 } 240 241 /// getSize - Return the size of the register in bytes, which is also the size 242 /// of a stack slot allocated to hold a spilled copy of this register. 243 unsigned getSize() const { return RegSize; } 244 245 /// getAlignment - Return the minimum required alignment for a register of 246 /// this class. 247 unsigned getAlignment() const { return Alignment; } 248 249 /// getCopyCost - Return the cost of copying a value between two registers in 250 /// this class. A negative number means the register class is very expensive 251 /// to copy e.g. status flag register classes. 252 int getCopyCost() const { return CopyCost; } 253}; 254 255 256/// TargetRegisterInfo base class - We assume that the target defines a static 257/// array of TargetRegisterDesc objects that represent all of the machine 258/// registers that the target has. As such, we simply have to track a pointer 259/// to this array so that we can turn register number into a register 260/// descriptor. 261/// 262class TargetRegisterInfo { 263protected: 264 const unsigned* SubregHash; 265 const unsigned SubregHashSize; 266 const unsigned* SuperregHash; 267 const unsigned SuperregHashSize; 268 const unsigned* AliasesHash; 269 const unsigned AliasesHashSize; 270public: 271 typedef const TargetRegisterClass * const * regclass_iterator; 272private: 273 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 274 unsigned NumRegs; // Number of entries in the array 275 276 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 277 278 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 279protected: 280 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 281 regclass_iterator RegClassBegin, 282 regclass_iterator RegClassEnd, 283 int CallFrameSetupOpcode = -1, 284 int CallFrameDestroyOpcode = -1, 285 const unsigned* subregs = 0, 286 const unsigned subregsize = 0, 287 const unsigned* superregs = 0, 288 const unsigned superregsize = 0, 289 const unsigned* aliases = 0, 290 const unsigned aliasessize = 0); 291 virtual ~TargetRegisterInfo(); 292public: 293 294 enum { // Define some target independent constants 295 /// NoRegister - This physical register is not a real target register. It 296 /// is useful as a sentinal. 297 NoRegister = 0, 298 299 /// FirstVirtualRegister - This is the first register number that is 300 /// considered to be a 'virtual' register, which is part of the SSA 301 /// namespace. This must be the same for all targets, which means that each 302 /// target is limited to 1024 registers. 303 FirstVirtualRegister = 1024 304 }; 305 306 /// isPhysicalRegister - Return true if the specified register number is in 307 /// the physical register namespace. 308 static bool isPhysicalRegister(unsigned Reg) { 309 assert(Reg && "this is not a register!"); 310 return Reg < FirstVirtualRegister; 311 } 312 313 /// isVirtualRegister - Return true if the specified register number is in 314 /// the virtual register namespace. 315 static bool isVirtualRegister(unsigned Reg) { 316 assert(Reg && "this is not a register!"); 317 return Reg >= FirstVirtualRegister; 318 } 319 320 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 321 /// register of the given type. If type is EVT::Other, then just return any 322 /// register class the register belongs to. 323 virtual const TargetRegisterClass * 324 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const; 325 326 /// getAllocatableSet - Returns a bitset indexed by register number 327 /// indicating if a register is allocatable or not. If a register class is 328 /// specified, returns the subset for the class. 329 BitVector getAllocatableSet(MachineFunction &MF, 330 const TargetRegisterClass *RC = NULL) const; 331 332 const TargetRegisterDesc &operator[](unsigned RegNo) const { 333 assert(RegNo < NumRegs && 334 "Attempting to access record for invalid register number!"); 335 return Desc[RegNo]; 336 } 337 338 /// Provide a get method, equivalent to [], but more useful if we have a 339 /// pointer to this object. 340 /// 341 const TargetRegisterDesc &get(unsigned RegNo) const { 342 return operator[](RegNo); 343 } 344 345 /// getAliasSet - Return the set of registers aliased by the specified 346 /// register, or a null list of there are none. The list returned is zero 347 /// terminated. 348 /// 349 const unsigned *getAliasSet(unsigned RegNo) const { 350 return get(RegNo).AliasSet; 351 } 352 353 /// getSubRegisters - Return the list of registers that are sub-registers of 354 /// the specified register, or a null list of there are none. The list 355 /// returned is zero terminated and sorted according to super-sub register 356 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 357 /// 358 const unsigned *getSubRegisters(unsigned RegNo) const { 359 return get(RegNo).SubRegs; 360 } 361 362 /// getSuperRegisters - Return the list of registers that are super-registers 363 /// of the specified register, or a null list of there are none. The list 364 /// returned is zero terminated and sorted according to super-sub register 365 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 366 /// 367 const unsigned *getSuperRegisters(unsigned RegNo) const { 368 return get(RegNo).SuperRegs; 369 } 370 371 /// getAsmName - Return the symbolic target-specific name for the 372 /// specified physical register. 373 const char *getAsmName(unsigned RegNo) const { 374 return get(RegNo).AsmName; 375 } 376 377 /// getName - Return the human-readable symbolic target-specific name for the 378 /// specified physical register. 379 const char *getName(unsigned RegNo) const { 380 return get(RegNo).Name; 381 } 382 383 /// getNumRegs - Return the number of registers this target has (useful for 384 /// sizing arrays holding per register information) 385 unsigned getNumRegs() const { 386 return NumRegs; 387 } 388 389 /// areAliases - Returns true if the two registers alias each other, false 390 /// otherwise 391 bool areAliases(unsigned regA, unsigned regB) const { 392 size_t index = (regA + regB * 37) & (AliasesHashSize-1); 393 unsigned ProbeAmt = 0; 394 while (AliasesHash[index*2] != 0 && 395 AliasesHash[index*2+1] != 0) { 396 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) 397 return true; 398 399 index = (index + ProbeAmt) & (AliasesHashSize-1); 400 ProbeAmt += 2; 401 } 402 403 return false; 404 } 405 406 /// regsOverlap - Returns true if the two registers are equal or alias each 407 /// other. The registers may be virtual register. 408 bool regsOverlap(unsigned regA, unsigned regB) const { 409 if (regA == regB) 410 return true; 411 412 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 413 return false; 414 return areAliases(regA, regB); 415 } 416 417 /// isSubRegister - Returns true if regB is a sub-register of regA. 418 /// 419 bool isSubRegister(unsigned regA, unsigned regB) const { 420 // SubregHash is a simple quadratically probed hash table. 421 size_t index = (regA + regB * 37) & (SubregHashSize-1); 422 unsigned ProbeAmt = 2; 423 while (SubregHash[index*2] != 0 && 424 SubregHash[index*2+1] != 0) { 425 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 426 return true; 427 428 index = (index + ProbeAmt) & (SubregHashSize-1); 429 ProbeAmt += 2; 430 } 431 432 return false; 433 } 434 435 /// isSuperRegister - Returns true if regB is a super-register of regA. 436 /// 437 bool isSuperRegister(unsigned regA, unsigned regB) const { 438 // SuperregHash is a simple quadratically probed hash table. 439 size_t index = (regA + regB * 37) & (SuperregHashSize-1); 440 unsigned ProbeAmt = 2; 441 while (SuperregHash[index*2] != 0 && 442 SuperregHash[index*2+1] != 0) { 443 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB) 444 return true; 445 446 index = (index + ProbeAmt) & (SuperregHashSize-1); 447 ProbeAmt += 2; 448 } 449 450 return false; 451 } 452 453 /// getCalleeSavedRegs - Return a null-terminated list of all of the 454 /// callee saved registers on this target. The register should be in the 455 /// order of desired callee-save stack frame offset. The first register is 456 /// closed to the incoming stack pointer if stack grows down, and vice versa. 457 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 458 const = 0; 459 460 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 461 /// register classes to spill each callee saved register with. The order and 462 /// length of this list match the getCalleeSaveRegs() list. 463 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( 464 const MachineFunction *MF) const =0; 465 466 /// getReservedRegs - Returns a bitset indexed by physical register number 467 /// indicating if a register is a special register that has particular uses 468 /// and should be considered unavailable at all times, e.g. SP, RA. This is 469 /// used by register scavenger to determine what registers are free. 470 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 471 472 /// getSubReg - Returns the physical register number of sub-register "Index" 473 /// for physical register RegNo. Return zero if the sub-register does not 474 /// exist. 475 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 476 477 /// getMatchingSuperReg - Return a super-register of the specified register 478 /// Reg so its sub-register of index SubIdx is Reg. 479 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 480 const TargetRegisterClass *RC) const { 481 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 482 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 483 return SR; 484 return 0; 485 } 486 487 /// getMatchingSuperRegClass - Return a subclass of the specified register 488 /// class A so that each register in it has a sub-register of the 489 /// specified sub-register index which is in the specified register class B. 490 virtual const TargetRegisterClass * 491 getMatchingSuperRegClass(const TargetRegisterClass *A, 492 const TargetRegisterClass *B, unsigned Idx) const { 493 return 0; 494 } 495 496 //===--------------------------------------------------------------------===// 497 // Register Class Information 498 // 499 500 /// Register class iterators 501 /// 502 regclass_iterator regclass_begin() const { return RegClassBegin; } 503 regclass_iterator regclass_end() const { return RegClassEnd; } 504 505 unsigned getNumRegClasses() const { 506 return (unsigned)(regclass_end()-regclass_begin()); 507 } 508 509 /// getRegClass - Returns the register class associated with the enumeration 510 /// value. See class TargetOperandInfo. 511 const TargetRegisterClass *getRegClass(unsigned i) const { 512 assert(i <= getNumRegClasses() && "Register Class ID out of range"); 513 return i ? RegClassBegin[i - 1] : NULL; 514 } 515 516 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 517 /// values. If a target supports multiple different pointer register classes, 518 /// kind specifies which one is indicated. 519 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 520 assert(0 && "Target didn't implement getPointerRegClass!"); 521 return 0; // Must return a value in order to compile with VS 2005 522 } 523 524 /// getCrossCopyRegClass - Returns a legal register class to copy a register 525 /// in the specified class to or from. Returns NULL if it is possible to copy 526 /// between a two registers of the specified class. 527 virtual const TargetRegisterClass * 528 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 529 return NULL; 530 } 531 532 /// getAllocationOrder - Returns the register allocation order for a specified 533 /// register class in the form of a pair of TargetRegisterClass iterators. 534 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 535 getAllocationOrder(const TargetRegisterClass *RC, 536 unsigned HintType, unsigned HintReg, 537 const MachineFunction &MF) const { 538 return std::make_pair(RC->allocation_order_begin(MF), 539 RC->allocation_order_end(MF)); 540 } 541 542 /// ResolveRegAllocHint - Resolves the specified register allocation hint 543 /// to a physical register. Returns the physical register if it is successful. 544 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 545 const MachineFunction &MF) const { 546 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 547 return Reg; 548 return 0; 549 } 550 551 /// UpdateRegAllocHint - A callback to allow target a chance to update 552 /// register allocation hints when a register is "changed" (e.g. coalesced) 553 /// to another register. e.g. On ARM, some virtual registers should target 554 /// register pairs, if one of pair is coalesced to another register, the 555 /// allocation hint of the other half of the pair should be changed to point 556 /// to the new register. 557 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 558 MachineFunction &MF) const { 559 // Do nothing. 560 } 561 562 /// targetHandlesStackFrameRounding - Returns true if the target is 563 /// responsible for rounding up the stack frame (probably at emitPrologue 564 /// time). 565 virtual bool targetHandlesStackFrameRounding() const { 566 return false; 567 } 568 569 /// requiresRegisterScavenging - returns true if the target requires (and can 570 /// make use of) the register scavenger. 571 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 572 return false; 573 } 574 575 /// hasFP - Return true if the specified function should have a dedicated 576 /// frame pointer register. For most targets this is true only if the function 577 /// has variable sized allocas or if frame pointer elimination is disabled. 578 virtual bool hasFP(const MachineFunction &MF) const = 0; 579 580 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 581 /// not required, we reserve argument space for call sites in the function 582 /// immediately on entry to the current function. This eliminates the need for 583 /// add/sub sp brackets around call sites. Returns true if the call frame is 584 /// included as part of the stack frame. 585 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 586 return !hasFP(MF); 587 } 588 589 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 590 /// the stack frame of the given function for the specified register. e.g. On 591 /// x86, if the frame register is required, the first fixed stack object is 592 /// reserved as its spill slot. This tells PEI not to create a new stack frame 593 /// object for the given register. It should be called only after 594 /// processFunctionBeforeCalleeSavedScan(). 595 virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg, 596 int &FrameIdx) const { 597 return false; 598 } 599 600 /// needsStackRealignment - true if storage within the function requires the 601 /// stack pointer to be aligned more than the normal calling convention calls 602 /// for. 603 virtual bool needsStackRealignment(const MachineFunction &MF) const { 604 return false; 605 } 606 607 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 608 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 609 /// targets use pseudo instructions in order to abstract away the difference 610 /// between operating with a frame pointer and operating without, through the 611 /// use of these two instructions. 612 /// 613 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 614 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 615 616 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 617 /// code insertion to eliminate call frame setup and destroy pseudo 618 /// instructions (but only if the Target is using them). It is responsible 619 /// for eliminating these instructions, replacing them with concrete 620 /// instructions. This method need only be implemented if using call frame 621 /// setup/destroy pseudo instructions. 622 /// 623 virtual void 624 eliminateCallFramePseudoInstr(MachineFunction &MF, 625 MachineBasicBlock &MBB, 626 MachineBasicBlock::iterator MI) const { 627 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 628 "eliminateCallFramePseudoInstr must be implemented if using" 629 " call frame setup/destroy pseudo instructions!"); 630 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 631 } 632 633 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 634 /// before PrologEpilogInserter scans the physical registers used to determine 635 /// what callee saved registers should be spilled. This method is optional. 636 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 637 RegScavenger *RS = NULL) const { 638 639 } 640 641 /// processFunctionBeforeFrameFinalized - This method is called immediately 642 /// before the specified functions frame layout (MF.getFrameInfo()) is 643 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 644 /// replaced with direct constants. This method is optional. 645 /// 646 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 647 } 648 649 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 650 /// frame indices from instructions which may use them. The instruction 651 /// referenced by the iterator contains an MO_FrameIndex operand which must be 652 /// eliminated by this method. This method may modify or replace the 653 /// specified instruction, as long as it keeps the iterator pointing the the 654 /// finished product. SPAdj is the SP adjustment due to call frame setup 655 /// instruction. 656 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 657 int SPAdj, RegScavenger *RS=NULL) const = 0; 658 659 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 660 /// the function. 661 virtual void emitPrologue(MachineFunction &MF) const = 0; 662 virtual void emitEpilogue(MachineFunction &MF, 663 MachineBasicBlock &MBB) const = 0; 664 665 //===--------------------------------------------------------------------===// 666 /// Debug information queries. 667 668 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 669 /// number. Returns -1 if there is no equivalent value. The second 670 /// parameter allows targets to use different numberings for EH info and 671 /// debugging info. 672 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 673 674 /// getFrameRegister - This method should return the register used as a base 675 /// for values allocated in the current stack frame. 676 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 677 678 /// getFrameIndexOffset - Returns the displacement from the frame register to 679 /// the stack frame of the specified index. 680 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; 681 682 /// getRARegister - This method should return the register where the return 683 /// address can be found. 684 virtual unsigned getRARegister() const = 0; 685 686 /// getInitialFrameState - Returns a list of machine moves that are assumed 687 /// on entry to all functions. Note that LabelID is ignored (assumed to be 688 /// the beginning of the function.) 689 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 690}; 691 692 693// This is useful when building IndexedMaps keyed on virtual registers 694struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 695 unsigned operator()(unsigned Reg) const { 696 return Reg - TargetRegisterInfo::FirstVirtualRegister; 697 } 698}; 699 700/// getCommonSubClass - find the largest common subclass of A and B. Return NULL 701/// if there is no common subclass. 702const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, 703 const TargetRegisterClass *B); 704 705} // End llvm namespace 706 707#endif 708