TargetRegisterInfo.h revision f8c7394781f7cf27ac52ca087e289436d36844da
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/ADT/DenseSet.h" 22#include <cassert> 23#include <functional> 24 25namespace llvm { 26 27class BitVector; 28class MachineFunction; 29class MachineMove; 30class RegScavenger; 31 32/// TargetRegisterDesc - This record contains all of the information known about 33/// a particular register. The AliasSet field (if not null) contains a pointer 34/// to a Zero terminated array of registers that this register aliases. This is 35/// needed for architectures like X86 which have AL alias AX alias EAX. 36/// Registers that this does not apply to simply should set this to null. 37/// The SubRegs field is a zero terminated array of registers that are 38/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 39/// The SuperRegs field is a zero terminated array of registers that are 40/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 41/// of AX. 42/// 43struct TargetRegisterDesc { 44 const char *AsmName; // Assembly language name for the register 45 const char *Name; // Printable name for the reg (for debugging) 46 const unsigned *AliasSet; // Register Alias Set, described above 47 const unsigned *SubRegs; // Sub-register set, described above 48 const unsigned *SuperRegs; // Super-register set, described above 49}; 50 51class TargetRegisterClass { 52public: 53 typedef const unsigned* iterator; 54 typedef const unsigned* const_iterator; 55 56 typedef const MVT* vt_iterator; 57 typedef const TargetRegisterClass* const * sc_iterator; 58private: 59 unsigned ID; 60 const char *Name; 61 bool isSubClass; 62 const vt_iterator VTs; 63 const sc_iterator SubClasses; 64 const sc_iterator SuperClasses; 65 const sc_iterator SubRegClasses; 66 const sc_iterator SuperRegClasses; 67 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 68 const int CopyCost; 69 const iterator RegsBegin, RegsEnd; 70 DenseSet<unsigned> RegSet; 71public: 72 TargetRegisterClass(unsigned id, 73 const char *name, 74 const MVT *vts, 75 const TargetRegisterClass * const *subcs, 76 const TargetRegisterClass * const *supcs, 77 const TargetRegisterClass * const *subregcs, 78 const TargetRegisterClass * const *superregcs, 79 unsigned RS, unsigned Al, int CC, 80 iterator RB, iterator RE) 81 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 82 SubRegClasses(subregcs), SuperRegClasses(superregcs), 83 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) { 84 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) 85 RegSet.insert(*I); 86 } 87 virtual ~TargetRegisterClass() {} // Allow subclasses 88 89 /// getID() - Return the register class ID number. 90 /// 91 unsigned getID() const { return ID; } 92 93 /// getName() - Return the register class name for debugging. 94 /// 95 const char *getName() const { return Name; } 96 97 /// begin/end - Return all of the registers in this class. 98 /// 99 iterator begin() const { return RegsBegin; } 100 iterator end() const { return RegsEnd; } 101 102 /// getNumRegs - Return the number of registers in this class. 103 /// 104 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 105 106 /// getRegister - Return the specified register in the class. 107 /// 108 unsigned getRegister(unsigned i) const { 109 assert(i < getNumRegs() && "Register number out of range!"); 110 return RegsBegin[i]; 111 } 112 113 /// contains - Return true if the specified register is included in this 114 /// register class. 115 bool contains(unsigned Reg) const { 116 return RegSet.count(Reg); 117 } 118 119 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 120 /// 121 bool hasType(MVT vt) const { 122 for(int i = 0; VTs[i] != MVT::Other; ++i) 123 if (VTs[i] == vt) 124 return true; 125 return false; 126 } 127 128 /// vt_begin / vt_end - Loop over all of the value types that can be 129 /// represented by values in this register class. 130 vt_iterator vt_begin() const { 131 return VTs; 132 } 133 134 vt_iterator vt_end() const { 135 vt_iterator I = VTs; 136 while (*I != MVT::Other) ++I; 137 return I; 138 } 139 140 /// subregclasses_begin / subregclasses_end - Loop over all of 141 /// the subreg register classes of this register class. 142 sc_iterator subregclasses_begin() const { 143 return SubRegClasses; 144 } 145 146 sc_iterator subregclasses_end() const { 147 sc_iterator I = SubRegClasses; 148 while (*I != NULL) ++I; 149 return I; 150 } 151 152 /// superregclasses_begin / superregclasses_end - Loop over all of 153 /// the superreg register classes of this register class. 154 sc_iterator superregclasses_begin() const { 155 return SuperRegClasses; 156 } 157 158 sc_iterator superregclasses_end() const { 159 sc_iterator I = SuperRegClasses; 160 while (*I != NULL) ++I; 161 return I; 162 } 163 164 /// hasSubClass - return true if the the specified TargetRegisterClass 165 /// is a proper subset of this TargetRegisterClass. 166 bool hasSubClass(const TargetRegisterClass *cs) const { 167 for (int i = 0; SubClasses[i] != NULL; ++i) 168 if (SubClasses[i] == cs) 169 return true; 170 return false; 171 } 172 173 /// subclasses_begin / subclasses_end - Loop over all of the classes 174 /// that are proper subsets of this register class. 175 sc_iterator subclasses_begin() const { 176 return SubClasses; 177 } 178 179 sc_iterator subclasses_end() const { 180 sc_iterator I = SubClasses; 181 while (*I != NULL) ++I; 182 return I; 183 } 184 185 /// hasSuperClass - return true if the specified TargetRegisterClass is a 186 /// proper superset of this TargetRegisterClass. 187 bool hasSuperClass(const TargetRegisterClass *cs) const { 188 for (int i = 0; SuperClasses[i] != NULL; ++i) 189 if (SuperClasses[i] == cs) 190 return true; 191 return false; 192 } 193 194 /// superclasses_begin / superclasses_end - Loop over all of the classes 195 /// that are proper supersets of this register class. 196 sc_iterator superclasses_begin() const { 197 return SuperClasses; 198 } 199 200 sc_iterator superclasses_end() const { 201 sc_iterator I = SuperClasses; 202 while (*I != NULL) ++I; 203 return I; 204 } 205 206 /// isASubClass - return true if this TargetRegisterClass is a subset 207 /// class of at least one other TargetRegisterClass. 208 bool isASubClass() const { 209 return SuperClasses[0] != 0; 210 } 211 212 /// allocation_order_begin/end - These methods define a range of registers 213 /// which specify the registers in this class that are valid to register 214 /// allocate, and the preferred order to allocate them in. For example, 215 /// callee saved registers should be at the end of the list, because it is 216 /// cheaper to allocate caller saved registers. 217 /// 218 /// These methods take a MachineFunction argument, which can be used to tune 219 /// the allocatable registers based on the characteristics of the function. 220 /// One simple example is that the frame pointer register can be used if 221 /// frame-pointer-elimination is performed. 222 /// 223 /// By default, these methods return all registers in the class. 224 /// 225 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 226 return begin(); 227 } 228 virtual iterator allocation_order_end(const MachineFunction &MF) const { 229 return end(); 230 } 231 232 233 234 /// getSize - Return the size of the register in bytes, which is also the size 235 /// of a stack slot allocated to hold a spilled copy of this register. 236 unsigned getSize() const { return RegSize; } 237 238 /// getAlignment - Return the minimum required alignment for a register of 239 /// this class. 240 unsigned getAlignment() const { return Alignment; } 241 242 /// getCopyCost - Return the cost of copying a value between two registers in 243 /// this class. A negative number means the register class is very expensive 244 /// to copy e.g. status flag register classes. 245 int getCopyCost() const { return CopyCost; } 246}; 247 248 249/// TargetRegisterInfo base class - We assume that the target defines a static 250/// array of TargetRegisterDesc objects that represent all of the machine 251/// registers that the target has. As such, we simply have to track a pointer 252/// to this array so that we can turn register number into a register 253/// descriptor. 254/// 255class TargetRegisterInfo { 256protected: 257 const unsigned* SubregHash; 258 const unsigned SubregHashSize; 259 const unsigned* SuperregHash; 260 const unsigned SuperregHashSize; 261 const unsigned* AliasesHash; 262 const unsigned AliasesHashSize; 263public: 264 typedef const TargetRegisterClass * const * regclass_iterator; 265private: 266 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 267 unsigned NumRegs; // Number of entries in the array 268 269 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 270 271 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 272protected: 273 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 274 regclass_iterator RegClassBegin, 275 regclass_iterator RegClassEnd, 276 int CallFrameSetupOpcode = -1, 277 int CallFrameDestroyOpcode = -1, 278 const unsigned* subregs = 0, 279 const unsigned subregsize = 0, 280 const unsigned* superregs = 0, 281 const unsigned superregsize = 0, 282 const unsigned* aliases = 0, 283 const unsigned aliasessize = 0); 284 virtual ~TargetRegisterInfo(); 285public: 286 287 enum { // Define some target independent constants 288 /// NoRegister - This physical register is not a real target register. It 289 /// is useful as a sentinal. 290 NoRegister = 0, 291 292 /// FirstVirtualRegister - This is the first register number that is 293 /// considered to be a 'virtual' register, which is part of the SSA 294 /// namespace. This must be the same for all targets, which means that each 295 /// target is limited to 1024 registers. 296 FirstVirtualRegister = 1024 297 }; 298 299 /// isPhysicalRegister - Return true if the specified register number is in 300 /// the physical register namespace. 301 static bool isPhysicalRegister(unsigned Reg) { 302 assert(Reg && "this is not a register!"); 303 return Reg < FirstVirtualRegister; 304 } 305 306 /// isVirtualRegister - Return true if the specified register number is in 307 /// the virtual register namespace. 308 static bool isVirtualRegister(unsigned Reg) { 309 assert(Reg && "this is not a register!"); 310 return Reg >= FirstVirtualRegister; 311 } 312 313 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 314 /// register of the given type. If type is MVT::Other, then just return any 315 /// register class the register belongs to. 316 virtual const TargetRegisterClass * 317 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const; 318 319 /// getAllocatableSet - Returns a bitset indexed by register number 320 /// indicating if a register is allocatable or not. If a register class is 321 /// specified, returns the subset for the class. 322 BitVector getAllocatableSet(MachineFunction &MF, 323 const TargetRegisterClass *RC = NULL) const; 324 325 const TargetRegisterDesc &operator[](unsigned RegNo) const { 326 assert(RegNo < NumRegs && 327 "Attempting to access record for invalid register number!"); 328 return Desc[RegNo]; 329 } 330 331 /// Provide a get method, equivalent to [], but more useful if we have a 332 /// pointer to this object. 333 /// 334 const TargetRegisterDesc &get(unsigned RegNo) const { 335 return operator[](RegNo); 336 } 337 338 /// getAliasSet - Return the set of registers aliased by the specified 339 /// register, or a null list of there are none. The list returned is zero 340 /// terminated. 341 /// 342 const unsigned *getAliasSet(unsigned RegNo) const { 343 return get(RegNo).AliasSet; 344 } 345 346 /// getSubRegisters - Return the list of registers that are sub-registers of 347 /// the specified register, or a null list of there are none. The list 348 /// returned is zero terminated and sorted according to super-sub register 349 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 350 /// 351 const unsigned *getSubRegisters(unsigned RegNo) const { 352 return get(RegNo).SubRegs; 353 } 354 355 /// getSuperRegisters - Return the list of registers that are super-registers 356 /// of the specified register, or a null list of there are none. The list 357 /// returned is zero terminated and sorted according to super-sub register 358 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 359 /// 360 const unsigned *getSuperRegisters(unsigned RegNo) const { 361 return get(RegNo).SuperRegs; 362 } 363 364 /// getAsmName - Return the symbolic target-specific name for the 365 /// specified physical register. 366 const char *getAsmName(unsigned RegNo) const { 367 return get(RegNo).AsmName; 368 } 369 370 /// getName - Return the human-readable symbolic target-specific name for the 371 /// specified physical register. 372 const char *getName(unsigned RegNo) const { 373 return get(RegNo).Name; 374 } 375 376 /// getNumRegs - Return the number of registers this target has (useful for 377 /// sizing arrays holding per register information) 378 unsigned getNumRegs() const { 379 return NumRegs; 380 } 381 382 /// areAliases - Returns true if the two registers alias each other, false 383 /// otherwise 384 bool areAliases(unsigned regA, unsigned regB) const { 385 size_t index = (regA + regB * 37) & (AliasesHashSize-1); 386 unsigned ProbeAmt = 0; 387 while (AliasesHash[index*2] != 0 && 388 AliasesHash[index*2+1] != 0) { 389 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) 390 return true; 391 392 index = (index + ProbeAmt) & (AliasesHashSize-1); 393 ProbeAmt += 2; 394 } 395 396 return false; 397 } 398 399 /// regsOverlap - Returns true if the two registers are equal or alias each 400 /// other. The registers may be virtual register. 401 bool regsOverlap(unsigned regA, unsigned regB) const { 402 if (regA == regB) 403 return true; 404 405 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 406 return false; 407 return areAliases(regA, regB); 408 } 409 410 /// isSubRegister - Returns true if regB is a sub-register of regA. 411 /// 412 bool isSubRegister(unsigned regA, unsigned regB) const { 413 // SubregHash is a simple quadratically probed hash table. 414 size_t index = (regA + regB * 37) & (SubregHashSize-1); 415 unsigned ProbeAmt = 2; 416 while (SubregHash[index*2] != 0 && 417 SubregHash[index*2+1] != 0) { 418 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 419 return true; 420 421 index = (index + ProbeAmt) & (SubregHashSize-1); 422 ProbeAmt += 2; 423 } 424 425 return false; 426 } 427 428 /// isSuperRegister - Returns true if regB is a super-register of regA. 429 /// 430 bool isSuperRegister(unsigned regA, unsigned regB) const { 431 // SuperregHash is a simple quadratically probed hash table. 432 size_t index = (regA + regB * 37) & (SuperregHashSize-1); 433 unsigned ProbeAmt = 2; 434 while (SuperregHash[index*2] != 0 && 435 SuperregHash[index*2+1] != 0) { 436 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB) 437 return true; 438 439 index = (index + ProbeAmt) & (SuperregHashSize-1); 440 ProbeAmt += 2; 441 } 442 443 return false; 444 } 445 446 /// getCalleeSavedRegs - Return a null-terminated list of all of the 447 /// callee saved registers on this target. The register should be in the 448 /// order of desired callee-save stack frame offset. The first register is 449 /// closed to the incoming stack pointer if stack grows down, and vice versa. 450 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 451 const = 0; 452 453 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 454 /// register classes to spill each callee saved register with. The order and 455 /// length of this list match the getCalleeSaveRegs() list. 456 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( 457 const MachineFunction *MF) const =0; 458 459 /// getReservedRegs - Returns a bitset indexed by physical register number 460 /// indicating if a register is a special register that has particular uses 461 /// and should be considered unavailable at all times, e.g. SP, RA. This is 462 /// used by register scavenger to determine what registers are free. 463 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 464 465 /// getSubReg - Returns the physical register number of sub-register "Index" 466 /// for physical register RegNo. Return zero if the sub-register does not 467 /// exist. 468 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 469 470 //===--------------------------------------------------------------------===// 471 // Register Class Information 472 // 473 474 /// Register class iterators 475 /// 476 regclass_iterator regclass_begin() const { return RegClassBegin; } 477 regclass_iterator regclass_end() const { return RegClassEnd; } 478 479 unsigned getNumRegClasses() const { 480 return (unsigned)(regclass_end()-regclass_begin()); 481 } 482 483 /// getRegClass - Returns the register class associated with the enumeration 484 /// value. See class TargetOperandInfo. 485 const TargetRegisterClass *getRegClass(unsigned i) const { 486 assert(i <= getNumRegClasses() && "Register Class ID out of range"); 487 return i ? RegClassBegin[i - 1] : NULL; 488 } 489 490 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 491 /// values. 492 virtual const TargetRegisterClass *getPointerRegClass() const { 493 assert(0 && "Target didn't implement getPointerRegClass!"); 494 return 0; // Must return a value in order to compile with VS 2005 495 } 496 497 /// getCrossCopyRegClass - Returns a legal register class to copy a register 498 /// in the specified class to or from. Returns NULL if it is possible to copy 499 /// between a two registers of the specified class. 500 virtual const TargetRegisterClass * 501 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 502 return NULL; 503 } 504 505 /// targetHandlesStackFrameRounding - Returns true if the target is 506 /// responsible for rounding up the stack frame (probably at emitPrologue 507 /// time). 508 virtual bool targetHandlesStackFrameRounding() const { 509 return false; 510 } 511 512 /// requiresRegisterScavenging - returns true if the target requires (and can 513 /// make use of) the register scavenger. 514 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 515 return false; 516 } 517 518 /// hasFP - Return true if the specified function should have a dedicated 519 /// frame pointer register. For most targets this is true only if the function 520 /// has variable sized allocas or if frame pointer elimination is disabled. 521 virtual bool hasFP(const MachineFunction &MF) const = 0; 522 523 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is 524 // not required, we reserve argument space for call sites in the function 525 // immediately on entry to the current function. This eliminates the need for 526 // add/sub sp brackets around call sites. Returns true if the call frame is 527 // included as part of the stack frame. 528 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 529 return !hasFP(MF); 530 } 531 532 // needsStackRealignment - true if storage within the function requires the 533 // stack pointer to be aligned more than the normal calling convention calls 534 // for. 535 virtual bool needsStackRealignment(const MachineFunction &MF) const { 536 return false; 537 } 538 539 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 540 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 541 /// targets use pseudo instructions in order to abstract away the difference 542 /// between operating with a frame pointer and operating without, through the 543 /// use of these two instructions. 544 /// 545 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 546 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 547 548 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 549 /// code insertion to eliminate call frame setup and destroy pseudo 550 /// instructions (but only if the Target is using them). It is responsible 551 /// for eliminating these instructions, replacing them with concrete 552 /// instructions. This method need only be implemented if using call frame 553 /// setup/destroy pseudo instructions. 554 /// 555 virtual void 556 eliminateCallFramePseudoInstr(MachineFunction &MF, 557 MachineBasicBlock &MBB, 558 MachineBasicBlock::iterator MI) const { 559 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 560 "eliminateCallFramePseudoInstr must be implemented if using" 561 " call frame setup/destroy pseudo instructions!"); 562 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 563 } 564 565 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 566 /// before PrologEpilogInserter scans the physical registers used to determine 567 /// what callee saved registers should be spilled. This method is optional. 568 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 569 RegScavenger *RS = NULL) const { 570 571 } 572 573 /// processFunctionBeforeFrameFinalized - This method is called immediately 574 /// before the specified functions frame layout (MF.getFrameInfo()) is 575 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 576 /// replaced with direct constants. This method is optional. 577 /// 578 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 579 } 580 581 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 582 /// frame indices from instructions which may use them. The instruction 583 /// referenced by the iterator contains an MO_FrameIndex operand which must be 584 /// eliminated by this method. This method may modify or replace the 585 /// specified instruction, as long as it keeps the iterator pointing the the 586 /// finished product. SPAdj is the SP adjustment due to call frame setup 587 /// instruction. 588 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 589 int SPAdj, RegScavenger *RS=NULL) const = 0; 590 591 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 592 /// the function. 593 virtual void emitPrologue(MachineFunction &MF) const = 0; 594 virtual void emitEpilogue(MachineFunction &MF, 595 MachineBasicBlock &MBB) const = 0; 596 597 //===--------------------------------------------------------------------===// 598 /// Debug information queries. 599 600 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 601 /// number. Returns -1 if there is no equivalent value. The second 602 /// parameter allows targets to use different numberings for EH info and 603 /// debugging info. 604 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 605 606 /// getFrameRegister - This method should return the register used as a base 607 /// for values allocated in the current stack frame. 608 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 609 610 /// getFrameIndexOffset - Returns the displacement from the frame register to 611 /// the stack frame of the specified index. 612 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; 613 614 /// getRARegister - This method should return the register where the return 615 /// address can be found. 616 virtual unsigned getRARegister() const = 0; 617 618 /// getInitialFrameState - Returns a list of machine moves that are assumed 619 /// on entry to all functions. Note that LabelID is ignored (assumed to be 620 /// the beginning of the function.) 621 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 622}; 623 624// This is useful when building IndexedMaps keyed on virtual registers 625struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 626 unsigned operator()(unsigned Reg) const { 627 return Reg - TargetRegisterInfo::FirstVirtualRegister; 628 } 629}; 630 631} // End llvm namespace 632 633#endif 634