TargetSchedule.td revision 13745262a8db98d6c4513ff9934db4be75a8b26c
1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent scheduling interfaces which should 11// be implemented by each target which is using TableGen based scheduling. 12// 13// The SchedMachineModel is defined by subtargets for three categories of data: 14// 1. Basic properties for coarse grained instruction cost model. 15// 2. Scheduler Read/Write resources for simple per-opcode cost model. 16// 3. Instruction itineraties for detailed reservation tables. 17// 18// (1) Basic properties are defined by the SchedMachineModel 19// class. Target hooks allow subtargets to associate opcodes with 20// those properties. 21// 22// (2) A per-operand machine model can be implemented in any 23// combination of the following ways: 24// 25// A. Associate per-operand SchedReadWrite types with Instructions by 26// modifying the Instruction definition to inherit from Sched. For 27// each subtarget, define WriteRes and ReadAdvance to associate 28// processor resources and latency with each SchedReadWrite type. 29// 30// B. In each instruction definition, name an ItineraryClass. For each 31// subtarget, define ItinRW entries to map ItineraryClass to 32// per-operand SchedReadWrite types. Unlike method A, these types may 33// be subtarget specific and can be directly associated with resources 34// by defining SchedWriteRes and SchedReadAdvance. 35// 36// C. In the subtarget, map SchedReadWrite types to specific 37// opcodes. This overrides any SchedReadWrite types or 38// ItineraryClasses defined by the Instruction. As in method B, the 39// subtarget can directly associate resources with SchedReadWrite 40// types by defining SchedWriteRes and SchedReadAdvance. 41// 42// D. In either the target or subtarget, define SchedWriteVariant or 43// SchedReadVariant to map one SchedReadWrite type onto another 44// sequence of SchedReadWrite types. This allows dynamic selection of 45// an instruction's machine model via custom C++ code. It also allows 46// a machine-independent SchedReadWrite type to map to a sequence of 47// machine-dependent types. 48// 49// (3) A per-pipeline-stage machine model can be implemented by providing 50// Itineraries in addition to mapping instructions to ItineraryClasses. 51//===----------------------------------------------------------------------===// 52 53// Include legacy support for instruction itineraries. 54include "llvm/Target/TargetItinerary.td" 55 56class Instruction; // Forward def 57 58// DAG operator that interprets the DAG args as Instruction defs. 59def instrs; 60 61// DAG operator that interprets each DAG arg as a regex pattern for 62// matching Instruction opcode names. 63// The regex must match the beginning of the opcode (as in Python re.match). 64// To avoid matching prefixes, append '$' to the pattern. 65def instregex; 66 67// Define the SchedMachineModel and provide basic properties for 68// coarse grained instruction cost model. Default values for the 69// properties are defined in MCSchedModel. A value of "-1" in the 70// target description's SchedMachineModel indicates that the property 71// is not overriden by the target. 72// 73// Target hooks allow subtargets to associate LoadLatency and 74// HighLatency with groups of opcodes. 75class SchedMachineModel { 76 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. 77 int MinLatency = -1; // Determines which instrucions are allowed in a group. 78 // (-1) inorder (0) ooo, (1): inorder +var latencies. 79 int LoadLatency = -1; // Cycles for loads to access the cache. 80 int HighLatency = -1; // Approximation of cycles for "high latency" ops. 81 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. 82 83 // Per-cycle resources tables. 84 ProcessorItineraries Itineraries = NoItineraries; 85 86 bit NoModel = 0; // Special tag to indicate missing machine model. 87} 88 89def NoSchedModel : SchedMachineModel { 90 let NoModel = 1; 91} 92 93// Define a kind of processor resource that may be common across 94// similar subtargets. 95class ProcResourceKind; 96 97// Define a number of interchangeable processor resources. NumUnits 98// determines the throughput of instructions that require the resource. 99// 100// An optional Super resource may be given to model these resources as 101// a subset of the more general super resources. Using one of these 102// resources implies using one of the super resoruces. 103// 104// ProcResourceUnits normally model a few buffered resources within an 105// out-of-order engine that the compiler attempts to conserve. 106// Buffered resources may be held for multiple clock cycles, but the 107// scheduler does not pin them to a particular clock cycle relative to 108// instruction dispatch. Setting Buffered=0 changes this to an 109// in-order resource. In this case, the scheduler counts down from the 110// cycle that the instruction issues in-order, forcing an interlock 111// with subsequent instructions that require the same resource until 112// the number of ResourceCyles specified in WriteRes expire. 113// 114// SchedModel ties these units to a processor for any stand-alone defs 115// of this class. Instances of subclass ProcResource will be automatically 116// attached to a processor, so SchedModel is not needed. 117class ProcResourceUnits<ProcResourceKind kind, int num> { 118 ProcResourceKind Kind = kind; 119 int NumUnits = num; 120 ProcResourceKind Super = ?; 121 bit Buffered = 1; 122 SchedMachineModel SchedModel = ?; 123} 124 125// EponymousProcResourceKind helps implement ProcResourceUnits by 126// allowing a ProcResourceUnits definition to reference itself. It 127// should not be referenced anywhere else. 128def EponymousProcResourceKind : ProcResourceKind; 129 130// Subtargets typically define processor resource kind and number of 131// units in one place. 132class ProcResource<int num> : ProcResourceKind, 133 ProcResourceUnits<EponymousProcResourceKind, num>; 134 135// A target architecture may define SchedReadWrite types and associate 136// them with instruction operands. 137class SchedReadWrite; 138 139// List the per-operand types that map to the machine model of an 140// instruction. One SchedWrite type must be listed for each explicit 141// def operand in order. Additional SchedWrite types may optionally be 142// listed for implicit def operands. SchedRead types may optionally 143// be listed for use operands in order. The order of defs relative to 144// uses is insignificant. This way, the same SchedReadWrite list may 145// be used for multiple forms of an operation. For example, a 146// two-address instruction could have two tied operands or single 147// operand that both reads and writes a reg. In both cases we have a 148// single SchedWrite and single SchedRead in any order. 149class Sched<list<SchedReadWrite> schedrw> { 150 list<SchedReadWrite> SchedRW = schedrw; 151} 152 153// Define a scheduler resource associated with a def operand. 154class SchedWrite : SchedReadWrite; 155def NoWrite : SchedWrite; 156 157// Define a scheduler resource associated with a use operand. 158class SchedRead : SchedReadWrite; 159 160// Define a SchedWrite that is modeled as a sequence of other 161// SchedWrites with additive latency. This allows a single operand to 162// be mapped the resources composed from a set of previously defined 163// SchedWrites. 164// 165// If the final write in this sequence is a SchedWriteVariant marked 166// Variadic, then the list of prior writes are distributed across all 167// operands after resolving the predicate for the final write. 168// 169// SchedModel silences warnings but is ignored. 170class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite { 171 list<SchedWrite> Writes = writes; 172 int Repeat = rep; 173 SchedMachineModel SchedModel = ?; 174} 175 176// Define values common to WriteRes and SchedWriteRes. 177// 178// SchedModel ties these resources to a processor. 179class ProcWriteResources<list<ProcResourceKind> resources> { 180 list<ProcResourceKind> ProcResources = resources; 181 list<int> ResourceCycles = []; 182 int Latency = 1; 183 int NumMicroOps = 1; 184 bit BeginGroup = 0; 185 bit EndGroup = 0; 186 // Allow a processor to mark some scheduling classes as unsupported 187 // for stronger verification. 188 bit Unsupported = 0; 189 SchedMachineModel SchedModel = ?; 190} 191 192// Define the resources and latency of a SchedWrite. This will be used 193// directly by targets that have no itinerary classes. In this case, 194// SchedWrite is defined by the target, while WriteResources is 195// defined by the subtarget, and maps the SchedWrite to processor 196// resources. 197// 198// If a target already has itinerary classes, SchedWriteResources can 199// be used instead to define subtarget specific SchedWrites and map 200// them to processor resources in one place. Then ItinRW can map 201// itinerary classes to the subtarget's SchedWrites. 202// 203// ProcResources indicates the set of resources consumed by the write. 204// Optionally, ResourceCycles indicates the number of cycles the 205// resource is consumed. Each ResourceCycles item is paired with the 206// ProcResource item at the same position in its list. Since 207// ResourceCycles are rarely specialized, the list may be 208// incomplete. By default, resources are consumed for a single cycle, 209// regardless of latency, which models a fully pipelined processing 210// unit. A value of 0 for ResourceCycles means that the resource must 211// be available but is not consumed, which is only relevant for 212// unbuffered resources. 213// 214// By default, each SchedWrite takes one micro-op, which is counted 215// against the processor's IssueWidth limit. If an instruction can 216// write multiple registers with a single micro-op, the subtarget 217// should define one of the writes to be zero micro-ops. If a 218// subtarget requires multiple micro-ops to write a single result, it 219// should either override the write's NumMicroOps to be greater than 1 220// or require additional writes. Extra writes can be required either 221// by defining a WriteSequence, or simply listing extra writes in the 222// instruction's list of writers beyond the number of "def" 223// operands. The scheduler assumes that all micro-ops must be 224// dispatched in the same cycle. These micro-ops may be required to 225// begin or end the current dispatch group. 226class WriteRes<SchedWrite write, list<ProcResourceKind> resources> 227 : ProcWriteResources<resources> { 228 SchedWrite WriteType = write; 229} 230 231// Directly name a set of WriteResources defining a new SchedWrite 232// type at the same time. This class is unaware of its SchedModel so 233// must be referenced by InstRW or ItinRW. 234class SchedWriteRes<list<ProcResourceKind> resources> : SchedWrite, 235 ProcWriteResources<resources>; 236 237// Define values common to ReadAdvance and SchedReadAdvance. 238// 239// SchedModel ties these resources to a processor. 240class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> { 241 int Cycles = cycles; 242 list<SchedWrite> ValidWrites = writes; 243 // Allow a processor to mark some scheduling classes as unsupported 244 // for stronger verification. 245 bit Unsupported = 0; 246 SchedMachineModel SchedModel = ?; 247} 248 249// A processor may define a ReadAdvance associated with a SchedRead 250// to reduce latency of a prior write by N cycles. A negative advance 251// effectively increases latency, which may be used for cross-domain 252// stalls. 253// 254// A ReadAdvance may be associated with a list of SchedWrites 255// to implement pipeline bypass. The Writes list may be empty to 256// indicate operands that are always read this number of Cycles later 257// than a normal register read, allowing the read's parent instruction 258// to issue earlier relative to the writer. 259class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []> 260 : ProcReadAdvance<cycles, writes> { 261 SchedRead ReadType = read; 262} 263 264// Directly associate a new SchedRead type with a delay and optional 265// pipeline bypess. For use with InstRW or ItinRW. 266class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead, 267 ProcReadAdvance<cycles, writes>; 268 269// Define SchedRead defaults. Reads seldom need special treatment. 270def ReadDefault : SchedRead; 271def NoReadAdvance : SchedReadAdvance<0>; 272 273// Define shared code that will be in the same scope as all 274// SchedPredicates. Available variables are: 275// (const MachineInstr *MI, const TargetSchedModel *SchedModel) 276class PredicateProlog<code c> { 277 code Code = c; 278} 279 280// Define a predicate to determine which SchedVariant applies to a 281// particular MachineInstr. The code snippet is used as an 282// if-statement's expression. Available variables are MI, SchedModel, 283// and anything defined in a PredicateProlog. 284// 285// SchedModel silences warnings but is ignored. 286class SchedPredicate<code pred> { 287 SchedMachineModel SchedModel = ?; 288 code Predicate = pred; 289} 290def NoSchedPred : SchedPredicate<[{true}]>; 291 292// Associate a predicate with a list of SchedReadWrites. By default, 293// the selected SchedReadWrites are still associated with a single 294// operand and assumed to execute sequentially with additive 295// latency. However, if the parent SchedWriteVariant or 296// SchedReadVariant is marked "Variadic", then each Selected 297// SchedReadWrite is mapped in place to the instruction's variadic 298// operands. In this case, latency is not additive. If the current Variant 299// is already part of a Sequence, then that entire chain leading up to 300// the Variant is distributed over the variadic operands. 301class SchedVar<SchedPredicate pred, list<SchedReadWrite> selected> { 302 SchedPredicate Predicate = pred; 303 list<SchedReadWrite> Selected = selected; 304} 305 306// SchedModel silences warnings but is ignored. 307class SchedVariant<list<SchedVar> variants> { 308 list<SchedVar> Variants = variants; 309 bit Variadic = 0; 310 SchedMachineModel SchedModel = ?; 311} 312 313// A SchedWriteVariant is a single SchedWrite type that maps to a list 314// of SchedWrite types under the conditions defined by its predicates. 315// 316// A Variadic write is expanded to cover multiple "def" operands. The 317// SchedVariant's Expansion list is then interpreted as one write 318// per-operand instead of the usual sequential writes feeding a single 319// operand. 320class SchedWriteVariant<list<SchedVar> variants> : SchedWrite, 321 SchedVariant<variants> { 322} 323 324// A SchedReadVariant is a single SchedRead type that maps to a list 325// of SchedRead types under the conditions defined by its predicates. 326// 327// A Variadic write is expanded to cover multiple "readsReg" operands as 328// explained above. 329class SchedReadVariant<list<SchedVar> variants> : SchedRead, 330 SchedVariant<variants> { 331} 332 333// Map a set of opcodes to a list of SchedReadWrite types. This allows 334// the subtarget to easily override specific operations. 335// 336// SchedModel ties this opcode mapping to a processor. 337class InstRW<list<SchedReadWrite> rw, dag instrlist> { 338 list<SchedReadWrite> OperandReadWrites = rw; 339 dag Instrs = instrlist; 340 SchedMachineModel SchedModel = ?; 341} 342 343// Map a set of itinerary classes to SchedReadWrite resources. This is 344// used to bootstrap a target (e.g. ARM) when itineraries already 345// exist and changing InstrInfo is undesirable. 346// 347// SchedModel ties this ItineraryClass mapping to a processor. 348class ItinRW<list<SchedReadWrite> rw, list<InstrItinClass> iic> { 349 list<InstrItinClass> MatchedItinClasses = iic; 350 list<SchedReadWrite> OperandReadWrites = rw; 351 SchedMachineModel SchedModel = ?; 352} 353 354// Alias a target-defined SchedReadWrite to a processor specific 355// SchedReadWrite. This allows a subtarget to easily map a 356// SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or 357// SchedReadVariant. 358// 359// SchedModel will usually be provided by surrounding let statement 360// and ties this SchedAlias mapping to a processor. 361class SchedAlias<SchedReadWrite match, SchedReadWrite alias> { 362 SchedReadWrite MatchRW = match; 363 SchedReadWrite AliasRW = alias; 364 SchedMachineModel SchedModel = ?; 365} 366