TargetSchedule.td revision 391b3431e2a9049fb1a5d51b6cca1c9a86d636c1 
1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file defines the target-independent scheduling interfaces which should
11// be implemented by each target which is using TableGen based scheduling.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Processor functional unit - These values represent the function units
17// available across all chip sets for the target.  Eg., IntUnit, FPUnit, ...
18// These may be independent values for each chip set or may be shared across
19// all chip sets of the target.  Each functional unit is treated as a resource
20// during scheduling and has an affect instruction order based on availability
21// during a time interval.
22//  
23class FuncUnit;
24
25class ReservationKind<bits<1> val> {
26  int Value = val;
27}
28
29def Required : ReservationKind<0>;
30def Reserved : ReservationKind<1>;
31
32//===----------------------------------------------------------------------===//
33// Instruction stage - These values represent a non-pipelined step in
34// the execution of an instruction.  Cycles represents the number of
35// discrete time slots needed to complete the stage.  Units represent
36// the choice of functional units that can be used to complete the
37// stage.  Eg. IntUnit1, IntUnit2. NextCycles indicates how many
38// cycles should elapse from the start of this stage to the start of
39// the next stage in the itinerary.  For example:
40//
41// A stage is specified in one of two ways:
42//
43//   InstrStage<1, [FU_x, FU_y]>     - TimeInc defaults to Cycles
44//   InstrStage<1, [FU_x, FU_y], 0>  - TimeInc explicit
45//
46
47class InstrStage2<int cycles, list<FuncUnit> units,
48                  int timeinc, ReservationKind kind> {
49  int Cycles          = cycles;       // length of stage in machine cycles
50  list<FuncUnit> Units = units;       // choice of functional units
51  int TimeInc         = timeinc;      // cycles till start of next stage
52  int Kind            = kind.Value;   // kind of FU reservation
53}
54
55class InstrStage<int cycles, list<FuncUnit> units,
56                 int timeinc = -1>
57  : InstrStage2<cycles, units, timeinc, Required>;
58
59//===----------------------------------------------------------------------===//
60// Instruction itinerary - An itinerary represents a sequential series of steps
61// required to complete an instruction.  Itineraries are represented as lists of
62// instruction stages.
63//
64
65//===----------------------------------------------------------------------===//
66// Instruction itinerary classes - These values represent 'named' instruction
67// itinerary.  Using named itineraries simplifies managing groups of
68// instructions across chip sets.  An instruction uses the same itinerary class
69// across all chip sets.  Thus a new chip set can be added without modifying
70// instruction information.
71//
72class InstrItinClass;
73def NoItinerary : InstrItinClass;
74
75//===----------------------------------------------------------------------===//
76// Instruction itinerary data - These values provide a runtime map of an 
77// instruction itinerary class (name) to its itinerary data.
78//
79class InstrItinData<InstrItinClass Class, list<InstrStage2> stages,
80                    list<int> operandcycles = []> {
81  InstrItinClass TheClass = Class;
82  list<InstrStage2> Stages = stages;
83  list<int> OperandCycles = operandcycles;
84}
85
86//===----------------------------------------------------------------------===//
87// Processor itineraries - These values represent the set of all itinerary
88// classes for a given chip set.
89//
90class ProcessorItineraries<list<InstrItinData> iid> {
91  list<InstrItinData> IID = iid;
92}
93
94// NoItineraries - A marker that can be used by processors without schedule
95// info.
96def NoItineraries : ProcessorItineraries<[]>;
97
98