TargetSchedule.td revision 92649883119aaa8edd9ccf612eaaff5ccc8fcc77
1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent scheduling interfaces which should 11// be implemented by each target which is using TableGen based scheduling. 12// 13// The SchedMachineModel is defined by subtargets for three categories of data: 14// 1. Basic properties for coarse grained instruction cost model. 15// 2. Scheduler Read/Write resources for simple per-opcode cost model. 16// 3. Instruction itineraties for detailed reservation tables. 17// 18// (1) Basic properties are defined by the SchedMachineModel 19// class. Target hooks allow subtargets to associate opcodes with 20// those properties. 21// 22// (2) A per-operand machine model can be implemented in any 23// combination of the following ways: 24// 25// A. Associate per-operand SchedReadWrite types with Instructions by 26// modifying the Instruction definition to inherit from Sched. For 27// each subtarget, define WriteRes and ReadAdvance to associate 28// processor resources and latency with each SchedReadWrite type. 29// 30// B. In each instruction definition, name an ItineraryClass. For each 31// subtarget, define ItinRW entries to map ItineraryClass to 32// per-operand SchedReadWrite types. Unlike method A, these types may 33// be subtarget specific and can be directly associated with resources 34// by defining SchedWriteRes and SchedReadAdvance. 35// 36// C. In the subtarget, map SchedReadWrite types to specific 37// opcodes. This overrides any SchedReadWrite types or 38// ItineraryClasses defined by the Instruction. As in method B, the 39// subtarget can directly associate resources with SchedReadWrite 40// types by defining SchedWriteRes and SchedReadAdvance. 41// 42// D. In either the target or subtarget, define SchedWriteVariant or 43// SchedReadVariant to map one SchedReadWrite type onto another 44// sequence of SchedReadWrite types. This allows dynamic selection of 45// an instruction's machine model via custom C++ code. It also allows 46// a machine-independent SchedReadWrite type to map to a sequence of 47// machine-dependent types. 48// 49// (3) A per-pipeline-stage machine model can be implemented by providing 50// Itineraries in addition to mapping instructions to ItineraryClasses. 51//===----------------------------------------------------------------------===// 52 53// Include legacy support for instruction itineraries. 54include "llvm/Target/TargetItinerary.td" 55 56class Instruction; // Forward def 57 58// Define the SchedMachineModel and provide basic properties for 59// coarse grained instruction cost model. Default values for the 60// properties are defined in MCSchedModel. A value of "-1" in the 61// target description's SchedMachineModel indicates that the property 62// is not overriden by the target. 63// 64// Target hooks allow subtargets to associate LoadLatency and 65// HighLatency with groups of opcodes. 66class SchedMachineModel { 67 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. 68 int MinLatency = -1; // Determines which instrucions are allowed in a group. 69 // (-1) inorder (0) ooo, (1): inorder +var latencies. 70 int LoadLatency = -1; // Cycles for loads to access the cache. 71 int HighLatency = -1; // Approximation of cycles for "high latency" ops. 72 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. 73 74 // Per-cycle resources tables. 75 ProcessorItineraries Itineraries = NoItineraries; 76 77 bit NoModel = 0; // Special tag to indicate missing machine model. 78} 79 80def NoSchedModel : SchedMachineModel { 81 let NoModel = 1; 82} 83 84// Define a kind of processor resource that may be common across 85// similar subtargets. 86class ProcResourceKind; 87 88// Define a number of interchangeable processor resources. NumUnits 89// determines the throughput of instructions that require the resource. 90// 91// An optional Super resource may be given to model these resources as 92// a subset of the more general super resources. Using one of these 93// resources implies using one of the super resoruces. 94// 95// ProcResourceUnits normally model a few buffered resources within an 96// out-of-order engine that the compiler attempts to conserve. 97// Buffered resources may be held for multiple clock cycles, but the 98// scheduler does not pin them to a particular clock cycle relative to 99// instruction dispatch. Setting Buffered=0 changes this to an 100// in-order resource. In this case, the scheduler counts down from the 101// cycle that the instruction issues in-order, forcing an interlock 102// with subsequent instructions that require the same resource until 103// the number of ResourceCyles specified in WriteRes expire. 104// 105// SchedModel ties these units to a processor for any stand-alone defs 106// of this class. Instances of subclass ProcResource will be automatically 107// attached to a processor, so SchedModel is not needed. 108class ProcResourceUnits<ProcResourceKind kind, int num> { 109 ProcResourceKind Kind = kind; 110 int NumUnits = num; 111 ProcResourceKind Super = ?; 112 bit Buffered = 1; 113 SchedMachineModel SchedModel = ?; 114} 115 116// EponymousProcResourceKind helps implement ProcResourceUnits by 117// allowing a ProcResourceUnits definition to reference itself. It 118// should not be referenced anywhere else. 119def EponymousProcResourceKind : ProcResourceKind; 120 121// Subtargets typically define processor resource kind and number of 122// units in one place. 123class ProcResource<int num> : ProcResourceKind, 124 ProcResourceUnits<EponymousProcResourceKind, num>; 125 126// A target architecture may define SchedReadWrite types and associate 127// them with instruction operands. 128class SchedReadWrite; 129 130// List the per-operand types that map to the machine model of an 131// instruction. One SchedWrite type must be listed for each explicit 132// def operand in order. Additional SchedWrite types may optionally be 133// listed for implicit def operands. SchedRead types may optionally 134// be listed for use operands in order. The order of defs relative to 135// uses is insignificant. This way, the same SchedReadWrite list may 136// be used for multiple forms of an operation. For example, a 137// two-address instruction could have two tied operands or single 138// operand that both reads and writes a reg. In both cases we have a 139// single SchedWrite and single SchedRead in any order. 140class Sched<list<SchedReadWrite> schedrw> { 141 list<SchedReadWrite> SchedRW = schedrw; 142} 143 144// Define a scheduler resource associated with a def operand. 145class SchedWrite : SchedReadWrite; 146def NoWrite : SchedWrite; 147 148// Define a scheduler resource associated with a use operand. 149class SchedRead : SchedReadWrite; 150 151// Define a SchedWrite that is modeled as a sequence of other 152// SchedWrites with additive latency. This allows a single operand to 153// be mapped the resources composed from a set of previously defined 154// SchedWrites. 155// 156// If the final write in this sequence is a SchedWriteVariant marked 157// Variadic, then the list of prior writes are distributed across all 158// operands after resolving the predicate for the final write. 159// 160// SchedModel silences warnings but is ignored. 161class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite { 162 list<SchedWrite> Writes = writes; 163 int Repeat = rep; 164 SchedMachineModel SchedModel = ?; 165} 166 167// Define values common to WriteRes and SchedWriteRes. 168// 169// SchedModel ties these resources to a processor. 170class ProcWriteResources<list<ProcResourceKind> resources> { 171 list<ProcResourceKind> ProcResources = resources; 172 list<int> ResourceCycles = []; 173 int Latency = 1; 174 int NumMicroOps = 1; 175 bit BeginGroup = 0; 176 bit EndGroup = 0; 177 // Allow a processor to mark some scheduling classes as unsupported 178 // for stronger verification. 179 bit Unsupported = 0; 180 SchedMachineModel SchedModel = ?; 181} 182 183// Define the resources and latency of a SchedWrite. This will be used 184// directly by targets that have no itinerary classes. In this case, 185// SchedWrite is defined by the target, while WriteResources is 186// defined by the subtarget, and maps the SchedWrite to processor 187// resources. 188// 189// If a target already has itinerary classes, SchedWriteResources can 190// be used instead to define subtarget specific SchedWrites and map 191// them to processor resources in one place. Then ItinRW can map 192// itinerary classes to the subtarget's SchedWrites. 193// 194// ProcResources indicates the set of resources consumed by the write. 195// Optionally, ResourceCycles indicates the number of cycles the 196// resource is consumed. Each ResourceCycles item is paired with the 197// ProcResource item at the same position in its list. Since 198// ResourceCycles are rarely specialized, the list may be 199// incomplete. By default, resources are consumed for a single cycle, 200// regardless of latency, which models a fully pipelined processing 201// unit. A value of 0 for ResourceCycles means that the resource must 202// be available but is not consumed, which is only relevant for 203// unbuffered resources. 204// 205// By default, each SchedWrite takes one micro-op, which is counted 206// against the processor's IssueWidth limit. If an instruction can 207// write multiple registers with a single micro-op, the subtarget 208// should define one of the writes to be zero micro-ops. If a 209// subtarget requires multiple micro-ops to write a single result, it 210// should either override the write's NumMicroOps to be greater than 1 211// or require additional writes. Extra writes can be required either 212// by defining a WriteSequence, or simply listing extra writes in the 213// instruction's list of writers beyond the number of "def" 214// operands. The scheduler assumes that all micro-ops must be 215// dispatched in the same cycle. These micro-ops may be required to 216// begin or end the current dispatch group. 217class WriteRes<SchedWrite write, list<ProcResourceKind> resources> 218 : ProcWriteResources<resources> { 219 SchedWrite WriteType = write; 220} 221 222// Directly name a set of WriteResources defining a new SchedWrite 223// type at the same time. This class is unaware of its SchedModel so 224// must be referenced by InstRW or ItinRW. 225class SchedWriteRes<list<ProcResourceKind> resources> : SchedWrite, 226 ProcWriteResources<resources>; 227 228// Define values common to ReadAdvance and SchedReadAdvance. 229// 230// SchedModel ties these resources to a processor. 231class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> { 232 int Cycles = cycles; 233 list<SchedWrite> ValidWrites = writes; 234 // Allow a processor to mark some scheduling classes as unsupported 235 // for stronger verification. 236 bit Unsupported = 0; 237 SchedMachineModel SchedModel = ?; 238} 239 240// A processor may define a ReadAdvance associated with a SchedRead 241// to reduce latency of a prior write by N cycles. A negative advance 242// effectively increases latency, which may be used for cross-domain 243// stalls. 244// 245// A ReadAdvance may be associated with a list of SchedWrites 246// to implement pipeline bypass. The Writes list may be empty to 247// indicate operands that are always read this number of Cycles later 248// than a normal register read, allowing the read's parent instruction 249// to issue earlier relative to the writer. 250class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []> 251 : ProcReadAdvance<cycles, writes> { 252 SchedRead ReadType = read; 253} 254 255// Directly associate a new SchedRead type with a delay and optional 256// pipeline bypess. For use with InstRW or ItinRW. 257class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead, 258 ProcReadAdvance<cycles, writes>; 259 260// Define SchedRead defaults. Reads seldom need special treatment. 261def ReadDefault : SchedRead; 262def NoReadAdvance : SchedReadAdvance<0>; 263 264// Define shared code that will be in the same scope as all 265// SchedPredicates. Available variables are: 266// (const MachineInstr *MI, const TargetSchedModel *SchedModel) 267class PredicateProlog<code c> { 268 code Code = c; 269} 270 271// Define a predicate to determine which SchedVariant applies to a 272// particular MachineInstr. The code snippet is used as an 273// if-statement's expression. Available variables are MI, SchedModel, 274// and anything defined in a PredicateProlog. 275// 276// SchedModel silences warnings but is ignored. 277class SchedPredicate<code pred> { 278 SchedMachineModel SchedModel = ?; 279 code Predicate = pred; 280} 281def NoSchedPred : SchedPredicate<[{true}]>; 282 283// Associate a predicate with a list of SchedReadWrites. By default, 284// the selected SchedReadWrites are still associated with a single 285// operand and assumed to execute sequentially with additive 286// latency. However, if the parent SchedWriteVariant or 287// SchedReadVariant is marked "Variadic", then each Selected 288// SchedReadWrite is mapped in place to the instruction's variadic 289// operands. In this case, latency is not additive. If the current Variant 290// is already part of a Sequence, then that entire chain leading up to 291// the Variant is distributed over the variadic operands. 292class SchedVar<SchedPredicate pred, list<SchedReadWrite> selected> { 293 SchedPredicate Predicate = pred; 294 list<SchedReadWrite> Selected = selected; 295} 296 297// SchedModel silences warnings but is ignored. 298class SchedVariant<list<SchedVar> variants> { 299 list<SchedVar> Variants = variants; 300 bit Variadic = 0; 301 SchedMachineModel SchedModel = ?; 302} 303 304// A SchedWriteVariant is a single SchedWrite type that maps to a list 305// of SchedWrite types under the conditions defined by its predicates. 306// 307// A Variadic write is expanded to cover multiple "def" operands. The 308// SchedVariant's Expansion list is then interpreted as one write 309// per-operand instead of the usual sequential writes feeding a single 310// operand. 311class SchedWriteVariant<list<SchedVar> variants> : SchedWrite, 312 SchedVariant<variants> { 313} 314 315// A SchedReadVariant is a single SchedRead type that maps to a list 316// of SchedRead types under the conditions defined by its predicates. 317// 318// A Variadic write is expanded to cover multiple "readsReg" operands as 319// explained above. 320class SchedReadVariant<list<SchedVar> variants> : SchedRead, 321 SchedVariant<variants> { 322} 323 324// Map a set of opcodes to a list of SchedReadWrite types. This allows 325// the subtarget to easily override specific operations. 326// 327// SchedModel ties this opcode mapping to a processor. 328class InstRW<list<SchedReadWrite> rw, list<Instruction> instrs> { 329 list<SchedReadWrite> OperandReadWrites = rw; 330 list<Instruction> Instrs = instrs; 331 SchedMachineModel SchedModel = ?; 332} 333 334// Map a set of itinerary classes to SchedReadWrite resources. This is 335// used to bootstrap a target (e.g. ARM) when itineraries already 336// exist and changing InstrInfo is undesirable. 337// 338// SchedModel ties this ItineraryClass mapping to a processor. 339class ItinRW<list<SchedReadWrite> rw, list<InstrItinClass> iic> { 340 list<InstrItinClass> MatchedItinClasses = iic; 341 list<SchedReadWrite> OperandReadWrites = rw; 342 SchedMachineModel SchedModel = ?; 343} 344 345// Alias a target-defined SchedReadWrite to a processor specific 346// SchedReadWrite. This allows a subtarget to easily map a 347// SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or 348// SchedReadVariant. 349// 350// SchedModel will usually be provided by surrounding let statement 351// and ties this SchedAlias mapping to a processor. 352class SchedAlias<SchedReadWrite match, SchedReadWrite alias> { 353 SchedReadWrite MatchRW = match; 354 SchedReadWrite AliasRW = alias; 355 SchedMachineModel SchedModel = ?; 356} 357