TargetSchedule.td revision b86a0cdb674549d8493043331cecd9cbf53b80da
1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent scheduling interfaces which should 11// be implemented by each target which is using TableGen based scheduling. 12// 13// The SchedMachineModel is defined by subtargets for three categories of data: 14// 1. Basic properties for coarse grained instruction cost model. 15// 2. Scheduler Read/Write resources for simple per-opcode cost model. 16// 3. Instruction itineraties for detailed reservation tables. 17// 18// (1) Basic properties are defined by the SchedMachineModel 19// class. Target hooks allow subtargets to associate opcodes with 20// those properties. 21// 22// (2) A per-operand machine model can be implemented in any 23// combination of the following ways: 24// 25// A. Associate per-operand SchedReadWrite types with Instructions by 26// modifying the Instruction definition to inherit from Sched. For 27// each subtarget, define WriteRes and ReadAdvance to associate 28// processor resources and latency with each SchedReadWrite type. 29// 30// B. In each instruction definition, name an ItineraryClass. For each 31// subtarget, define ItinRW entries to map ItineraryClass to 32// per-operand SchedReadWrite types. Unlike method A, these types may 33// be subtarget specific and can be directly associated with resources 34// by defining SchedWriteRes and SchedReadAdvance. 35// 36// C. In the subtarget, map SchedReadWrite types to specific 37// opcodes. This overrides any SchedReadWrite types or 38// ItineraryClasses defined by the Instruction. As in method B, the 39// subtarget can directly associate resources with SchedReadWrite 40// types by defining SchedWriteRes and SchedReadAdvance. 41// 42// D. In either the target or subtarget, define SchedWriteVariant or 43// SchedReadVariant to map one SchedReadWrite type onto another 44// sequence of SchedReadWrite types. This allows dynamic selection of 45// an instruction's machine model via custom C++ code. It also allows 46// a machine-independent SchedReadWrite type to map to a sequence of 47// machine-dependent types. 48// 49// (3) A per-pipeline-stage machine model can be implemented by providing 50// Itineraries in addition to mapping instructions to ItineraryClasses. 51//===----------------------------------------------------------------------===// 52 53// Include legacy support for instruction itineraries. 54include "llvm/Target/TargetItinerary.td" 55 56class Instruction; // Forward def 57 58// DAG operator that interprets the DAG args as Instruction defs. 59def instrs; 60 61// DAG operator that interprets each DAG arg as a regex pattern for 62// matching Instruction opcode names. 63// The regex must match the beginning of the opcode (as in Python re.match). 64// To avoid matching prefixes, append '$' to the pattern. 65def instregex; 66 67// Define the SchedMachineModel and provide basic properties for 68// coarse grained instruction cost model. Default values for the 69// properties are defined in MCSchedModel. A value of "-1" in the 70// target description's SchedMachineModel indicates that the property 71// is not overriden by the target. 72// 73// Target hooks allow subtargets to associate LoadLatency and 74// HighLatency with groups of opcodes. 75// 76// See MCSchedule.h for detailed comments. 77class SchedMachineModel { 78 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. 79 int MinLatency = -1; // Determines which instrucions are allowed in a group. 80 // (-1) inorder (0) ooo, (1): inorder +var latencies. 81 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered. 82 int LoadLatency = -1; // Cycles for loads to access the cache. 83 int HighLatency = -1; // Approximation of cycles for "high latency" ops. 84 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. 85 86 // Per-cycle resources tables. 87 ProcessorItineraries Itineraries = NoItineraries; 88 89 bit NoModel = 0; // Special tag to indicate missing machine model. 90} 91 92def NoSchedModel : SchedMachineModel { 93 let NoModel = 1; 94} 95 96// Define a kind of processor resource that may be common across 97// similar subtargets. 98class ProcResourceKind; 99 100// Define a number of interchangeable processor resources. NumUnits 101// determines the throughput of instructions that require the resource. 102// 103// An optional Super resource may be given to model these resources as 104// a subset of the more general super resources. Using one of these 105// resources implies using one of the super resoruces. 106// 107// ProcResourceUnits normally model a few buffered resources within an 108// out-of-order engine that the compiler attempts to conserve. 109// Buffered resources may be held for multiple clock cycles, but the 110// scheduler does not pin them to a particular clock cycle relative to 111// instruction dispatch. Setting BufferSize=0 changes this to an 112// in-order resource. In this case, the scheduler counts down from the 113// cycle that the instruction issues in-order, forcing an interlock 114// with subsequent instructions that require the same resource until 115// the number of ResourceCyles specified in WriteRes expire. 116// 117// SchedModel ties these units to a processor for any stand-alone defs 118// of this class. Instances of subclass ProcResource will be automatically 119// attached to a processor, so SchedModel is not needed. 120class ProcResourceUnits<ProcResourceKind kind, int num> { 121 ProcResourceKind Kind = kind; 122 int NumUnits = num; 123 ProcResourceKind Super = ?; 124 int BufferSize = -1; 125 SchedMachineModel SchedModel = ?; 126} 127 128// EponymousProcResourceKind helps implement ProcResourceUnits by 129// allowing a ProcResourceUnits definition to reference itself. It 130// should not be referenced anywhere else. 131def EponymousProcResourceKind : ProcResourceKind; 132 133// Subtargets typically define processor resource kind and number of 134// units in one place. 135class ProcResource<int num> : ProcResourceKind, 136 ProcResourceUnits<EponymousProcResourceKind, num>; 137 138class ProcResGroup<list<ProcResource> resources> : ProcResourceKind { 139 list<ProcResource> Resources = resources; 140 SchedMachineModel SchedModel = ?; 141} 142 143// A target architecture may define SchedReadWrite types and associate 144// them with instruction operands. 145class SchedReadWrite; 146 147// List the per-operand types that map to the machine model of an 148// instruction. One SchedWrite type must be listed for each explicit 149// def operand in order. Additional SchedWrite types may optionally be 150// listed for implicit def operands. SchedRead types may optionally 151// be listed for use operands in order. The order of defs relative to 152// uses is insignificant. This way, the same SchedReadWrite list may 153// be used for multiple forms of an operation. For example, a 154// two-address instruction could have two tied operands or single 155// operand that both reads and writes a reg. In both cases we have a 156// single SchedWrite and single SchedRead in any order. 157class Sched<list<SchedReadWrite> schedrw> { 158 list<SchedReadWrite> SchedRW = schedrw; 159} 160 161// Define a scheduler resource associated with a def operand. 162class SchedWrite : SchedReadWrite; 163def NoWrite : SchedWrite; 164 165// Define a scheduler resource associated with a use operand. 166class SchedRead : SchedReadWrite; 167 168// Define a SchedWrite that is modeled as a sequence of other 169// SchedWrites with additive latency. This allows a single operand to 170// be mapped the resources composed from a set of previously defined 171// SchedWrites. 172// 173// If the final write in this sequence is a SchedWriteVariant marked 174// Variadic, then the list of prior writes are distributed across all 175// operands after resolving the predicate for the final write. 176// 177// SchedModel silences warnings but is ignored. 178class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite { 179 list<SchedWrite> Writes = writes; 180 int Repeat = rep; 181 SchedMachineModel SchedModel = ?; 182} 183 184// Define values common to WriteRes and SchedWriteRes. 185// 186// SchedModel ties these resources to a processor. 187class ProcWriteResources<list<ProcResourceKind> resources> { 188 list<ProcResourceKind> ProcResources = resources; 189 list<int> ResourceCycles = []; 190 int Latency = 1; 191 int NumMicroOps = 1; 192 bit BeginGroup = 0; 193 bit EndGroup = 0; 194 // Allow a processor to mark some scheduling classes as unsupported 195 // for stronger verification. 196 bit Unsupported = 0; 197 SchedMachineModel SchedModel = ?; 198} 199 200// Define the resources and latency of a SchedWrite. This will be used 201// directly by targets that have no itinerary classes. In this case, 202// SchedWrite is defined by the target, while WriteResources is 203// defined by the subtarget, and maps the SchedWrite to processor 204// resources. 205// 206// If a target already has itinerary classes, SchedWriteResources can 207// be used instead to define subtarget specific SchedWrites and map 208// them to processor resources in one place. Then ItinRW can map 209// itinerary classes to the subtarget's SchedWrites. 210// 211// ProcResources indicates the set of resources consumed by the write. 212// Optionally, ResourceCycles indicates the number of cycles the 213// resource is consumed. Each ResourceCycles item is paired with the 214// ProcResource item at the same position in its list. Since 215// ResourceCycles are rarely specialized, the list may be 216// incomplete. By default, resources are consumed for a single cycle, 217// regardless of latency, which models a fully pipelined processing 218// unit. A value of 0 for ResourceCycles means that the resource must 219// be available but is not consumed, which is only relevant for 220// unbuffered resources. 221// 222// By default, each SchedWrite takes one micro-op, which is counted 223// against the processor's IssueWidth limit. If an instruction can 224// write multiple registers with a single micro-op, the subtarget 225// should define one of the writes to be zero micro-ops. If a 226// subtarget requires multiple micro-ops to write a single result, it 227// should either override the write's NumMicroOps to be greater than 1 228// or require additional writes. Extra writes can be required either 229// by defining a WriteSequence, or simply listing extra writes in the 230// instruction's list of writers beyond the number of "def" 231// operands. The scheduler assumes that all micro-ops must be 232// dispatched in the same cycle. These micro-ops may be required to 233// begin or end the current dispatch group. 234class WriteRes<SchedWrite write, list<ProcResourceKind> resources> 235 : ProcWriteResources<resources> { 236 SchedWrite WriteType = write; 237} 238 239// Directly name a set of WriteResources defining a new SchedWrite 240// type at the same time. This class is unaware of its SchedModel so 241// must be referenced by InstRW or ItinRW. 242class SchedWriteRes<list<ProcResourceKind> resources> : SchedWrite, 243 ProcWriteResources<resources>; 244 245// Define values common to ReadAdvance and SchedReadAdvance. 246// 247// SchedModel ties these resources to a processor. 248class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> { 249 int Cycles = cycles; 250 list<SchedWrite> ValidWrites = writes; 251 // Allow a processor to mark some scheduling classes as unsupported 252 // for stronger verification. 253 bit Unsupported = 0; 254 SchedMachineModel SchedModel = ?; 255} 256 257// A processor may define a ReadAdvance associated with a SchedRead 258// to reduce latency of a prior write by N cycles. A negative advance 259// effectively increases latency, which may be used for cross-domain 260// stalls. 261// 262// A ReadAdvance may be associated with a list of SchedWrites 263// to implement pipeline bypass. The Writes list may be empty to 264// indicate operands that are always read this number of Cycles later 265// than a normal register read, allowing the read's parent instruction 266// to issue earlier relative to the writer. 267class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []> 268 : ProcReadAdvance<cycles, writes> { 269 SchedRead ReadType = read; 270} 271 272// Directly associate a new SchedRead type with a delay and optional 273// pipeline bypess. For use with InstRW or ItinRW. 274class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead, 275 ProcReadAdvance<cycles, writes>; 276 277// Define SchedRead defaults. Reads seldom need special treatment. 278def ReadDefault : SchedRead; 279def NoReadAdvance : SchedReadAdvance<0>; 280 281// Define shared code that will be in the same scope as all 282// SchedPredicates. Available variables are: 283// (const MachineInstr *MI, const TargetSchedModel *SchedModel) 284class PredicateProlog<code c> { 285 code Code = c; 286} 287 288// Define a predicate to determine which SchedVariant applies to a 289// particular MachineInstr. The code snippet is used as an 290// if-statement's expression. Available variables are MI, SchedModel, 291// and anything defined in a PredicateProlog. 292// 293// SchedModel silences warnings but is ignored. 294class SchedPredicate<code pred> { 295 SchedMachineModel SchedModel = ?; 296 code Predicate = pred; 297} 298def NoSchedPred : SchedPredicate<[{true}]>; 299 300// Associate a predicate with a list of SchedReadWrites. By default, 301// the selected SchedReadWrites are still associated with a single 302// operand and assumed to execute sequentially with additive 303// latency. However, if the parent SchedWriteVariant or 304// SchedReadVariant is marked "Variadic", then each Selected 305// SchedReadWrite is mapped in place to the instruction's variadic 306// operands. In this case, latency is not additive. If the current Variant 307// is already part of a Sequence, then that entire chain leading up to 308// the Variant is distributed over the variadic operands. 309class SchedVar<SchedPredicate pred, list<SchedReadWrite> selected> { 310 SchedPredicate Predicate = pred; 311 list<SchedReadWrite> Selected = selected; 312} 313 314// SchedModel silences warnings but is ignored. 315class SchedVariant<list<SchedVar> variants> { 316 list<SchedVar> Variants = variants; 317 bit Variadic = 0; 318 SchedMachineModel SchedModel = ?; 319} 320 321// A SchedWriteVariant is a single SchedWrite type that maps to a list 322// of SchedWrite types under the conditions defined by its predicates. 323// 324// A Variadic write is expanded to cover multiple "def" operands. The 325// SchedVariant's Expansion list is then interpreted as one write 326// per-operand instead of the usual sequential writes feeding a single 327// operand. 328class SchedWriteVariant<list<SchedVar> variants> : SchedWrite, 329 SchedVariant<variants> { 330} 331 332// A SchedReadVariant is a single SchedRead type that maps to a list 333// of SchedRead types under the conditions defined by its predicates. 334// 335// A Variadic write is expanded to cover multiple "readsReg" operands as 336// explained above. 337class SchedReadVariant<list<SchedVar> variants> : SchedRead, 338 SchedVariant<variants> { 339} 340 341// Map a set of opcodes to a list of SchedReadWrite types. This allows 342// the subtarget to easily override specific operations. 343// 344// SchedModel ties this opcode mapping to a processor. 345class InstRW<list<SchedReadWrite> rw, dag instrlist> { 346 list<SchedReadWrite> OperandReadWrites = rw; 347 dag Instrs = instrlist; 348 SchedMachineModel SchedModel = ?; 349} 350 351// Map a set of itinerary classes to SchedReadWrite resources. This is 352// used to bootstrap a target (e.g. ARM) when itineraries already 353// exist and changing InstrInfo is undesirable. 354// 355// SchedModel ties this ItineraryClass mapping to a processor. 356class ItinRW<list<SchedReadWrite> rw, list<InstrItinClass> iic> { 357 list<InstrItinClass> MatchedItinClasses = iic; 358 list<SchedReadWrite> OperandReadWrites = rw; 359 SchedMachineModel SchedModel = ?; 360} 361 362// Alias a target-defined SchedReadWrite to a processor specific 363// SchedReadWrite. This allows a subtarget to easily map a 364// SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or 365// SchedReadVariant. 366// 367// SchedModel will usually be provided by surrounding let statement 368// and ties this SchedAlias mapping to a processor. 369class SchedAlias<SchedReadWrite match, SchedReadWrite alias> { 370 SchedReadWrite MatchRW = match; 371 SchedReadWrite AliasRW = alias; 372 SchedMachineModel SchedModel = ?; 373} 374