TargetSchedule.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent scheduling interfaces which should 11// be implemented by each target which is using TableGen based scheduling. 12// 13// The SchedMachineModel is defined by subtargets for three categories of data: 14// 1. Basic properties for coarse grained instruction cost model. 15// 2. Scheduler Read/Write resources for simple per-opcode cost model. 16// 3. Instruction itineraties for detailed reservation tables. 17// 18// (1) Basic properties are defined by the SchedMachineModel 19// class. Target hooks allow subtargets to associate opcodes with 20// those properties. 21// 22// (2) A per-operand machine model can be implemented in any 23// combination of the following ways: 24// 25// A. Associate per-operand SchedReadWrite types with Instructions by 26// modifying the Instruction definition to inherit from Sched. For 27// each subtarget, define WriteRes and ReadAdvance to associate 28// processor resources and latency with each SchedReadWrite type. 29// 30// B. In each instruction definition, name an ItineraryClass. For each 31// subtarget, define ItinRW entries to map ItineraryClass to 32// per-operand SchedReadWrite types. Unlike method A, these types may 33// be subtarget specific and can be directly associated with resources 34// by defining SchedWriteRes and SchedReadAdvance. 35// 36// C. In the subtarget, map SchedReadWrite types to specific 37// opcodes. This overrides any SchedReadWrite types or 38// ItineraryClasses defined by the Instruction. As in method B, the 39// subtarget can directly associate resources with SchedReadWrite 40// types by defining SchedWriteRes and SchedReadAdvance. 41// 42// D. In either the target or subtarget, define SchedWriteVariant or 43// SchedReadVariant to map one SchedReadWrite type onto another 44// sequence of SchedReadWrite types. This allows dynamic selection of 45// an instruction's machine model via custom C++ code. It also allows 46// a machine-independent SchedReadWrite type to map to a sequence of 47// machine-dependent types. 48// 49// (3) A per-pipeline-stage machine model can be implemented by providing 50// Itineraries in addition to mapping instructions to ItineraryClasses. 51//===----------------------------------------------------------------------===// 52 53// Include legacy support for instruction itineraries. 54include "llvm/Target/TargetItinerary.td" 55 56class Instruction; // Forward def 57 58// DAG operator that interprets the DAG args as Instruction defs. 59def instrs; 60 61// DAG operator that interprets each DAG arg as a regex pattern for 62// matching Instruction opcode names. 63// The regex must match the beginning of the opcode (as in Python re.match). 64// To avoid matching prefixes, append '$' to the pattern. 65def instregex; 66 67// Define the SchedMachineModel and provide basic properties for 68// coarse grained instruction cost model. Default values for the 69// properties are defined in MCSchedModel. A value of "-1" in the 70// target description's SchedMachineModel indicates that the property 71// is not overriden by the target. 72// 73// Target hooks allow subtargets to associate LoadLatency and 74// HighLatency with groups of opcodes. 75// 76// See MCSchedule.h for detailed comments. 77class SchedMachineModel { 78 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. 79 int MinLatency = -1; // Determines which instructions are allowed in a group. 80 // (-1) inorder (0) ooo, (1): inorder +var latencies. 81 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered. 82 int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for 83 // optimized loop dispatch/execution. 84 int LoadLatency = -1; // Cycles for loads to access the cache. 85 int HighLatency = -1; // Approximation of cycles for "high latency" ops. 86 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. 87 88 // Per-cycle resources tables. 89 ProcessorItineraries Itineraries = NoItineraries; 90 91 // Subtargets that define a model for only a subset of instructions 92 // that have a scheduling class (itinerary class or SchedRW list) 93 // and may actually be generated for that subtarget must clear this 94 // bit. Otherwise, the scheduler considers an unmodelled opcode to 95 // be an error. This should only be set during initial bringup, 96 // or there will be no way to catch simple errors in the model 97 // resulting from changes to the instruction definitions. 98 bit CompleteModel = 1; 99 100 bit NoModel = 0; // Special tag to indicate missing machine model. 101} 102 103def NoSchedModel : SchedMachineModel { 104 let NoModel = 1; 105} 106 107// Define a kind of processor resource that may be common across 108// similar subtargets. 109class ProcResourceKind; 110 111// Define a number of interchangeable processor resources. NumUnits 112// determines the throughput of instructions that require the resource. 113// 114// An optional Super resource may be given to model these resources as 115// a subset of the more general super resources. Using one of these 116// resources implies using one of the super resoruces. 117// 118// ProcResourceUnits normally model a few buffered resources within an 119// out-of-order engine. Buffered resources may be held for multiple 120// clock cycles, but the scheduler does not pin them to a particular 121// clock cycle relative to instruction dispatch. Setting BufferSize=0 122// changes this to an in-order issue/dispatch resource. In this case, 123// the scheduler counts down from the cycle that the instruction 124// issues in-order, forcing a stall whenever a subsequent instruction 125// requires the same resource until the number of ResourceCyles 126// specified in WriteRes expire. Setting BufferSize=1 changes this to 127// an in-order latency resource. In this case, the scheduler models 128// producer/consumer stalls between instructions that use the 129// resource. 130// 131// Examples (all assume an out-of-order engine): 132// 133// Use BufferSize = -1 for "issue ports" fed by a unified reservation 134// station. Here the size of the reservation station is modeled by 135// MicroOpBufferSize, which should be the minimum size of either the 136// register rename pool, unified reservation station, or reorder 137// buffer. 138// 139// Use BufferSize = 0 for resources that force "dispatch/issue 140// groups". (Different processors define dispath/issue 141// differently. Here we refer to stage between decoding into micro-ops 142// and moving them into a reservation station.) Normally NumMicroOps 143// is sufficient to limit dispatch/issue groups. However, some 144// processors can form groups of with only certain combinitions of 145// instruction types. e.g. POWER7. 146// 147// Use BufferSize = 1 for in-order execution units. This is used for 148// an in-order pipeline within an out-of-order core where scheduling 149// dependent operations back-to-back is guaranteed to cause a 150// bubble. e.g. Cortex-a9 floating-point. 151// 152// Use BufferSize > 1 for out-of-order executions units with a 153// separate reservation station. This simply models the size of the 154// reservation station. 155// 156// To model both dispatch/issue groups and in-order execution units, 157// create two types of units, one with BufferSize=0 and one with 158// BufferSize=1. 159// 160// SchedModel ties these units to a processor for any stand-alone defs 161// of this class. Instances of subclass ProcResource will be automatically 162// attached to a processor, so SchedModel is not needed. 163class ProcResourceUnits<ProcResourceKind kind, int num> { 164 ProcResourceKind Kind = kind; 165 int NumUnits = num; 166 ProcResourceKind Super = ?; 167 int BufferSize = -1; 168 SchedMachineModel SchedModel = ?; 169} 170 171// EponymousProcResourceKind helps implement ProcResourceUnits by 172// allowing a ProcResourceUnits definition to reference itself. It 173// should not be referenced anywhere else. 174def EponymousProcResourceKind : ProcResourceKind; 175 176// Subtargets typically define processor resource kind and number of 177// units in one place. 178class ProcResource<int num> : ProcResourceKind, 179 ProcResourceUnits<EponymousProcResourceKind, num>; 180 181class ProcResGroup<list<ProcResource> resources> : ProcResourceKind { 182 list<ProcResource> Resources = resources; 183 SchedMachineModel SchedModel = ?; 184 int BufferSize = -1; 185} 186 187// A target architecture may define SchedReadWrite types and associate 188// them with instruction operands. 189class SchedReadWrite; 190 191// List the per-operand types that map to the machine model of an 192// instruction. One SchedWrite type must be listed for each explicit 193// def operand in order. Additional SchedWrite types may optionally be 194// listed for implicit def operands. SchedRead types may optionally 195// be listed for use operands in order. The order of defs relative to 196// uses is insignificant. This way, the same SchedReadWrite list may 197// be used for multiple forms of an operation. For example, a 198// two-address instruction could have two tied operands or single 199// operand that both reads and writes a reg. In both cases we have a 200// single SchedWrite and single SchedRead in any order. 201class Sched<list<SchedReadWrite> schedrw> { 202 list<SchedReadWrite> SchedRW = schedrw; 203} 204 205// Define a scheduler resource associated with a def operand. 206class SchedWrite : SchedReadWrite; 207def NoWrite : SchedWrite; 208 209// Define a scheduler resource associated with a use operand. 210class SchedRead : SchedReadWrite; 211 212// Define a SchedWrite that is modeled as a sequence of other 213// SchedWrites with additive latency. This allows a single operand to 214// be mapped the resources composed from a set of previously defined 215// SchedWrites. 216// 217// If the final write in this sequence is a SchedWriteVariant marked 218// Variadic, then the list of prior writes are distributed across all 219// operands after resolving the predicate for the final write. 220// 221// SchedModel silences warnings but is ignored. 222class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite { 223 list<SchedWrite> Writes = writes; 224 int Repeat = rep; 225 SchedMachineModel SchedModel = ?; 226} 227 228// Define values common to WriteRes and SchedWriteRes. 229// 230// SchedModel ties these resources to a processor. 231class ProcWriteResources<list<ProcResourceKind> resources> { 232 list<ProcResourceKind> ProcResources = resources; 233 list<int> ResourceCycles = []; 234 int Latency = 1; 235 int NumMicroOps = 1; 236 bit BeginGroup = 0; 237 bit EndGroup = 0; 238 // Allow a processor to mark some scheduling classes as unsupported 239 // for stronger verification. 240 bit Unsupported = 0; 241 SchedMachineModel SchedModel = ?; 242} 243 244// Define the resources and latency of a SchedWrite. This will be used 245// directly by targets that have no itinerary classes. In this case, 246// SchedWrite is defined by the target, while WriteResources is 247// defined by the subtarget, and maps the SchedWrite to processor 248// resources. 249// 250// If a target already has itinerary classes, SchedWriteResources can 251// be used instead to define subtarget specific SchedWrites and map 252// them to processor resources in one place. Then ItinRW can map 253// itinerary classes to the subtarget's SchedWrites. 254// 255// ProcResources indicates the set of resources consumed by the write. 256// Optionally, ResourceCycles indicates the number of cycles the 257// resource is consumed. Each ResourceCycles item is paired with the 258// ProcResource item at the same position in its list. Since 259// ResourceCycles are rarely specialized, the list may be 260// incomplete. By default, resources are consumed for a single cycle, 261// regardless of latency, which models a fully pipelined processing 262// unit. A value of 0 for ResourceCycles means that the resource must 263// be available but is not consumed, which is only relevant for 264// unbuffered resources. 265// 266// By default, each SchedWrite takes one micro-op, which is counted 267// against the processor's IssueWidth limit. If an instruction can 268// write multiple registers with a single micro-op, the subtarget 269// should define one of the writes to be zero micro-ops. If a 270// subtarget requires multiple micro-ops to write a single result, it 271// should either override the write's NumMicroOps to be greater than 1 272// or require additional writes. Extra writes can be required either 273// by defining a WriteSequence, or simply listing extra writes in the 274// instruction's list of writers beyond the number of "def" 275// operands. The scheduler assumes that all micro-ops must be 276// dispatched in the same cycle. These micro-ops may be required to 277// begin or end the current dispatch group. 278class WriteRes<SchedWrite write, list<ProcResourceKind> resources> 279 : ProcWriteResources<resources> { 280 SchedWrite WriteType = write; 281} 282 283// Directly name a set of WriteResources defining a new SchedWrite 284// type at the same time. This class is unaware of its SchedModel so 285// must be referenced by InstRW or ItinRW. 286class SchedWriteRes<list<ProcResourceKind> resources> : SchedWrite, 287 ProcWriteResources<resources>; 288 289// Define values common to ReadAdvance and SchedReadAdvance. 290// 291// SchedModel ties these resources to a processor. 292class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> { 293 int Cycles = cycles; 294 list<SchedWrite> ValidWrites = writes; 295 // Allow a processor to mark some scheduling classes as unsupported 296 // for stronger verification. 297 bit Unsupported = 0; 298 SchedMachineModel SchedModel = ?; 299} 300 301// A processor may define a ReadAdvance associated with a SchedRead 302// to reduce latency of a prior write by N cycles. A negative advance 303// effectively increases latency, which may be used for cross-domain 304// stalls. 305// 306// A ReadAdvance may be associated with a list of SchedWrites 307// to implement pipeline bypass. The Writes list may be empty to 308// indicate operands that are always read this number of Cycles later 309// than a normal register read, allowing the read's parent instruction 310// to issue earlier relative to the writer. 311class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []> 312 : ProcReadAdvance<cycles, writes> { 313 SchedRead ReadType = read; 314} 315 316// Directly associate a new SchedRead type with a delay and optional 317// pipeline bypess. For use with InstRW or ItinRW. 318class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead, 319 ProcReadAdvance<cycles, writes>; 320 321// Define SchedRead defaults. Reads seldom need special treatment. 322def ReadDefault : SchedRead; 323def NoReadAdvance : SchedReadAdvance<0>; 324 325// Define shared code that will be in the same scope as all 326// SchedPredicates. Available variables are: 327// (const MachineInstr *MI, const TargetSchedModel *SchedModel) 328class PredicateProlog<code c> { 329 code Code = c; 330} 331 332// Define a predicate to determine which SchedVariant applies to a 333// particular MachineInstr. The code snippet is used as an 334// if-statement's expression. Available variables are MI, SchedModel, 335// and anything defined in a PredicateProlog. 336// 337// SchedModel silences warnings but is ignored. 338class SchedPredicate<code pred> { 339 SchedMachineModel SchedModel = ?; 340 code Predicate = pred; 341} 342def NoSchedPred : SchedPredicate<[{true}]>; 343 344// Associate a predicate with a list of SchedReadWrites. By default, 345// the selected SchedReadWrites are still associated with a single 346// operand and assumed to execute sequentially with additive 347// latency. However, if the parent SchedWriteVariant or 348// SchedReadVariant is marked "Variadic", then each Selected 349// SchedReadWrite is mapped in place to the instruction's variadic 350// operands. In this case, latency is not additive. If the current Variant 351// is already part of a Sequence, then that entire chain leading up to 352// the Variant is distributed over the variadic operands. 353class SchedVar<SchedPredicate pred, list<SchedReadWrite> selected> { 354 SchedPredicate Predicate = pred; 355 list<SchedReadWrite> Selected = selected; 356} 357 358// SchedModel silences warnings but is ignored. 359class SchedVariant<list<SchedVar> variants> { 360 list<SchedVar> Variants = variants; 361 bit Variadic = 0; 362 SchedMachineModel SchedModel = ?; 363} 364 365// A SchedWriteVariant is a single SchedWrite type that maps to a list 366// of SchedWrite types under the conditions defined by its predicates. 367// 368// A Variadic write is expanded to cover multiple "def" operands. The 369// SchedVariant's Expansion list is then interpreted as one write 370// per-operand instead of the usual sequential writes feeding a single 371// operand. 372class SchedWriteVariant<list<SchedVar> variants> : SchedWrite, 373 SchedVariant<variants> { 374} 375 376// A SchedReadVariant is a single SchedRead type that maps to a list 377// of SchedRead types under the conditions defined by its predicates. 378// 379// A Variadic write is expanded to cover multiple "readsReg" operands as 380// explained above. 381class SchedReadVariant<list<SchedVar> variants> : SchedRead, 382 SchedVariant<variants> { 383} 384 385// Map a set of opcodes to a list of SchedReadWrite types. This allows 386// the subtarget to easily override specific operations. 387// 388// SchedModel ties this opcode mapping to a processor. 389class InstRW<list<SchedReadWrite> rw, dag instrlist> { 390 list<SchedReadWrite> OperandReadWrites = rw; 391 dag Instrs = instrlist; 392 SchedMachineModel SchedModel = ?; 393} 394 395// Map a set of itinerary classes to SchedReadWrite resources. This is 396// used to bootstrap a target (e.g. ARM) when itineraries already 397// exist and changing InstrInfo is undesirable. 398// 399// SchedModel ties this ItineraryClass mapping to a processor. 400class ItinRW<list<SchedReadWrite> rw, list<InstrItinClass> iic> { 401 list<InstrItinClass> MatchedItinClasses = iic; 402 list<SchedReadWrite> OperandReadWrites = rw; 403 SchedMachineModel SchedModel = ?; 404} 405 406// Alias a target-defined SchedReadWrite to a processor specific 407// SchedReadWrite. This allows a subtarget to easily map a 408// SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or 409// SchedReadVariant. 410// 411// SchedModel will usually be provided by surrounding let statement 412// and ties this SchedAlias mapping to a processor. 413class SchedAlias<SchedReadWrite match, SchedReadWrite alias> { 414 SchedReadWrite MatchRW = match; 415 SchedReadWrite AliasRW = alias; 416 SchedMachineModel SchedModel = ?; 417} 418