TargetSubtargetInfo.h revision 38e61122f27a8ca4ef0578eaf6dc5242880d2918
1//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subtarget options of a Target machine. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 15#define LLVM_TARGET_TARGETSUBTARGETINFO_H 16 17#include "llvm/MC/MCSubtargetInfo.h" 18#include "llvm/Support/CodeGen.h" 19 20namespace llvm { 21 22class MachineFunction; 23class MachineInstr; 24class SDep; 25class SUnit; 26class TargetRegisterClass; 27class TargetSchedModel; 28struct MachineSchedPolicy; 29template <typename T> class SmallVectorImpl; 30 31//===----------------------------------------------------------------------===// 32/// 33/// TargetSubtargetInfo - Generic base class for all target subtargets. All 34/// Target-specific options that control code generation and printing should 35/// be exposed through a TargetSubtargetInfo-derived class. 36/// 37class TargetSubtargetInfo : public MCSubtargetInfo { 38 TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 39 void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 40protected: // Can only create subclasses... 41 TargetSubtargetInfo(); 42public: 43 // AntiDepBreakMode - Type of anti-dependence breaking that should 44 // be performed before post-RA scheduling. 45 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 46 typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; 47 48 virtual ~TargetSubtargetInfo(); 49 50 /// Resolve a SchedClass at runtime, where SchedClass identifies an 51 /// MCSchedClassDesc with the isVariant property. This may return the ID of 52 /// another variant SchedClass, but repeated invocation must quickly terminate 53 /// in a nonvariant SchedClass. 54 virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, 55 const TargetSchedModel* SchedModel) const { 56 return 0; 57 } 58 59 /// \brief True if the subtarget should run MachineScheduler after aggressive 60 /// coalescing. 61 /// 62 /// This currently replaces the SelectionDAG scheduler with the "source" order 63 /// scheduler. It does not yet disable the postRA scheduler. 64 virtual bool enableMachineScheduler() const; 65 66 /// \brief Override generic scheduling policy within a region. 67 /// 68 /// This is a convenient way for targets that don't provide any custom 69 /// scheduling heuristics (no custom MachineSchedStrategy) to make 70 /// changes to the generic scheduling policy. 71 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, 72 MachineInstr *begin, 73 MachineInstr *end, 74 unsigned NumRegionInstrs) const {} 75 76 // enablePostRAScheduler - If the target can benefit from post-regalloc 77 // scheduling and the specified optimization level meets the requirement 78 // return true to enable post-register-allocation scheduling. In 79 // CriticalPathRCs return any register classes that should only be broken 80 // if on the critical path. 81 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 82 AntiDepBreakMode& Mode, 83 RegClassVector& CriticalPathRCs) const; 84 // adjustSchedDependency - Perform target specific adjustments to 85 // the latency of a schedule dependency. 86 virtual void adjustSchedDependency(SUnit *def, SUnit *use, 87 SDep& dep) const { } 88 89 /// \brief Enable use of alias analysis during code generation (during MI 90 /// scheduling, DAGCombine, etc.). 91 virtual bool useAA() const; 92 93 /// \brief Reset the features for the subtarget. 94 virtual void resetSubtargetFeatures(const MachineFunction *MF) { } 95}; 96 97} // End llvm namespace 98 99#endif 100