TargetSubtargetInfo.h revision b6ac11cd03e9dd97b45dc97787171f942ef8e344 
1//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subtarget options of a Target machine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15#define LLVM_TARGET_TARGETSUBTARGETINFO_H
16
17#include "llvm/MC/MCSubtargetInfo.h"
18#include "llvm/Support/CodeGen.h"
19
20namespace llvm {
21
22class MachineFunction;
23class MachineInstr;
24class SDep;
25class SUnit;
26class TargetRegisterClass;
27class TargetSchedModel;
28struct MachineSchedPolicy;
29template <typename T> class SmallVectorImpl;
30
31//===----------------------------------------------------------------------===//
32///
33/// TargetSubtargetInfo - Generic base class for all target subtargets.  All
34/// Target-specific options that control code generation and printing should
35/// be exposed through a TargetSubtargetInfo-derived class.
36///
37class TargetSubtargetInfo : public MCSubtargetInfo {
38  TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
39  void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
40protected: // Can only create subclasses...
41  TargetSubtargetInfo();
42public:
43  // AntiDepBreakMode - Type of anti-dependence breaking that should
44  // be performed before post-RA scheduling.
45  typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
46  typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector;
47
48  virtual ~TargetSubtargetInfo();
49
50  /// Resolve a SchedClass at runtime, where SchedClass identifies an
51  /// MCSchedClassDesc with the isVariant property. This may return the ID of
52  /// another variant SchedClass, but repeated invocation must quickly terminate
53  /// in a nonvariant SchedClass.
54  virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,
55                                     const TargetSchedModel* SchedModel) const {
56    return 0;
57  }
58
59  /// \brief Temporary API to test migration to MI scheduler.
60  bool useMachineScheduler() const;
61
62  /// \brief True if the subtarget should run MachineScheduler after aggressive
63  /// coalescing.
64  ///
65  /// This currently replaces the SelectionDAG scheduler with the "source" order
66  /// scheduler. It does not yet disable the postRA scheduler.
67  virtual bool enableMachineScheduler() const;
68
69  /// \brief Override generic scheduling policy within a region.
70  ///
71  /// This is a convenient way for targets that don't provide any custom
72  /// scheduling heuristics (no custom MachineSchedStrategy) to make
73  /// changes to the generic scheduling policy.
74  virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
75                                   MachineInstr *begin,
76                                   MachineInstr *end,
77                                   unsigned NumRegionInstrs) const {}
78
79  // enablePostRAScheduler - If the target can benefit from post-regalloc
80  // scheduling and the specified optimization level meets the requirement
81  // return true to enable post-register-allocation scheduling. In
82  // CriticalPathRCs return any register classes that should only be broken
83  // if on the critical path.
84  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
85                                     AntiDepBreakMode& Mode,
86                                     RegClassVector& CriticalPathRCs) const;
87  // adjustSchedDependency - Perform target specific adjustments to
88  // the latency of a schedule dependency.
89  virtual void adjustSchedDependency(SUnit *def, SUnit *use,
90                                     SDep& dep) const { }
91
92  /// \brief Enable use of alias analysis during code generation (during MI
93  /// scheduling, DAGCombine, etc.).
94  virtual bool useAA() const;
95
96  /// \brief Reset the features for the subtarget.
97  virtual void resetSubtargetFeatures(const MachineFunction *MF) { }
98};
99
100} // End llvm namespace
101
102#endif
103